NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_21_RX_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (144/144)	100.0 % (21/21)	N.A.	N.A.	100.0 % (194/194)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_21_RX_INST

100.0 % (15/15)

100.0 % (14/14)

100.0 % (144/144)

100.0 % (21/21)

N.A.

100.0 % (194/194)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 6274829
Threshold: 1

If statement on lines 154 to 162:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 13446942
Threshold: 1

Signal assignment statement on line 155:

155: crc_d <= (others => '0');
Count: 210470
Threshold: 1

Signal assignment statement on line 156:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 210470
Threshold: 1

Signal assignment statement on lines 158 to 159:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 6573711
Threshold: 1

Signal assignment statement on line 161:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 6662761
Threshold: 1

If statement on lines 165 to 167:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 23016173
Threshold: 1

Signal assignment statement on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 113459
Threshold: 1

Signal assignment statement on line 166:

166: '1' when (enable = '1' and trig = '1') else
Count: 6916065
Threshold: 1

Signal assignment statement on line 167:

167: '0';
Count: 15986649
Threshold: 1

If statement on lines 174 to 180:

174:        if (res_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 175:

175: crc_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 177 to 179:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 178:

178: crc_q <= crc_d;
Count: 6989189
Threshold: 1

Signal assignment statement on line 184:

184: crc <= crc_q;
Count: 6946656
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	210470	1
Bin	False	13236472	1

"if" / "when" / "else" condition on line 157:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	6573711	1
Bin	False	6662761	1

"if" / "when" / "else" condition on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	113459	1
Bin	False	22902714	1

"if" / "when" / "else" condition on line 166:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6916065	1
Bin	False	15986649	1

"if" / "when" / "else" condition on line 174:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 176:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 177:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	6989189	1
Bin	False	536802489	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INIT_VECT_MSB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CRC

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1747719	1
Bin	(20)	1	0	1749311	1
Bin	(19)	0	1	1699622	1
Bin	(19)	1	0	1701219	1
Bin	(18)	0	1	1716066	1
Bin	(18)	1	0	1717663	1
Bin	(17)	0	1	1729728	1
Bin	(17)	1	0	1731328	1
Bin	(16)	0	1	1743409	1
Bin	(16)	1	0	1745008	1
Bin	(15)	0	1	1756358	1
Bin	(15)	1	0	1757957	1
Bin	(14)	0	1	1768901	1
Bin	(14)	1	0	1770498	1
Bin	(13)	0	1	1783918	1
Bin	(13)	1	0	1785513	1
Bin	(12)	0	1	1732017	1
Bin	(12)	1	0	1733614	1
Bin	(11)	0	1	1745487	1
Bin	(11)	1	0	1747087	1
Bin	(10)	0	1	1733386	1
Bin	(10)	1	0	1734982	1
Bin	(9)	0	1	1746619	1
Bin	(9)	1	0	1748216	1
Bin	(8)	0	1	1761088	1
Bin	(8)	1	0	1762684	1
Bin	(7)	0	1	1776191	1
Bin	(7)	1	0	1777791	1
Bin	(6)	0	1	1709060	1
Bin	(6)	1	0	1710658	1
Bin	(5)	0	1	1723265	1
Bin	(5)	1	0	1724863	1
Bin	(4)	0	1	1736710	1
Bin	(4)	1	0	1738310	1
Bin	(3)	0	1	1762520	1
Bin	(3)	1	0	1764117	1
Bin	(2)	0	1	1758156	1
Bin	(2)	1	0	1759752	1
Bin	(1)	0	1	1770759	1
Bin	(1)	1	0	1772359	1
Bin	(0)	0	1	1784893	1
Bin	(0)	1	0	1786489	1

Signal:

CRC_Q

	Element	From	To	Count	Threshold
Bin	(20)	0	1	3529153	1
Bin	(20)	1	0	3415902	1
Bin	(19)	0	1	1699622	1
Bin	(19)	1	0	1708753	1
Bin	(18)	0	1	1716066	1
Bin	(18)	1	0	1724971	1
Bin	(17)	0	1	1729728	1
Bin	(17)	1	0	1740156	1
Bin	(16)	0	1	1743409	1
Bin	(16)	1	0	1753713	1
Bin	(15)	0	1	1756358	1
Bin	(15)	1	0	1766257	1
Bin	(14)	0	1	1768901	1
Bin	(14)	1	0	1778926	1
Bin	(13)	0	1	1783918	1
Bin	(13)	1	0	1794332	1
Bin	(12)	0	1	1732017	1
Bin	(12)	1	0	1742022	1
Bin	(11)	0	1	1745487	1
Bin	(11)	1	0	1754672	1
Bin	(10)	0	1	1733386	1
Bin	(10)	1	0	1743680	1
Bin	(9)	0	1	1746619	1
Bin	(9)	1	0	1755832	1
Bin	(8)	0	1	1761088	1
Bin	(8)	1	0	1770213	1
Bin	(7)	0	1	1776191	1
Bin	(7)	1	0	1786212	1
Bin	(6)	0	1	1709060	1
Bin	(6)	1	0	1718295	1
Bin	(5)	0	1	1723265	1
Bin	(5)	1	0	1733308	1
Bin	(4)	0	1	1736710	1
Bin	(4)	1	0	1745468	1
Bin	(3)	0	1	1762520	1
Bin	(3)	1	0	1771448	1
Bin	(2)	0	1	1758156	1
Bin	(2)	1	0	1767502	1
Bin	(1)	0	1	1770759	1
Bin	(1)	1	0	1779940	1
Bin	(0)	0	1	1784893	1
Bin	(0)	1	0	1793658	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	3136610	1
Bin	1	0	3135017	1

Signal:

CRC_D

	Element	From	To	Count	Threshold
Bin	(20)	0	1	6736415	1
Bin	(20)	1	0	6604001	1
Bin	(19)	0	1	1716068	1
Bin	(19)	1	0	1798471	1
Bin	(18)	0	1	1729732	1
Bin	(18)	1	0	1809634	1
Bin	(17)	0	1	1743411	1
Bin	(17)	1	0	1823080	1
Bin	(16)	0	1	1756361	1
Bin	(16)	1	0	1836657	1
Bin	(15)	0	1	1768903	1
Bin	(15)	1	0	1846056	1
Bin	(14)	0	1	1783920	1
Bin	(14)	1	0	1868817	1
Bin	(13)	0	1	4855871	1
Bin	(13)	1	0	4941378	1
Bin	(12)	0	1	1745488	1
Bin	(12)	1	0	1821998	1
Bin	(11)	0	1	4856168	1
Bin	(11)	1	0	4946087	1
Bin	(10)	0	1	1746619	1
Bin	(10)	1	0	1824725	1
Bin	(9)	0	1	1761092	1
Bin	(9)	1	0	1837612	1
Bin	(8)	0	1	1776192	1
Bin	(8)	1	0	1853547	1
Bin	(7)	0	1	4831173	1
Bin	(7)	1	0	4911645	1
Bin	(6)	0	1	1723265	1
Bin	(6)	1	0	1800723	1
Bin	(5)	0	1	1736711	1
Bin	(5)	1	0	1810097	1
Bin	(4)	0	1	4886811	1
Bin	(4)	1	0	4977332	1
Bin	(3)	0	1	4881563	1
Bin	(3)	1	0	4969798	1
Bin	(2)	0	1	1770762	1
Bin	(2)	1	0	1842974	1
Bin	(1)	0	1	1784897	1
Bin	(1)	1	0	1862536	1
Bin	(0)	0	1	3137517	1
Bin	(0)	1	0	3225638	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	7029524	1
Bin	1	0	7031125	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

 data_in xor crc_q(G_CRC_WIDTH - 1) 
 <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1547228	1
Bin	'0'	'1'	1543378	1
Bin	'1'	'0'	1593232	1
Bin	'1'	'1'	1587789	1

"=" expression on line 154:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	13236472	1
Bin	True	210470	1

"=" expression on line 157:

crc_nxt = '1'

	Evaluated to	Count	Threshold
Bin	False	6662761	1
Bin	True	6573711	1

"=" expression on line 165:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	22902714	1
Bin	True	113459	1

"and" expression on line 166:

 enable = '1' and trig = '1' 
 <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4473081	1
Bin	True	False	6919110	1
Bin	True	True	6916065	1

"=" expression on line 166:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	9067539	1
Bin	True	13835175	1

"=" expression on line 166:

trig = '1'

	Evaluated to	Count	Threshold
Bin	False	11513568	1
Bin	True	11389146	1

"=" expression on line 174:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 177:

crc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	536802489	1
Bin	True	6989189	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_21_RX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

If statement on lines 154 to 162:

Signal assignment statement on line 155:

Signal assignment statement on line 156:

Signal assignment statement on lines 158 to 159:

Signal assignment statement on line 161:

If statement on lines 165 to 167:

Signal assignment statement on line 165:

Signal assignment statement on line 166:

Signal assignment statement on line 167:

If statement on lines 174 to 180:

Signal assignment statement on line 175:

If statement on lines 177 to 179:

Signal assignment statement on line 178:

Signal assignment statement on line 184:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 176:

"if" / "when" / "else" condition on line 177:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

"=" expression on line 154:

"=" expression on line 157:

"=" expression on line 165:

"and" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 174:

"=" expression on line 177:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: