NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_21_RX_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (144/144)	100.0 % (21/21)	N.A.	N.A.	100.0 % (193/193)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 6253281
Threshold: 1

If statement:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 13400672
Threshold: 1

Signal assignment statement:

155: crc_d <= (others => '0');
Count: 207890
Threshold: 1

Signal assignment statement:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 207890
Threshold: 1

Signal assignment statement:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 6567241
Threshold: 1

Signal assignment statement:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 6625541
Threshold: 1

If statement:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 22330801
Threshold: 1

Signal assignment statement:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 112514
Threshold: 1

Signal assignment statement:

166: '1' when (enable = '1' and trig = '1') else
Count: 6895167
Threshold: 1

Signal assignment statement:

167: '0';
Count: 15323120
Threshold: 1

If statement:

174:        if (res_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

175: crc_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

178: crc_q <= crc_d;
Count: 6966803
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	207890	1
Bin	False	13192782	1

"if" / "when" / "else" condition:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	6567241	1
Bin	False	6625541	1

"if" / "when" / "else" condition:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	112514	1
Bin	False	22218287	1

"if" / "when" / "else" condition:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6895167	1
Bin	False	15323120	1

"if" / "when" / "else" condition:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	6966803	1
Bin	False	519407497	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

DATA_IN

	From	To	Count	Threshold
Bin	0	1	1387496	1
Bin	1	0	1385896	1

Port:

TRIG

	From	To	Count	Threshold
Bin	0	1	11043148	1
Bin	1	0	11044748	1

Port:

ENABLE

	From	To	Count	Threshold
Bin	0	1	61272	1
Bin	1	0	62872	1

Port:

INIT_VECT_MSB

	From	To	Count	Threshold
Bin	0	1	1730	1
Bin	1	0	1730	1

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold
Bin	0	1	112514	1
Bin	1	0	114114	1

Port:

CRC(20)

	From	To	Count	Threshold
Bin	0	1	1738348	1
Bin	1	0	1739941	1

Port:

CRC(19)

	From	To	Count	Threshold
Bin	0	1	1694492	1
Bin	1	0	1696089	1

Port:

CRC(18)

	From	To	Count	Threshold
Bin	0	1	1709182	1
Bin	1	0	1710780	1

Port:

CRC(17)

	From	To	Count	Threshold
Bin	0	1	1723668	1
Bin	1	0	1725266	1

Port:

CRC(16)

	From	To	Count	Threshold
Bin	0	1	1736428	1
Bin	1	0	1738027	1

Port:

CRC(15)

	From	To	Count	Threshold
Bin	0	1	1749537	1
Bin	1	0	1751135	1

Port:

CRC(14)

	From	To	Count	Threshold
Bin	0	1	1762507	1
Bin	1	0	1764105	1

Port:

CRC(13)

	From	To	Count	Threshold
Bin	0	1	1777446	1
Bin	1	0	1779044	1

Port:

CRC(12)

	From	To	Count	Threshold
Bin	0	1	1718146	1
Bin	1	0	1719743	1

Port:

CRC(11)

	From	To	Count	Threshold
Bin	0	1	1733293	1
Bin	1	0	1734892	1

Port:

CRC(10)

	From	To	Count	Threshold
Bin	0	1	1723964	1
Bin	1	0	1725560	1

Port:

CRC(9)

	From	To	Count	Threshold
Bin	0	1	1737663	1
Bin	1	0	1739261	1

Port:

CRC(8)

	From	To	Count	Threshold
Bin	0	1	1753350	1
Bin	1	0	1754945	1

Port:

CRC(7)

	From	To	Count	Threshold
Bin	0	1	1768568	1
Bin	1	0	1770168	1

Port:

CRC(6)

	From	To	Count	Threshold
Bin	0	1	1710305	1
Bin	1	0	1711902	1

Port:

CRC(5)

	From	To	Count	Threshold
Bin	0	1	1724000	1
Bin	1	0	1725597	1

Port:

CRC(4)

	From	To	Count	Threshold
Bin	0	1	1737131	1
Bin	1	0	1738729	1

Port:

CRC(3)

	From	To	Count	Threshold
Bin	0	1	1753239	1
Bin	1	0	1754837	1

Port:

CRC(2)

	From	To	Count	Threshold
Bin	0	1	1752204	1
Bin	1	0	1753800	1

Port:

CRC(1)

	From	To	Count	Threshold
Bin	0	1	1764851	1
Bin	1	0	1766449	1

Port:

CRC(0)

	From	To	Count	Threshold
Bin	0	1	1777838	1
Bin	1	0	1779434	1

Signal:

CRC_Q(20)

	From	To	Count	Threshold
Bin	0	1	3522340	1
Bin	1	0	3399886	1

Signal:

CRC_Q(19)

	From	To	Count	Threshold
Bin	0	1	1694492	1
Bin	1	0	1703701	1

Signal:

CRC_Q(18)

	From	To	Count	Threshold
Bin	0	1	1709182	1
Bin	1	0	1718120	1

Signal:

CRC_Q(17)

	From	To	Count	Threshold
Bin	0	1	1723668	1
Bin	1	0	1734074	1

Signal:

CRC_Q(16)

	From	To	Count	Threshold
Bin	0	1	1736428	1
Bin	1	0	1746718	1

Signal:

CRC_Q(15)

	From	To	Count	Threshold
Bin	0	1	1749537	1
Bin	1	0	1759517	1

Signal:

CRC_Q(14)

	From	To	Count	Threshold
Bin	0	1	1762507	1
Bin	1	0	1772536	1

Signal:

CRC_Q(13)

	From	To	Count	Threshold
Bin	0	1	1777446	1
Bin	1	0	1787810	1

Signal:

CRC_Q(12)

	From	To	Count	Threshold
Bin	0	1	1718146	1
Bin	1	0	1728252	1

Signal:

CRC_Q(11)

	From	To	Count	Threshold
Bin	0	1	1733293	1
Bin	1	0	1742473	1

Signal:

CRC_Q(10)

	From	To	Count	Threshold
Bin	0	1	1723964	1
Bin	1	0	1734476	1

Signal:

CRC_Q(9)

	From	To	Count	Threshold
Bin	0	1	1737663	1
Bin	1	0	1746789	1

Signal:

CRC_Q(8)

	From	To	Count	Threshold
Bin	0	1	1753350	1
Bin	1	0	1762652	1

Signal:

CRC_Q(7)

	From	To	Count	Threshold
Bin	0	1	1768568	1
Bin	1	0	1778541	1

Signal:

CRC_Q(6)

	From	To	Count	Threshold
Bin	0	1	1710305	1
Bin	1	0	1719469	1

Signal:

CRC_Q(5)

	From	To	Count	Threshold
Bin	0	1	1724000	1
Bin	1	0	1733969	1

Signal:

CRC_Q(4)

	From	To	Count	Threshold
Bin	0	1	1737131	1
Bin	1	0	1745894	1

Signal:

CRC_Q(3)

	From	To	Count	Threshold
Bin	0	1	1753239	1
Bin	1	0	1762200	1

Signal:

CRC_Q(2)

	From	To	Count	Threshold
Bin	0	1	1752204	1
Bin	1	0	1761452	1

Signal:

CRC_Q(1)

	From	To	Count	Threshold
Bin	0	1	1764851	1
Bin	1	0	1773934	1

Signal:

CRC_Q(0)

	From	To	Count	Threshold
Bin	0	1	1777838	1
Bin	1	0	1786617	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	3125837	1
Bin	1	0	3124244	1

Signal:

CRC_D(20)

	From	To	Count	Threshold
Bin	0	1	6721045	1
Bin	1	0	6574748	1

Signal:

CRC_D(19)

	From	To	Count	Threshold
Bin	0	1	1709183	1
Bin	1	0	1786919	1

Signal:

CRC_D(18)

	From	To	Count	Threshold
Bin	0	1	1723671	1
Bin	1	0	1805180	1

Signal:

CRC_D(17)

	From	To	Count	Threshold
Bin	0	1	1736433	1
Bin	1	0	1813245	1

Signal:

CRC_D(16)

	From	To	Count	Threshold
Bin	0	1	1749542	1
Bin	1	0	1830264	1

Signal:

CRC_D(15)

	From	To	Count	Threshold
Bin	0	1	1762512	1
Bin	1	0	1837643	1

Signal:

CRC_D(14)

	From	To	Count	Threshold
Bin	0	1	1777450	1
Bin	1	0	1858870	1

Signal:

CRC_D(13)

	From	To	Count	Threshold
Bin	0	1	4831380	1
Bin	1	0	4912133	1

Signal:

CRC_D(12)

	From	To	Count	Threshold
Bin	0	1	1733294	1
Bin	1	0	1814598	1

Signal:

CRC_D(11)

	From	To	Count	Threshold
Bin	0	1	4836787	1
Bin	1	0	4924884	1

Signal:

CRC_D(10)

	From	To	Count	Threshold
Bin	0	1	1737666	1
Bin	1	0	1811362	1

Signal:

CRC_D(9)

	From	To	Count	Threshold
Bin	0	1	1753356	1
Bin	1	0	1833335	1

Signal:

CRC_D(8)

	From	To	Count	Threshold
Bin	0	1	1768569	1
Bin	1	0	1852598	1

Signal:

CRC_D(7)

	From	To	Count	Threshold
Bin	0	1	4824182	1
Bin	1	0	4911861	1

Signal:

CRC_D(6)

	From	To	Count	Threshold
Bin	0	1	1724002	1
Bin	1	0	1799845	1

Signal:

CRC_D(5)

	From	To	Count	Threshold
Bin	0	1	1737134	1
Bin	1	0	1808039	1

Signal:

CRC_D(4)

	From	To	Count	Threshold
Bin	0	1	4866949	1
Bin	1	0	4954437	1

Signal:

CRC_D(3)

	From	To	Count	Threshold
Bin	0	1	4864113	1
Bin	1	0	4945610	1

Signal:

CRC_D(2)

	From	To	Count	Threshold
Bin	0	1	1764853	1
Bin	1	0	1842257	1

Signal:

CRC_D(1)

	From	To	Count	Threshold
Bin	0	1	1777839	1
Bin	1	0	1854946	1

Signal:

CRC_D(0)

	From	To	Count	Threshold
Bin	0	1	3126700	1
Bin	1	0	3211233	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	7007681	1
Bin	1	0	7009281	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

150:    crc_nxt         <= data_in xor crc_q(G_CRC_WIDTH - 1); 
                           <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1536474	1
Bin	'0'	'1'	1547604	1
Bin	'1'	'0'	1578233	1
Bin	'1'	'1'	1587770	1

"=" expression

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	False	13192782	1
Bin	True	207890	1

"=" expression

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	False	6625541	1
Bin	True	6567241	1

"=" expression

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	False	22218287	1
Bin	True	112514	1

"=" expression

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	False	8424836	1
Bin	True	13793451	1

"=" expression

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	False	11170948	1
Bin	True	11047339	1

"and" expression

166:              '1' when (enable = '1' and trig = '1') else 
                            <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4152172	1
Bin	True	False	6898284	1
Bin	True	True	6895167	1

"=" expression

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	519407497	1
Bin	True	6966803	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_21_RX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

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If statement:

Signal assignment statement:

Signal assignment statement:

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If statement:

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Signal assignment statement:

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If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

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