NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_FILTER_A_INST	100.0 % (6/6)	100.0 % (2/2)	100.0 % (294/294)	100.0 % (5/5)	N.A.	N.A.	100.0 % (307/307)
BIT_FILTER_B_INST	100.0 % (6/6)	100.0 % (2/2)	100.0 % (294/294)	100.0 % (5/5)	N.A.	N.A.	100.0 % (307/307)
BIT_FILTER_C_INST	100.0 % (6/6)	100.0 % (2/2)	100.0 % (294/294)	100.0 % (5/5)	N.A.	N.A.	100.0 % (307/307)
RANGE_FILTER_INST	100.0 % (11/11)	100.0 % (2/2)	100.0 % (178/178)	100.0 % (12/12)	N.A.	N.A.	100.0 % (203/203)
FILT_SUP_GEN_TRUE	100.0 % (11/11)	100.0 % (10/10)	N.A.	100.0 % (30/30)	N.A.	N.A.	100.0 % (51/51)
FILT_SUP_GEN_FALSE	100.0 % (3/3)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (3/3)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST	100.0 % (37/37)	100.0 % (24/24)	100.0 % (654/654)	100.0 % (30/30)	N.A.	N.A.	100.0 % (745/745)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

242: int_data_ctrl <= rec_frame_type & rec_ident_type;
Count: 93194
Threshold: 1

Sequential statement:

245:    with int_data_ctrl select int_data_type <= 
246:        "0001" when "00",       --CAN Basic 
247:        "0010" when "01",       --CAN Extended 
248:        "0100" when "10",       --CAN FD Basic 
249:        "1000" when others;     --CAN Fd Extended

Count: 93194
Threshold: 1

Signal assignment statement:

246: "0001" when "00", --CAN Basic
Count: 38568
Threshold: 1

Signal assignment statement:

247: "0010" when "01", --CAN Extended
Count: 15760
Threshold: 1

Signal assignment statement:

248: "0100" when "10", --CAN FD Basic
Count: 28438
Threshold: 1

Signal assignment statement:

249: "1000" when others; --CAN Fd Extended
Count: 10428
Threshold: 1

Signal assignment statement:

253:    mask_filter_a <= mr_filter_control_fafe & mr_filter_control_fafb & 
254:                     mr_filter_control_fane & mr_filter_control_fanb;

Count: 5709
Threshold: 1

Signal assignment statement:

256:    mask_filter_b <= mr_filter_control_fbfe & mr_filter_control_fbfb & 
257:                     mr_filter_control_fbne & mr_filter_control_fbnb;

Count: 3824
Threshold: 1

Signal assignment statement:

259:    mask_filter_c <= mr_filter_control_fcfe & mr_filter_control_fcfb & 
260:                     mr_filter_control_fcne & mr_filter_control_fcnb;

Count: 3824
Threshold: 1

Signal assignment statement:

262:    mask_filter_range <= mr_filter_control_frfe & mr_filter_control_frfb & 
263:                         mr_filter_control_frne & mr_filter_control_frnb;

Count: 3222
Threshold: 1

If statement:

266:    filter_a_enable <= '1' when ((mask_filter_a and int_data_type) /= x"0") 
267:                           else 
268:                       '0';

Count: 97278
Threshold: 1

Signal assignment statement:

266: filter_a_enable <= '1' when ((mask_filter_a and int_data_type) /= x"0")
Count: 91173
Threshold: 1

Signal assignment statement:

268: '0';
Count: 6105
Threshold: 1

If statement:

270:    filter_b_enable <= '1' when ((mask_filter_b and int_data_type) /= x"0") 
271:                           else 
272:                       '0';

Count: 95418
Threshold: 1

Signal assignment statement:

270: filter_b_enable <= '1' when ((mask_filter_b and int_data_type) /= x"0")
Count: 3525
Threshold: 1

Signal assignment statement:

272: '0';
Count: 91893
Threshold: 1

If statement:

274:    filter_c_enable <= '1' when ((mask_filter_c and int_data_type) /= x"0") 
275:                           else 
276:                       '0';

Count: 95410
Threshold: 1

Signal assignment statement:

274: filter_c_enable <= '1' when ((mask_filter_c and int_data_type) /= x"0")
Count: 3499
Threshold: 1

Signal assignment statement:

276: '0';
Count: 91911
Threshold: 1

If statement:

278:    filter_range_enable <= '1' when ((mask_filter_range and int_data_type) /= x"0") 
279:                               else 
280:                           '0';

Count: 94816
Threshold: 1

Signal assignment statement:

278: filter_range_enable <= '1' when ((mask_filter_range and int_data_type) /= x"0")
Count: 3206
Threshold: 1

Signal assignment statement:

280: '0';
Count: 91610
Threshold: 1

If statement:

384:        if (res_n = '0') then 
385:            ident_valid_q <= '0'; 
386:        elsif rising_edge(clk_sys) then 
387:            ident_valid_q <= ident_valid_d; 
388:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

385: ident_valid_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

387: ident_valid_q <= ident_valid_d;
Count: 526374300
Threshold: 1

If statement:

394:    store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1') 
395:                            else 
396:                        '0';

Count: 80357
Threshold: 1

Signal assignment statement:

394: store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1')
Count: 26358
Threshold: 1

Signal assignment statement:

396: '0';
Count: 53999
Threshold: 1

If statement:

398:    store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1') 
399:                        else 
400:                    '0';

Count: 201111
Threshold: 1

Signal assignment statement:

398: store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1')
Count: 86336
Threshold: 1

Signal assignment statement:

400: '0';
Count: 114775
Threshold: 1

If statement:

402:    rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1') 
403:                       else 
404:                   '0';

Count: 55275
Threshold: 1

Signal assignment statement:

402: rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1')
Count: 13021
Threshold: 1

Signal assignment statement:

404: '0';
Count: 42254
Threshold: 1

If statement:

406:    rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1') 
407:                       else 
408:                   '0';

Count: 84965
Threshold: 1

Signal assignment statement:

406: rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1')
Count: 30820
Threshold: 1

Signal assignment statement:

408: '0';
Count: 54145
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

246: "0001" when "00", --CAN Basic

	Choice of	Count	Threshold
Bin	`"00"`	38568	1

"case" / "with" / "select" choice:

247: "0010" when "01", --CAN Extended

	Choice of	Count	Threshold
Bin	`"01"`	15760	1

"case" / "with" / "select" choice:

248: "0100" when "10", --CAN FD Basic

	Choice of	Count	Threshold
Bin	`"10"`	28438	1

"case" / "with" / "select" choice:

249: "1000" when others; --CAN Fd Extended

	Choice of	Count	Threshold
Bin	`others`	10428	1

"if" / "when" / "else" condition:

266: filter_a_enable <= '1' when ((mask_filter_a and int_data_type) /= x"0")

	Evaluated to	Count	Threshold
Bin	True	91173	1
Bin	False	6105	1

"if" / "when" / "else" condition:

270: filter_b_enable <= '1' when ((mask_filter_b and int_data_type) /= x"0")

	Evaluated to	Count	Threshold
Bin	True	3525	1
Bin	False	91893	1

"if" / "when" / "else" condition:

274: filter_c_enable <= '1' when ((mask_filter_c and int_data_type) /= x"0")

	Evaluated to	Count	Threshold
Bin	True	3499	1
Bin	False	91911	1

"if" / "when" / "else" condition:

278: filter_range_enable <= '1' when ((mask_filter_range and int_data_type) /= x"0")

	Evaluated to	Count	Threshold
Bin	True	3206	1
Bin	False	91610	1

"if" / "when" / "else" condition:

384: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

386: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

394: store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	True	26358	1
Bin	False	53999	1

"if" / "when" / "else" condition:

398: store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	True	86336	1
Bin	False	114775	1

"if" / "when" / "else" condition:

402: rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	True	13021	1
Bin	False	42254	1

"if" / "when" / "else" condition:

406: rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	True	30820	1
Bin	False	54145	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

MR_FILTER_CONTROL_FAFE

	From	To	Count	Threshold
Bin	0	1	2028	1
Bin	1	0	428	1

Port:

MR_FILTER_CONTROL_FAFB

	From	To	Count	Threshold
Bin	0	1	2059	1
Bin	1	0	459	1

Port:

MR_FILTER_CONTROL_FANE

	From	To	Count	Threshold
Bin	0	1	2028	1
Bin	1	0	428	1

Port:

MR_FILTER_CONTROL_FANB

	From	To	Count	Threshold
Bin	0	1	2051	1
Bin	1	0	451	1

Port:

MR_FILTER_CONTROL_FBFE

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_CONTROL_FBFB

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1707	1

Port:

MR_FILTER_CONTROL_FBNE

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_CONTROL_FBNB

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	1706	1

Port:

MR_FILTER_CONTROL_FCFE

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_CONTROL_FCFB

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1707	1

Port:

MR_FILTER_CONTROL_FCNE

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_CONTROL_FCNB

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	1706	1

Port:

MR_FILTER_CONTROL_FRFE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

MR_FILTER_CONTROL_FRFB

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	1606	1

Port:

MR_FILTER_CONTROL_FRNE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

MR_FILTER_CONTROL_FRNB

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	1606	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(28)

	From	To	Count	Threshold
Bin	0	1	412	1
Bin	1	0	2012	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(27)

	From	To	Count	Threshold
Bin	0	1	334	1
Bin	1	0	1934	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(26)

	From	To	Count	Threshold
Bin	0	1	358	1
Bin	1	0	1958	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(25)

	From	To	Count	Threshold
Bin	0	1	362	1
Bin	1	0	1962	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(24)

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1990	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(23)

	From	To	Count	Threshold
Bin	0	1	407	1
Bin	1	0	2007	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(22)

	From	To	Count	Threshold
Bin	0	1	387	1
Bin	1	0	1987	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(21)

	From	To	Count	Threshold
Bin	0	1	344	1
Bin	1	0	1944	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(20)

	From	To	Count	Threshold
Bin	0	1	376	1
Bin	1	0	1976	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(19)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	1974	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(18)

	From	To	Count	Threshold
Bin	0	1	412	1
Bin	1	0	2012	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(17)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	1709	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(16)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1677	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(15)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(14)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	1714	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(13)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	1691	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(12)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1707	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(11)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	1723	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(10)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	1856	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(9)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	1867	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(8)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	1867	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(7)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	1882	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(6)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	1843	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(5)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	1876	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(4)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	1866	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(3)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	1865	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(2)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	1874	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(1)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	1834	1

Port:

MR_FILTER_A_MASK_BIT_MASK_A_VAL(0)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	1896	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(28)

	From	To	Count	Threshold
Bin	0	1	786	1
Bin	1	0	2386	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(27)

	From	To	Count	Threshold
Bin	0	1	850	1
Bin	1	0	2450	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(26)

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	2368	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(25)

	From	To	Count	Threshold
Bin	0	1	738	1
Bin	1	0	2338	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(24)

	From	To	Count	Threshold
Bin	0	1	792	1
Bin	1	0	2392	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(23)

	From	To	Count	Threshold
Bin	0	1	782	1
Bin	1	0	2382	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(22)

	From	To	Count	Threshold
Bin	0	1	837	1
Bin	1	0	2437	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(21)

	From	To	Count	Threshold
Bin	0	1	822	1
Bin	1	0	2422	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(20)

	From	To	Count	Threshold
Bin	0	1	781	1
Bin	1	0	2381	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(19)

	From	To	Count	Threshold
Bin	0	1	816	1
Bin	1	0	2416	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(18)

	From	To	Count	Threshold
Bin	0	1	814	1
Bin	1	0	2414	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(17)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	1997	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(16)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	1997	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(15)

	From	To	Count	Threshold
Bin	0	1	407	1
Bin	1	0	2007	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(14)

	From	To	Count	Threshold
Bin	0	1	433	1
Bin	1	0	2033	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(13)

	From	To	Count	Threshold
Bin	0	1	409	1
Bin	1	0	2009	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(12)

	From	To	Count	Threshold
Bin	0	1	375	1
Bin	1	0	1975	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(11)

	From	To	Count	Threshold
Bin	0	1	458	1
Bin	1	0	2058	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(10)

	From	To	Count	Threshold
Bin	0	1	405	1
Bin	1	0	2005	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(9)

	From	To	Count	Threshold
Bin	0	1	385	1
Bin	1	0	1985	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(8)

	From	To	Count	Threshold
Bin	0	1	381	1
Bin	1	0	1981	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(7)

	From	To	Count	Threshold
Bin	0	1	399	1
Bin	1	0	1999	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(6)

	From	To	Count	Threshold
Bin	0	1	405	1
Bin	1	0	2005	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(5)

	From	To	Count	Threshold
Bin	0	1	415	1
Bin	1	0	2015	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(4)

	From	To	Count	Threshold
Bin	0	1	417	1
Bin	1	0	2017	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(3)

	From	To	Count	Threshold
Bin	0	1	407	1
Bin	1	0	2007	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(2)

	From	To	Count	Threshold
Bin	0	1	416	1
Bin	1	0	2016	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(1)

	From	To	Count	Threshold
Bin	0	1	378	1
Bin	1	0	1978	1

Port:

MR_FILTER_A_VAL_BIT_VAL_A_VAL(0)

	From	To	Count	Threshold
Bin	0	1	417	1
Bin	1	0	2017	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(28)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(27)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	1689	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(26)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1688	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(25)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	1713	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(24)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1692	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(23)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1676	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(22)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(21)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(20)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	1702	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(19)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(18)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1671	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(17)

	From	To	Count	Threshold
Bin	0	1	29	1
Bin	1	0	1629	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(16)

	From	To	Count	Threshold
Bin	0	1	28	1
Bin	1	0	1628	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(15)

	From	To	Count	Threshold
Bin	0	1	21	1
Bin	1	0	1621	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(14)

	From	To	Count	Threshold
Bin	0	1	39	1
Bin	1	0	1639	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(13)

	From	To	Count	Threshold
Bin	0	1	27	1
Bin	1	0	1627	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(12)

	From	To	Count	Threshold
Bin	0	1	33	1
Bin	1	0	1633	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(11)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	1622	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(10)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1670	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(9)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1661	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(8)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1656	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(7)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1677	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(6)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1662	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(5)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1663	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(4)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1666	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(3)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1654	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(2)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1665	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(1)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1662	1

Port:

MR_FILTER_B_MASK_BIT_MASK_B_VAL(0)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1681	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(28)

	From	To	Count	Threshold
Bin	0	1	186	1
Bin	1	0	1786	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(27)

	From	To	Count	Threshold
Bin	0	1	188	1
Bin	1	0	1788	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(26)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	1793	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(25)

	From	To	Count	Threshold
Bin	0	1	184	1
Bin	1	0	1784	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(24)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	1825	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(23)

	From	To	Count	Threshold
Bin	0	1	190	1
Bin	1	0	1790	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(22)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	1815	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(21)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	1810	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(20)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	1800	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(19)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	1805	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(18)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	1818	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(17)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(16)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	1718	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(15)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	1699	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(14)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1692	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(13)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(12)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1682	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(11)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1694	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(10)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	1721	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(9)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(8)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(7)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	1689	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(6)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(5)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(4)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1690	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(3)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	1713	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(2)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1704	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(1)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_B_VAL_BIT_VAL_B_VAL(0)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	1693	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(28)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1694	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(27)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	1699	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(26)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1688	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(25)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1682	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(24)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1690	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(23)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	1692	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(22)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	1722	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(21)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1677	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(20)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	1699	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(19)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1703	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(18)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1680	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(17)

	From	To	Count	Threshold
Bin	0	1	26	1
Bin	1	0	1626	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(16)

	From	To	Count	Threshold
Bin	0	1	36	1
Bin	1	0	1636	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(15)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(14)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(13)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1643	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(12)

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	1631	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(11)

	From	To	Count	Threshold
Bin	0	1	18	1
Bin	1	0	1618	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(10)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1680	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(9)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1659	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(8)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1673	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(7)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1696	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(6)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1656	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(5)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1676	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(4)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1671	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(3)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1660	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(2)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1675	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(1)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1661	1

Port:

MR_FILTER_C_MASK_BIT_MASK_C_VAL(0)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1662	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(28)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	1816	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(27)

	From	To	Count	Threshold
Bin	0	1	189	1
Bin	1	0	1789	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(26)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	1805	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(25)

	From	To	Count	Threshold
Bin	0	1	186	1
Bin	1	0	1786	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(24)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	1799	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(23)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	1816	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(22)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	1824	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(21)

	From	To	Count	Threshold
Bin	0	1	224	1
Bin	1	0	1824	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(20)

	From	To	Count	Threshold
Bin	0	1	199	1
Bin	1	0	1799	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(19)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	1802	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(18)

	From	To	Count	Threshold
Bin	0	1	196	1
Bin	1	0	1796	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(17)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	1715	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(16)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	1716	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(15)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1701	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(14)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	1717	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(13)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(12)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1704	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(11)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1694	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(10)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1680	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(9)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1685	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(8)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1704	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(7)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	1698	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(6)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	1695	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(5)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	1700	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(4)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	1712	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(3)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1696	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(2)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1704	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(1)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

MR_FILTER_C_VAL_BIT_VAL_C_VAL(0)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	1728	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	1602	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)

	From	To	Count	Threshold
Bin	0	1	1	1
Bin	1	0	1601	1

Port:

MR_SETTINGS_FDRF

	From	To	Count	Threshold
Bin	0	1	4	1
Bin	1	0	1604	1

Port:

MR_MODE_AFM

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1668	1

Port:

REC_IDENT(28)

	From	To	Count	Threshold
Bin	0	1	34332	1
Bin	1	0	30165	1

Port:

REC_IDENT(27)

	From	To	Count	Threshold
Bin	0	1	20951	1
Bin	1	0	16748	1

Port:

REC_IDENT(26)

	From	To	Count	Threshold
Bin	0	1	34995	1
Bin	1	0	29978	1

Port:

REC_IDENT(25)

	From	To	Count	Threshold
Bin	0	1	26409	1
Bin	1	0	21440	1

Port:

REC_IDENT(24)

	From	To	Count	Threshold
Bin	0	1	37621	1
Bin	1	0	32560	1

Port:

REC_IDENT(23)

	From	To	Count	Threshold
Bin	0	1	27574	1
Bin	1	0	22162	1

Port:

REC_IDENT(22)

	From	To	Count	Threshold
Bin	0	1	37576	1
Bin	1	0	32729	1

Port:

REC_IDENT(21)

	From	To	Count	Threshold
Bin	0	1	26623	1
Bin	1	0	21662	1

Port:

REC_IDENT(20)

	From	To	Count	Threshold
Bin	0	1	34131	1
Bin	1	0	30013	1

Port:

REC_IDENT(19)

	From	To	Count	Threshold
Bin	0	1	25018	1
Bin	1	0	20939	1

Port:

REC_IDENT(18)

	From	To	Count	Threshold
Bin	0	1	35861	1
Bin	1	0	31802	1

Port:

REC_IDENT(17)

	From	To	Count	Threshold
Bin	0	1	6676	1
Bin	1	0	77411	1

Port:

REC_IDENT(16)

	From	To	Count	Threshold
Bin	0	1	6481	1
Bin	1	0	76980	1

Port:

REC_IDENT(15)

	From	To	Count	Threshold
Bin	0	1	6016	1
Bin	1	0	75936	1

Port:

REC_IDENT(14)

	From	To	Count	Threshold
Bin	0	1	6457	1
Bin	1	0	77301	1

Port:

REC_IDENT(13)

	From	To	Count	Threshold
Bin	0	1	6203	1
Bin	1	0	75854	1

Port:

REC_IDENT(12)

	From	To	Count	Threshold
Bin	0	1	6655	1
Bin	1	0	77348	1

Port:

REC_IDENT(11)

	From	To	Count	Threshold
Bin	0	1	6116	1
Bin	1	0	76014	1

Port:

REC_IDENT(10)

	From	To	Count	Threshold
Bin	0	1	6759	1
Bin	1	0	77172	1

Port:

REC_IDENT(9)

	From	To	Count	Threshold
Bin	0	1	6340	1
Bin	1	0	76882	1

Port:

REC_IDENT(8)

	From	To	Count	Threshold
Bin	0	1	7191	1
Bin	1	0	78168	1

Port:

REC_IDENT(7)

	From	To	Count	Threshold
Bin	0	1	6170	1
Bin	1	0	76119	1

Port:

REC_IDENT(6)

	From	To	Count	Threshold
Bin	0	1	6636	1
Bin	1	0	77753	1

Port:

REC_IDENT(5)

	From	To	Count	Threshold
Bin	0	1	6122	1
Bin	1	0	76213	1

Port:

REC_IDENT(4)

	From	To	Count	Threshold
Bin	0	1	6712	1
Bin	1	0	78180	1

Port:

REC_IDENT(3)

	From	To	Count	Threshold
Bin	0	1	6213	1
Bin	1	0	76204	1

Port:

REC_IDENT(2)

	From	To	Count	Threshold
Bin	0	1	7044	1
Bin	1	0	78347	1

Port:

REC_IDENT(1)

	From	To	Count	Threshold
Bin	0	1	6316	1
Bin	1	0	75925	1

Port:

REC_IDENT(0)

	From	To	Count	Threshold
Bin	0	1	6757	1
Bin	1	0	77490	1

Port:

REC_IDENT_TYPE

	From	To	Count	Threshold
Bin	0	1	15760	1
Bin	1	0	17358	1

Port:

REC_FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	28440	1
Bin	1	0	30036	1

Port:

REC_IS_RTR

	From	To	Count	Threshold
Bin	0	1	22038	1
Bin	1	0	23636	1

Port:

REC_IVLD

	From	To	Count	Threshold
Bin	0	1	50520	1
Bin	1	0	52113	1

Port:

STORE_METADATA

	From	To	Count	Threshold
Bin	0	1	28520	1
Bin	1	0	30120	1

Port:

STORE_DATA

	From	To	Count	Threshold
Bin	0	1	88897	1
Bin	1	0	90497	1

Port:

REC_VALID

	From	To	Count	Threshold
Bin	0	1	15179	1
Bin	1	0	16779	1

Port:

REC_ABORT

	From	To	Count	Threshold
Bin	0	1	30824	1
Bin	1	0	32424	1

Port:

STORE_METADATA_F

	From	To	Count	Threshold
Bin	0	1	26358	1
Bin	1	0	27958	1

Port:

STORE_DATA_F

	From	To	Count	Threshold
Bin	0	1	86336	1
Bin	1	0	87936	1

Port:

REC_VALID_F

	From	To	Count	Threshold
Bin	0	1	13021	1
Bin	1	0	14621	1

Port:

REC_ABORT_F

	From	To	Count	Threshold
Bin	0	1	30820	1
Bin	1	0	32420	1

Signal:

INT_FILTER_A_VALID

	From	To	Count	Threshold
Bin	0	1	2084	1
Bin	1	0	3024	1

Signal:

INT_FILTER_B_VALID

	From	To	Count	Threshold
Bin	0	1	512	1
Bin	1	0	2112	1

Signal:

INT_FILTER_C_VALID

	From	To	Count	Threshold
Bin	0	1	523	1
Bin	1	0	2123	1

Signal:

INT_FILTER_RAN_VALID

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	1771	1

Signal:

MASK_FILTER_A(3)

	From	To	Count	Threshold
Bin	0	1	2028	1
Bin	1	0	428	1

Signal:

MASK_FILTER_A(2)

	From	To	Count	Threshold
Bin	0	1	2059	1
Bin	1	0	459	1

Signal:

MASK_FILTER_A(1)

	From	To	Count	Threshold
Bin	0	1	2028	1
Bin	1	0	428	1

Signal:

MASK_FILTER_A(0)

	From	To	Count	Threshold
Bin	0	1	2051	1
Bin	1	0	451	1

Signal:

MASK_FILTER_B(3)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Signal:

MASK_FILTER_B(2)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1707	1

Signal:

MASK_FILTER_B(1)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Signal:

MASK_FILTER_B(0)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	1706	1

Signal:

MASK_FILTER_C(3)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Signal:

MASK_FILTER_C(2)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	1707	1

Signal:

MASK_FILTER_C(1)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Signal:

MASK_FILTER_C(0)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	1706	1

Signal:

MASK_FILTER_RANGE(3)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

MASK_FILTER_RANGE(2)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	1606	1

Signal:

MASK_FILTER_RANGE(1)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

MASK_FILTER_RANGE(0)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	1606	1

Signal:

INT_DATA_TYPE(3)

	From	To	Count	Threshold
Bin	0	1	8828	1
Bin	1	0	8826	1

Signal:

INT_DATA_TYPE(2)

	From	To	Count	Threshold
Bin	0	1	28438	1
Bin	1	0	30036	1

Signal:

INT_DATA_TYPE(1)

	From	To	Count	Threshold
Bin	0	1	15760	1
Bin	1	0	17360	1

Signal:

INT_DATA_TYPE(0)

	From	To	Count	Threshold
Bin	0	1	38568	1
Bin	1	0	38572	1

Signal:

INT_DATA_CTRL(1)

	From	To	Count	Threshold
Bin	0	1	28440	1
Bin	1	0	30036	1

Signal:

INT_DATA_CTRL(0)

	From	To	Count	Threshold
Bin	0	1	15760	1
Bin	1	0	17358	1

Signal:

FILTER_A_ENABLE

	From	To	Count	Threshold
Bin	0	1	2598	1
Bin	1	0	998	1

Signal:

FILTER_B_ENABLE

	From	To	Count	Threshold
Bin	0	1	1868	1
Bin	1	0	1868	1

Signal:

FILTER_C_ENABLE

	From	To	Count	Threshold
Bin	0	1	1841	1
Bin	1	0	1841	1

Signal:

FILTER_RANGE_ENABLE

	From	To	Count	Threshold
Bin	0	1	1606	1
Bin	1	0	1606	1

Signal:

FILTER_RESULT

	From	To	Count	Threshold
Bin	0	1	3486	1
Bin	1	0	4426	1

Signal:

IDENT_VALID_D

	From	To	Count	Threshold
Bin	0	1	4426	1
Bin	1	0	2826	1

Signal:

IDENT_VALID_Q

	From	To	Count	Threshold
Bin	0	1	10863	1
Bin	1	0	10854	1

Signal:

DROP_RTR_FRAME

	From	To	Count	Threshold
Bin	0	1	4	1
Bin	1	0	1604	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

384: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

394: store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	51837	1
Bin	True	28520	1

"=" expression

394: store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	16778	1
Bin	True	63579	1

"and" expression

394:    store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1') 
                                      <-------LHS-------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	37221	1
Bin	True	False	2162	1
Bin	True	True	26358	1

"=" expression

398: store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	112214	1
Bin	True	88897	1

"=" expression

398: store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	17576	1
Bin	True	183535	1

"and" expression

398:    store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1') 
                                  <-----LHS------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	97199	1
Bin	True	False	2561	1
Bin	True	True	86336	1

"=" expression

402: rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	40096	1
Bin	True	15179	1

"=" expression

402: rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	16770	1
Bin	True	38505	1

"and" expression

402:    rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1') 
                                 <-----LHS----->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	25484	1
Bin	True	False	2158	1
Bin	True	True	13021	1

"=" expression

406: rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	54141	1
Bin	True	30824	1

"=" expression

406: rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	False	12462	1
Bin	True	72503	1

"and" expression

406:    rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1') 
                                 <-----LHS----->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	41683	1
Bin	True	False	4	1
Bin	True	True	30820	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

Sequential statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: