NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 15525
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 15525
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 496800
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 15525
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	797	1
Bin	1	0	1417	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	824	1
Bin	1	0	1444	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	888	1
Bin	1	0	1508	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	2429	1
Bin	1	0	3038	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	2410	1
Bin	1	0	3009	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	2341	1
Bin	1	0	2951	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	2351	1
Bin	1	0	2956	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	2251	1
Bin	1	0	2861	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	2638	1
Bin	1	0	3241	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	2750	1
Bin	1	0	3346	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	2473	1
Bin	1	0	3078	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	2365	1
Bin	1	0	2962	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	2495	1
Bin	1	0	3095	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	1523	1
Bin	1	0	2137	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	1651	1
Bin	1	0	2267	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	1565	1
Bin	1	0	2180	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	1605	1
Bin	1	0	2219	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	1539	1
Bin	1	0	2155	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	1729	1
Bin	1	0	2341	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	1747	1
Bin	1	0	2361	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	1696	1
Bin	1	0	2311	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	2507	1
Bin	1	0	3109	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	1680	1
Bin	1	0	2293	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	3152	1
Bin	1	0	3741	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	2395	1
Bin	1	0	2993	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	2387	1
Bin	1	0	2999	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	1721	1
Bin	1	0	2337	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	1906	1
Bin	1	0	2506	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	2312	1
Bin	1	0	2911	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	2184	1
Bin	1	0	2778	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	2823	1
Bin	1	0	3416	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	4119	1
Bin	1	0	3544	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	109206	1
Bin	'0'	'1'	36330	1
Bin	'1'	'0'	288953	1
Bin	'1'	'1'	41191	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(3).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

Loop statement:

Variable assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: