NVC code coverage report

NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)
SYNC_READ_GEN	100.0 % (2/2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST	100.0 % (1/1)	N.A.	100.0 % (1578/1578)	N.A.	N.A.	N.A.	100.0 % (1579/1579)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

191: int_read_data <= ram_memory(to_integer(unsigned(addr_B)));
Count: 109101
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13641406	1
Bin	1	0	13642066	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	2844	1
Bin	1	0	2844	1

Port:

ADDR_A(4)

	From	To	Count	Threshold
Bin	0	1	249177	1
Bin	1	0	24476309	1

Port:

ADDR_A(3)

	From	To	Count	Threshold
Bin	0	1	396315	1
Bin	1	0	24329131	1

Port:

ADDR_A(2)

	From	To	Count	Threshold
Bin	0	1	299383	1
Bin	1	0	24426521	1

Port:

ADDR_A(1)

	From	To	Count	Threshold
Bin	0	1	24183911	1
Bin	1	0	542807	1

Port:

ADDR_A(0)

	From	To	Count	Threshold
Bin	0	1	15922367	1
Bin	1	0	8806091	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	46503	1
Bin	1	0	47313	1

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	25826	1
Bin	1	0	746948	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	28125	1
Bin	1	0	744663	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	26617	1
Bin	1	0	746119	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	43526	1
Bin	1	0	729314	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	37131	1
Bin	1	0	735717	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	35466	1
Bin	1	0	737378	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	48636	1
Bin	1	0	724208	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	36191	1
Bin	1	0	736659	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	34962	1
Bin	1	0	737886	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	44024	1
Bin	1	0	728824	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	38311	1
Bin	1	0	734535	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	36729	1
Bin	1	0	736097	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	62608	1
Bin	1	0	710230	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	76422	1
Bin	1	0	696488	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	76216	1
Bin	1	0	696582	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	136306	1
Bin	1	0	636528	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	32795	1
Bin	1	0	740025	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	41285	1
Bin	1	0	731537	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	35707	1
Bin	1	0	737121	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	39715	1
Bin	1	0	733131	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	57878	1
Bin	1	0	714926	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	60791	1
Bin	1	0	712027	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	78521	1
Bin	1	0	694319	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	80173	1
Bin	1	0	692633	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	68290	1
Bin	1	0	704578	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	64556	1
Bin	1	0	708320	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	65430	1
Bin	1	0	707404	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	80291	1
Bin	1	0	692533	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	85667	1
Bin	1	0	687147	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	95190	1
Bin	1	0	677689	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	157097	1
Bin	1	0	615746	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	133139	1
Bin	1	0	639818	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	24721305	1
Bin	1	0	28617	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	24721613	1
Bin	1	0	28309	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	24633047	1
Bin	1	0	116875	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	24634059	1
Bin	1	0	115863	1

Port:

ADDR_B(4)

	From	To	Count	Threshold
Bin	0	1	10675	1
Bin	1	0	11335	1

Port:

ADDR_B(3)

	From	To	Count	Threshold
Bin	0	1	486	1
Bin	1	0	1146	1

Port:

ADDR_B(2)

	From	To	Count	Threshold
Bin	0	1	15816	1
Bin	1	0	16476	1

Port:

ADDR_B(1)

	From	To	Count	Threshold
Bin	0	1	13067	1
Bin	1	0	13067	1

Port:

ADDR_B(0)

	From	To	Count	Threshold
Bin	0	1	35808	1
Bin	1	0	36468	1

Port:

DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	973	1
Bin	1	0	1592	1

Port:

DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	1091	1
Bin	1	0	1711	1

Port:

DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	993	1
Bin	1	0	1612	1

Port:

DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	2718	1
Bin	1	0	3327	1

Port:

DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	2695	1
Bin	1	0	3296	1

Port:

DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	2787	1
Bin	1	0	3394	1

Port:

DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	2562	1
Bin	1	0	3169	1

Port:

DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	2692	1
Bin	1	0	3300	1

Port:

DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	3012	1
Bin	1	0	3615	1

Port:

DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	2766	1
Bin	1	0	3367	1

Port:

DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	3130	1
Bin	1	0	3728	1

Port:

DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	2846	1
Bin	1	0	3450	1

Port:

DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	3322	1
Bin	1	0	3922	1

Port:

DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	3063	1
Bin	1	0	3669	1

Port:

DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	2398	1
Bin	1	0	3013	1

Port:

DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	2168	1
Bin	1	0	2784	1

Port:

DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	1899	1
Bin	1	0	2508	1

Port:

DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	2448	1
Bin	1	0	3064	1

Port:

DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	2061	1
Bin	1	0	2674	1

Port:

DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	2487	1
Bin	1	0	3100	1

Port:

DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	2085	1
Bin	1	0	2696	1

Port:

DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	2481	1
Bin	1	0	3092	1

Port:

DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	3211	1
Bin	1	0	3810	1

Port:

DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	2183	1
Bin	1	0	2793	1

Port:

DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	4011	1
Bin	1	0	4597	1

Port:

DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	3294	1
Bin	1	0	3888	1

Port:

DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	3111	1
Bin	1	0	3719	1

Port:

DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	1852	1
Bin	1	0	2466	1

Port:

DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	2671	1
Bin	1	0	3265	1

Port:

DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	3234	1
Bin	1	0	3837	1

Port:

DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	2781	1
Bin	1	0	3377	1

Port:

DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	3526	1
Bin	1	0	4121	1

Signal:

RAM_MEMORY(0)(31)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	15982	1

Signal:

RAM_MEMORY(0)(30)

	From	To	Count	Threshold
Bin	0	1	215	1
Bin	1	0	16039	1

Signal:

RAM_MEMORY(0)(29)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16002	1

Signal:

RAM_MEMORY(0)(28)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	16125	1

Signal:

RAM_MEMORY(0)(27)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	16020	1

Signal:

RAM_MEMORY(0)(26)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	16097	1

Signal:

RAM_MEMORY(0)(25)

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	16146	1

Signal:

RAM_MEMORY(0)(24)

	From	To	Count	Threshold
Bin	0	1	196	1
Bin	1	0	16056	1

Signal:

RAM_MEMORY(0)(23)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	16236	1

Signal:

RAM_MEMORY(0)(22)

	From	To	Count	Threshold
Bin	0	1	175	1
Bin	1	0	16255	1

Signal:

RAM_MEMORY(0)(21)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16235	1

Signal:

RAM_MEMORY(0)(20)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	16316	1

Signal:

RAM_MEMORY(0)(19)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16254	1

Signal:

RAM_MEMORY(0)(18)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	16236	1

Signal:

RAM_MEMORY(0)(17)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	16236	1

Signal:

RAM_MEMORY(0)(16)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	16261	1

Signal:

RAM_MEMORY(0)(15)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	14213	1

Signal:

RAM_MEMORY(0)(14)

	From	To	Count	Threshold
Bin	0	1	176	1
Bin	1	0	14264	1

Signal:

RAM_MEMORY(0)(13)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	14227	1

Signal:

RAM_MEMORY(0)(12)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	14208	1

Signal:

RAM_MEMORY(0)(11)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	14223	1

Signal:

RAM_MEMORY(0)(10)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	14268	1

Signal:

RAM_MEMORY(0)(9)

	From	To	Count	Threshold
Bin	0	1	879	1
Bin	1	0	15414	1

Signal:

RAM_MEMORY(0)(8)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	14242	1

Signal:

RAM_MEMORY(0)(7)

	From	To	Count	Threshold
Bin	0	1	1345	1
Bin	1	0	13896	1

Signal:

RAM_MEMORY(0)(6)

	From	To	Count	Threshold
Bin	0	1	928	1
Bin	1	0	13789	1

Signal:

RAM_MEMORY(0)(5)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	13545	1

Signal:

RAM_MEMORY(0)(4)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	13329	1

Signal:

RAM_MEMORY(0)(3)

	From	To	Count	Threshold
Bin	0	1	895	1
Bin	1	0	13589	1

Signal:

RAM_MEMORY(0)(2)

	From	To	Count	Threshold
Bin	0	1	880	1
Bin	1	0	13706	1

Signal:

RAM_MEMORY(0)(1)

	From	To	Count	Threshold
Bin	0	1	806	1
Bin	1	0	13622	1

Signal:

RAM_MEMORY(0)(0)

	From	To	Count	Threshold
Bin	0	1	922	1
Bin	1	0	13666	1

Signal:

RAM_MEMORY(1)(31)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	12824	1

Signal:

RAM_MEMORY(1)(30)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	12826	1

Signal:

RAM_MEMORY(1)(29)

	From	To	Count	Threshold
Bin	0	1	189	1
Bin	1	0	12786	1

Signal:

RAM_MEMORY(1)(28)

	From	To	Count	Threshold
Bin	0	1	1057	1
Bin	1	0	13387	1

Signal:

RAM_MEMORY(1)(27)

	From	To	Count	Threshold
Bin	0	1	939	1
Bin	1	0	13321	1

Signal:

RAM_MEMORY(1)(26)

	From	To	Count	Threshold
Bin	0	1	1048	1
Bin	1	0	13447	1

Signal:

RAM_MEMORY(1)(25)

	From	To	Count	Threshold
Bin	0	1	1060	1
Bin	1	0	13393	1

Signal:

RAM_MEMORY(1)(24)

	From	To	Count	Threshold
Bin	0	1	1019	1
Bin	1	0	13431	1

Signal:

RAM_MEMORY(1)(23)

	From	To	Count	Threshold
Bin	0	1	948	1
Bin	1	0	13402	1

Signal:

RAM_MEMORY(1)(22)

	From	To	Count	Threshold
Bin	0	1	922	1
Bin	1	0	13358	1

Signal:

RAM_MEMORY(1)(21)

	From	To	Count	Threshold
Bin	0	1	1150	1
Bin	1	0	13504	1

Signal:

RAM_MEMORY(1)(20)

	From	To	Count	Threshold
Bin	0	1	992	1
Bin	1	0	13369	1

Signal:

RAM_MEMORY(1)(19)

	From	To	Count	Threshold
Bin	0	1	1074	1
Bin	1	0	13445	1

Signal:

RAM_MEMORY(1)(18)

	From	To	Count	Threshold
Bin	0	1	1018	1
Bin	1	0	13382	1

Signal:

RAM_MEMORY(1)(17)

	From	To	Count	Threshold
Bin	0	1	580	1
Bin	1	0	13091	1

Signal:

RAM_MEMORY(1)(16)

	From	To	Count	Threshold
Bin	0	1	664	1
Bin	1	0	13152	1

Signal:

RAM_MEMORY(1)(15)

	From	To	Count	Threshold
Bin	0	1	573	1
Bin	1	0	14217	1

Signal:

RAM_MEMORY(1)(14)

	From	To	Count	Threshold
Bin	0	1	670	1
Bin	1	0	14361	1

Signal:

RAM_MEMORY(1)(13)

	From	To	Count	Threshold
Bin	0	1	610	1
Bin	1	0	14276	1

Signal:

RAM_MEMORY(1)(12)

	From	To	Count	Threshold
Bin	0	1	670	1
Bin	1	0	14219	1

Signal:

RAM_MEMORY(1)(11)

	From	To	Count	Threshold
Bin	0	1	540	1
Bin	1	0	14105	1

Signal:

RAM_MEMORY(1)(10)

	From	To	Count	Threshold
Bin	0	1	692	1
Bin	1	0	14290	1

Signal:

RAM_MEMORY(1)(9)

	From	To	Count	Threshold
Bin	0	1	593	1
Bin	1	0	14186	1

Signal:

RAM_MEMORY(1)(8)

	From	To	Count	Threshold
Bin	0	1	611	1
Bin	1	0	14164	1

Signal:

RAM_MEMORY(1)(7)

	From	To	Count	Threshold
Bin	0	1	635	1
Bin	1	0	14296	1

Signal:

RAM_MEMORY(1)(6)

	From	To	Count	Threshold
Bin	0	1	678	1
Bin	1	0	14370	1

Signal:

RAM_MEMORY(1)(5)

	From	To	Count	Threshold
Bin	0	1	600	1
Bin	1	0	14239	1

Signal:

RAM_MEMORY(1)(4)

	From	To	Count	Threshold
Bin	0	1	631	1
Bin	1	0	14266	1

Signal:

RAM_MEMORY(1)(3)

	From	To	Count	Threshold
Bin	0	1	644	1
Bin	1	0	14313	1

Signal:

RAM_MEMORY(1)(2)

	From	To	Count	Threshold
Bin	0	1	566	1
Bin	1	0	14224	1

Signal:

RAM_MEMORY(1)(1)

	From	To	Count	Threshold
Bin	0	1	574	1
Bin	1	0	14179	1

Signal:

RAM_MEMORY(1)(0)

	From	To	Count	Threshold
Bin	0	1	582	1
Bin	1	0	14259	1

Signal:

RAM_MEMORY(2)(31)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	14876	1

Signal:

RAM_MEMORY(2)(30)

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	14862	1

Signal:

RAM_MEMORY(2)(29)

	From	To	Count	Threshold
Bin	0	1	219	1
Bin	1	0	14831	1

Signal:

RAM_MEMORY(2)(28)

	From	To	Count	Threshold
Bin	0	1	221	1
Bin	1	0	14844	1

Signal:

RAM_MEMORY(2)(27)

	From	To	Count	Threshold
Bin	0	1	219	1
Bin	1	0	14831	1

Signal:

RAM_MEMORY(2)(26)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	14887	1

Signal:

RAM_MEMORY(2)(25)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	14828	1

Signal:

RAM_MEMORY(2)(24)

	From	To	Count	Threshold
Bin	0	1	232	1
Bin	1	0	14875	1

Signal:

RAM_MEMORY(2)(23)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	14880	1

Signal:

RAM_MEMORY(2)(22)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	14853	1

Signal:

RAM_MEMORY(2)(21)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	14859	1

Signal:

RAM_MEMORY(2)(20)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	14965	1

Signal:

RAM_MEMORY(2)(19)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	14827	1

Signal:

RAM_MEMORY(2)(18)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	14878	1

Signal:

RAM_MEMORY(2)(17)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	14853	1

Signal:

RAM_MEMORY(2)(16)

	From	To	Count	Threshold
Bin	0	1	187	1
Bin	1	0	14832	1

Signal:

RAM_MEMORY(2)(15)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	14714	1

Signal:

RAM_MEMORY(2)(14)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	14767	1

Signal:

RAM_MEMORY(2)(13)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	14749	1

Signal:

RAM_MEMORY(2)(12)

	From	To	Count	Threshold
Bin	0	1	281	1
Bin	1	0	14775	1

Signal:

RAM_MEMORY(2)(11)

	From	To	Count	Threshold
Bin	0	1	237	1
Bin	1	0	14754	1

Signal:

RAM_MEMORY(2)(10)

	From	To	Count	Threshold
Bin	0	1	278	1
Bin	1	0	14867	1

Signal:

RAM_MEMORY(2)(9)

	From	To	Count	Threshold
Bin	0	1	211	1
Bin	1	0	14720	1

Signal:

RAM_MEMORY(2)(8)

	From	To	Count	Threshold
Bin	0	1	258	1
Bin	1	0	14771	1

Signal:

RAM_MEMORY(2)(7)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	14762	1

Signal:

RAM_MEMORY(2)(6)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	14779	1

Signal:

RAM_MEMORY(2)(5)

	From	To	Count	Threshold
Bin	0	1	289	1
Bin	1	0	14809	1

Signal:

RAM_MEMORY(2)(4)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	14775	1

Signal:

RAM_MEMORY(2)(3)

	From	To	Count	Threshold
Bin	0	1	299	1
Bin	1	0	14826	1

Signal:

RAM_MEMORY(2)(2)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	14828	1

Signal:

RAM_MEMORY(2)(1)

	From	To	Count	Threshold
Bin	0	1	225	1
Bin	1	0	14815	1

Signal:

RAM_MEMORY(2)(0)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	14771	1

Signal:

RAM_MEMORY(3)(31)

	From	To	Count	Threshold
Bin	0	1	302	1
Bin	1	0	14259	1

Signal:

RAM_MEMORY(3)(30)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	14261	1

Signal:

RAM_MEMORY(3)(29)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	14187	1

Signal:

RAM_MEMORY(3)(28)

	From	To	Count	Threshold
Bin	0	1	272	1
Bin	1	0	14232	1

Signal:

RAM_MEMORY(3)(27)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	14212	1

Signal:

RAM_MEMORY(3)(26)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	14231	1

Signal:

RAM_MEMORY(3)(25)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	14193	1

Signal:

RAM_MEMORY(3)(24)

	From	To	Count	Threshold
Bin	0	1	262	1
Bin	1	0	14227	1

Signal:

RAM_MEMORY(3)(23)

	From	To	Count	Threshold
Bin	0	1	262	1
Bin	1	0	14137	1

Signal:

RAM_MEMORY(3)(22)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	14132	1

Signal:

RAM_MEMORY(3)(21)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	14182	1

Signal:

RAM_MEMORY(3)(20)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	14138	1

Signal:

RAM_MEMORY(3)(19)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	14257	1

Signal:

RAM_MEMORY(3)(18)

	From	To	Count	Threshold
Bin	0	1	252	1
Bin	1	0	14128	1

Signal:

RAM_MEMORY(3)(17)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	14094	1

Signal:

RAM_MEMORY(3)(16)

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	14145	1

Signal:

RAM_MEMORY(3)(15)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	14163	1

Signal:

RAM_MEMORY(3)(14)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	14241	1

Signal:

RAM_MEMORY(3)(13)

	From	To	Count	Threshold
Bin	0	1	237	1
Bin	1	0	14154	1

Signal:

RAM_MEMORY(3)(12)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	14241	1

Signal:

RAM_MEMORY(3)(11)

	From	To	Count	Threshold
Bin	0	1	258	1
Bin	1	0	14170	1

Signal:

RAM_MEMORY(3)(10)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	14197	1

Signal:

RAM_MEMORY(3)(9)

	From	To	Count	Threshold
Bin	0	1	232	1
Bin	1	0	14154	1

Signal:

RAM_MEMORY(3)(8)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	14139	1

Signal:

RAM_MEMORY(3)(7)

	From	To	Count	Threshold
Bin	0	1	243	1
Bin	1	0	14161	1

Signal:

RAM_MEMORY(3)(6)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	14195	1

Signal:

RAM_MEMORY(3)(5)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	14173	1

Signal:

RAM_MEMORY(3)(4)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	14226	1

Signal:

RAM_MEMORY(3)(3)

	From	To	Count	Threshold
Bin	0	1	279	1
Bin	1	0	14231	1

Signal:

RAM_MEMORY(3)(2)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	14168	1

Signal:

RAM_MEMORY(3)(1)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	14142	1

Signal:

RAM_MEMORY(3)(0)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	14175	1

Signal:

RAM_MEMORY(4)(31)

	From	To	Count	Threshold
Bin	0	1	716	1
Bin	1	0	12105	1

Signal:

RAM_MEMORY(4)(30)

	From	To	Count	Threshold
Bin	0	1	692	1
Bin	1	0	12096	1

Signal:

RAM_MEMORY(4)(29)

	From	To	Count	Threshold
Bin	0	1	782	1
Bin	1	0	12054	1

Signal:

RAM_MEMORY(4)(28)

	From	To	Count	Threshold
Bin	0	1	735	1
Bin	1	0	12218	1

Signal:

RAM_MEMORY(4)(27)

	From	To	Count	Threshold
Bin	0	1	761	1
Bin	1	0	12143	1

Signal:

RAM_MEMORY(4)(26)

	From	To	Count	Threshold
Bin	0	1	703	1
Bin	1	0	12279	1

Signal:

RAM_MEMORY(4)(25)

	From	To	Count	Threshold
Bin	0	1	721	1
Bin	1	0	12004	1

Signal:

RAM_MEMORY(4)(24)

	From	To	Count	Threshold
Bin	0	1	719	1
Bin	1	0	11980	1

Signal:

RAM_MEMORY(4)(23)

	From	To	Count	Threshold
Bin	0	1	683	1
Bin	1	0	11925	1

Signal:

RAM_MEMORY(4)(22)

	From	To	Count	Threshold
Bin	0	1	780	1
Bin	1	0	12045	1

Signal:

RAM_MEMORY(4)(21)

	From	To	Count	Threshold
Bin	0	1	829	1
Bin	1	0	12005	1

Signal:

RAM_MEMORY(4)(20)

	From	To	Count	Threshold
Bin	0	1	716	1
Bin	1	0	12025	1

Signal:

RAM_MEMORY(4)(19)

	From	To	Count	Threshold
Bin	0	1	766	1
Bin	1	0	12099	1

Signal:

RAM_MEMORY(4)(18)

	From	To	Count	Threshold
Bin	0	1	775	1
Bin	1	0	12012	1

Signal:

RAM_MEMORY(4)(17)

	From	To	Count	Threshold
Bin	0	1	794	1
Bin	1	0	11889	1

Signal:

RAM_MEMORY(4)(16)

	From	To	Count	Threshold
Bin	0	1	711	1
Bin	1	0	11909	1

Signal:

RAM_MEMORY(4)(15)

	From	To	Count	Threshold
Bin	0	1	840	1
Bin	1	0	11977	1

Signal:

RAM_MEMORY(4)(14)

	From	To	Count	Threshold
Bin	0	1	801	1
Bin	1	0	11995	1

Signal:

RAM_MEMORY(4)(13)

	From	To	Count	Threshold
Bin	0	1	896	1
Bin	1	0	11983	1

Signal:

RAM_MEMORY(4)(12)

	From	To	Count	Threshold
Bin	0	1	784	1
Bin	1	0	11946	1

Signal:

RAM_MEMORY(4)(11)

	From	To	Count	Threshold
Bin	0	1	759	1
Bin	1	0	11952	1

Signal:

RAM_MEMORY(4)(10)

	From	To	Count	Threshold
Bin	0	1	830	1
Bin	1	0	11975	1

Signal:

RAM_MEMORY(4)(9)

	From	To	Count	Threshold
Bin	0	1	911	1
Bin	1	0	12061	1

Signal:

RAM_MEMORY(4)(8)

	From	To	Count	Threshold
Bin	0	1	806	1
Bin	1	0	11889	1

Signal:

RAM_MEMORY(4)(7)

	From	To	Count	Threshold
Bin	0	1	913	1
Bin	1	0	11853	1

Signal:

RAM_MEMORY(4)(6)

	From	To	Count	Threshold
Bin	0	1	878	1
Bin	1	0	11875	1

Signal:

RAM_MEMORY(4)(5)

	From	To	Count	Threshold
Bin	0	1	970	1
Bin	1	0	11912	1

Signal:

RAM_MEMORY(4)(4)

	From	To	Count	Threshold
Bin	0	1	793	1
Bin	1	0	11817	1

Signal:

RAM_MEMORY(4)(3)

	From	To	Count	Threshold
Bin	0	1	914	1
Bin	1	0	11857	1

Signal:

RAM_MEMORY(4)(2)

	From	To	Count	Threshold
Bin	0	1	834	1
Bin	1	0	11857	1

Signal:

RAM_MEMORY(4)(1)

	From	To	Count	Threshold
Bin	0	1	893	1
Bin	1	0	11842	1

Signal:

RAM_MEMORY(4)(0)

	From	To	Count	Threshold
Bin	0	1	792	1
Bin	1	0	11825	1

Signal:

RAM_MEMORY(5)(31)

	From	To	Count	Threshold
Bin	0	1	634	1
Bin	1	0	11830	1

Signal:

RAM_MEMORY(5)(30)

	From	To	Count	Threshold
Bin	0	1	541	1
Bin	1	0	11773	1

Signal:

RAM_MEMORY(5)(29)

	From	To	Count	Threshold
Bin	0	1	604	1
Bin	1	0	11746	1

Signal:

RAM_MEMORY(5)(28)

	From	To	Count	Threshold
Bin	0	1	584	1
Bin	1	0	12050	1

Signal:

RAM_MEMORY(5)(27)

	From	To	Count	Threshold
Bin	0	1	639	1
Bin	1	0	11819	1

Signal:

RAM_MEMORY(5)(26)

	From	To	Count	Threshold
Bin	0	1	630	1
Bin	1	0	12085	1

Signal:

RAM_MEMORY(5)(25)

	From	To	Count	Threshold
Bin	0	1	606	1
Bin	1	0	11987	1

Signal:

RAM_MEMORY(5)(24)

	From	To	Count	Threshold
Bin	0	1	584	1
Bin	1	0	11797	1

Signal:

RAM_MEMORY(5)(23)

	From	To	Count	Threshold
Bin	0	1	702	1
Bin	1	0	11830	1

Signal:

RAM_MEMORY(5)(22)

	From	To	Count	Threshold
Bin	0	1	701	1
Bin	1	0	11894	1

Signal:

RAM_MEMORY(5)(21)

	From	To	Count	Threshold
Bin	0	1	638	1
Bin	1	0	11796	1

Signal:

RAM_MEMORY(5)(20)

	From	To	Count	Threshold
Bin	0	1	533	1
Bin	1	0	11872	1

Signal:

RAM_MEMORY(5)(19)

	From	To	Count	Threshold
Bin	0	1	683	1
Bin	1	0	11953	1

Signal:

RAM_MEMORY(5)(18)

	From	To	Count	Threshold
Bin	0	1	646	1
Bin	1	0	11800	1

Signal:

RAM_MEMORY(5)(17)

	From	To	Count	Threshold
Bin	0	1	658	1
Bin	1	0	12031	1

Signal:

RAM_MEMORY(5)(16)

	From	To	Count	Threshold
Bin	0	1	650	1
Bin	1	0	11885	1

Signal:

RAM_MEMORY(5)(15)

	From	To	Count	Threshold
Bin	0	1	735	1
Bin	1	0	11799	1

Signal:

RAM_MEMORY(5)(14)

	From	To	Count	Threshold
Bin	0	1	779	1
Bin	1	0	11793	1

Signal:

RAM_MEMORY(5)(13)

	From	To	Count	Threshold
Bin	0	1	766	1
Bin	1	0	11910	1

Signal:

RAM_MEMORY(5)(12)

	From	To	Count	Threshold
Bin	0	1	598	1
Bin	1	0	11661	1

Signal:

RAM_MEMORY(5)(11)

	From	To	Count	Threshold
Bin	0	1	670	1
Bin	1	0	11689	1

Signal:

RAM_MEMORY(5)(10)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	11822	1

Signal:

RAM_MEMORY(5)(9)

	From	To	Count	Threshold
Bin	0	1	693	1
Bin	1	0	11865	1

Signal:

RAM_MEMORY(5)(8)

	From	To	Count	Threshold
Bin	0	1	613	1
Bin	1	0	11683	1

Signal:

RAM_MEMORY(5)(7)

	From	To	Count	Threshold
Bin	0	1	707	1
Bin	1	0	11561	1

Signal:

RAM_MEMORY(5)(6)

	From	To	Count	Threshold
Bin	0	1	763	1
Bin	1	0	11612	1

Signal:

RAM_MEMORY(5)(5)

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	11687	1

Signal:

RAM_MEMORY(5)(4)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	11602	1

Signal:

RAM_MEMORY(5)(3)

	From	To	Count	Threshold
Bin	0	1	776	1
Bin	1	0	11730	1

Signal:

RAM_MEMORY(5)(2)

	From	To	Count	Threshold
Bin	0	1	597	1
Bin	1	0	11603	1

Signal:

RAM_MEMORY(5)(1)

	From	To	Count	Threshold
Bin	0	1	765	1
Bin	1	0	11775	1

Signal:

RAM_MEMORY(5)(0)

	From	To	Count	Threshold
Bin	0	1	673	1
Bin	1	0	11624	1

Signal:

RAM_MEMORY(6)(31)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	11599	1

Signal:

RAM_MEMORY(6)(30)

	From	To	Count	Threshold
Bin	0	1	545	1
Bin	1	0	11721	1

Signal:

RAM_MEMORY(6)(29)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	11722	1

Signal:

RAM_MEMORY(6)(28)

	From	To	Count	Threshold
Bin	0	1	580	1
Bin	1	0	11705	1

Signal:

RAM_MEMORY(6)(27)

	From	To	Count	Threshold
Bin	0	1	633	1
Bin	1	0	11573	1

Signal:

RAM_MEMORY(6)(26)

	From	To	Count	Threshold
Bin	0	1	566	1
Bin	1	0	11678	1

Signal:

RAM_MEMORY(6)(25)

	From	To	Count	Threshold
Bin	0	1	553	1
Bin	1	0	11679	1

Signal:

RAM_MEMORY(6)(24)

	From	To	Count	Threshold
Bin	0	1	463	1
Bin	1	0	11604	1

Signal:

RAM_MEMORY(6)(23)

	From	To	Count	Threshold
Bin	0	1	565	1
Bin	1	0	11560	1

Signal:

RAM_MEMORY(6)(22)

	From	To	Count	Threshold
Bin	0	1	417	1
Bin	1	0	11546	1

Signal:

RAM_MEMORY(6)(21)

	From	To	Count	Threshold
Bin	0	1	658	1
Bin	1	0	11718	1

Signal:

RAM_MEMORY(6)(20)

	From	To	Count	Threshold
Bin	0	1	518	1
Bin	1	0	11754	1

Signal:

RAM_MEMORY(6)(19)

	From	To	Count	Threshold
Bin	0	1	553	1
Bin	1	0	11674	1

Signal:

RAM_MEMORY(6)(18)

	From	To	Count	Threshold
Bin	0	1	574	1
Bin	1	0	11714	1

Signal:

RAM_MEMORY(6)(17)

	From	To	Count	Threshold
Bin	0	1	611	1
Bin	1	0	11722	1

Signal:

RAM_MEMORY(6)(16)

	From	To	Count	Threshold
Bin	0	1	430	1
Bin	1	0	11692	1

Signal:

RAM_MEMORY(6)(15)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	11643	1

Signal:

RAM_MEMORY(6)(14)

	From	To	Count	Threshold
Bin	0	1	508	1
Bin	1	0	11674	1

Signal:

RAM_MEMORY(6)(13)

	From	To	Count	Threshold
Bin	0	1	583	1
Bin	1	0	11716	1

Signal:

RAM_MEMORY(6)(12)

	From	To	Count	Threshold
Bin	0	1	609	1
Bin	1	0	11695	1

Signal:

RAM_MEMORY(6)(11)

	From	To	Count	Threshold
Bin	0	1	548	1
Bin	1	0	11660	1

Signal:

RAM_MEMORY(6)(10)

	From	To	Count	Threshold
Bin	0	1	500	1
Bin	1	0	11631	1

Signal:

RAM_MEMORY(6)(9)

	From	To	Count	Threshold
Bin	0	1	626	1
Bin	1	0	11727	1

Signal:

RAM_MEMORY(6)(8)

	From	To	Count	Threshold
Bin	0	1	546	1
Bin	1	0	11766	1

Signal:

RAM_MEMORY(6)(7)

	From	To	Count	Threshold
Bin	0	1	509	1
Bin	1	0	11722	1

Signal:

RAM_MEMORY(6)(6)

	From	To	Count	Threshold
Bin	0	1	545	1
Bin	1	0	11686	1

Signal:

RAM_MEMORY(6)(5)

	From	To	Count	Threshold
Bin	0	1	663	1
Bin	1	0	11704	1

Signal:

RAM_MEMORY(6)(4)

	From	To	Count	Threshold
Bin	0	1	470	1
Bin	1	0	11681	1

Signal:

RAM_MEMORY(6)(3)

	From	To	Count	Threshold
Bin	0	1	463	1
Bin	1	0	11658	1

Signal:

RAM_MEMORY(6)(2)

	From	To	Count	Threshold
Bin	0	1	490	1
Bin	1	0	11741	1

Signal:

RAM_MEMORY(6)(1)

	From	To	Count	Threshold
Bin	0	1	639	1
Bin	1	0	11616	1

Signal:

RAM_MEMORY(6)(0)

	From	To	Count	Threshold
Bin	0	1	537	1
Bin	1	0	11620	1

Signal:

RAM_MEMORY(7)(31)

	From	To	Count	Threshold
Bin	0	1	471	1
Bin	1	0	11300	1

Signal:

RAM_MEMORY(7)(30)

	From	To	Count	Threshold
Bin	0	1	330	1
Bin	1	0	11276	1

Signal:

RAM_MEMORY(7)(29)

	From	To	Count	Threshold
Bin	0	1	528	1
Bin	1	0	11266	1

Signal:

RAM_MEMORY(7)(28)

	From	To	Count	Threshold
Bin	0	1	369	1
Bin	1	0	11106	1

Signal:

RAM_MEMORY(7)(27)

	From	To	Count	Threshold
Bin	0	1	458	1
Bin	1	0	11271	1

Signal:

RAM_MEMORY(7)(26)

	From	To	Count	Threshold
Bin	0	1	458	1
Bin	1	0	11217	1

Signal:

RAM_MEMORY(7)(25)

	From	To	Count	Threshold
Bin	0	1	432	1
Bin	1	0	11352	1

Signal:

RAM_MEMORY(7)(24)

	From	To	Count	Threshold
Bin	0	1	456	1
Bin	1	0	11225	1

Signal:

RAM_MEMORY(7)(23)

	From	To	Count	Threshold
Bin	0	1	472	1
Bin	1	0	11179	1

Signal:

RAM_MEMORY(7)(22)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	11227	1

Signal:

RAM_MEMORY(7)(21)

	From	To	Count	Threshold
Bin	0	1	484	1
Bin	1	0	11068	1

Signal:

RAM_MEMORY(7)(20)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	11136	1

Signal:

RAM_MEMORY(7)(19)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	11366	1

Signal:

RAM_MEMORY(7)(18)

	From	To	Count	Threshold
Bin	0	1	426	1
Bin	1	0	11335	1

Signal:

RAM_MEMORY(7)(17)

	From	To	Count	Threshold
Bin	0	1	551	1
Bin	1	0	11378	1

Signal:

RAM_MEMORY(7)(16)

	From	To	Count	Threshold
Bin	0	1	336	1
Bin	1	0	11161	1

Signal:

RAM_MEMORY(7)(15)

	From	To	Count	Threshold
Bin	0	1	480	1
Bin	1	0	11235	1

Signal:

RAM_MEMORY(7)(14)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	11385	1

Signal:

RAM_MEMORY(7)(13)

	From	To	Count	Threshold
Bin	0	1	478	1
Bin	1	0	11124	1

Signal:

RAM_MEMORY(7)(12)

	From	To	Count	Threshold
Bin	0	1	404	1
Bin	1	0	11181	1

Signal:

RAM_MEMORY(7)(11)

	From	To	Count	Threshold
Bin	0	1	441	1
Bin	1	0	11287	1

Signal:

RAM_MEMORY(7)(10)

	From	To	Count	Threshold
Bin	0	1	361	1
Bin	1	0	11182	1

Signal:

RAM_MEMORY(7)(9)

	From	To	Count	Threshold
Bin	0	1	448	1
Bin	1	0	11303	1

Signal:

RAM_MEMORY(7)(8)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	11287	1

Signal:

RAM_MEMORY(7)(7)

	From	To	Count	Threshold
Bin	0	1	442	1
Bin	1	0	11272	1

Signal:

RAM_MEMORY(7)(6)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	11097	1

Signal:

RAM_MEMORY(7)(5)

	From	To	Count	Threshold
Bin	0	1	476	1
Bin	1	0	11190	1

Signal:

RAM_MEMORY(7)(4)

	From	To	Count	Threshold
Bin	0	1	401	1
Bin	1	0	11277	1

Signal:

RAM_MEMORY(7)(3)

	From	To	Count	Threshold
Bin	0	1	419	1
Bin	1	0	11134	1

Signal:

RAM_MEMORY(7)(2)

	From	To	Count	Threshold
Bin	0	1	366	1
Bin	1	0	11314	1

Signal:

RAM_MEMORY(7)(1)

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	11250	1

Signal:

RAM_MEMORY(7)(0)

	From	To	Count	Threshold
Bin	0	1	472	1
Bin	1	0	11150	1

Signal:

RAM_MEMORY(8)(31)

	From	To	Count	Threshold
Bin	0	1	518	1
Bin	1	0	10701	1

Signal:

RAM_MEMORY(8)(30)

	From	To	Count	Threshold
Bin	0	1	392	1
Bin	1	0	10665	1

Signal:

RAM_MEMORY(8)(29)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	10639	1

Signal:

RAM_MEMORY(8)(28)

	From	To	Count	Threshold
Bin	0	1	361	1
Bin	1	0	10764	1

Signal:

RAM_MEMORY(8)(27)

	From	To	Count	Threshold
Bin	0	1	445	1
Bin	1	0	10689	1

Signal:

RAM_MEMORY(8)(26)

	From	To	Count	Threshold
Bin	0	1	422	1
Bin	1	0	10771	1

Signal:

RAM_MEMORY(8)(25)

	From	To	Count	Threshold
Bin	0	1	484	1
Bin	1	0	10706	1

Signal:

RAM_MEMORY(8)(24)

	From	To	Count	Threshold
Bin	0	1	448	1
Bin	1	0	10774	1

Signal:

RAM_MEMORY(8)(23)

	From	To	Count	Threshold
Bin	0	1	419	1
Bin	1	0	10787	1

Signal:

RAM_MEMORY(8)(22)

	From	To	Count	Threshold
Bin	0	1	407	1
Bin	1	0	10754	1

Signal:

RAM_MEMORY(8)(21)

	From	To	Count	Threshold
Bin	0	1	335	1
Bin	1	0	10717	1

Signal:

RAM_MEMORY(8)(20)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	10780	1

Signal:

RAM_MEMORY(8)(19)

	From	To	Count	Threshold
Bin	0	1	509	1
Bin	1	0	10760	1

Signal:

RAM_MEMORY(8)(18)

	From	To	Count	Threshold
Bin	0	1	413	1
Bin	1	0	10793	1

Signal:

RAM_MEMORY(8)(17)

	From	To	Count	Threshold
Bin	0	1	500	1
Bin	1	0	10781	1

Signal:

RAM_MEMORY(8)(16)

	From	To	Count	Threshold
Bin	0	1	403	1
Bin	1	0	10776	1

Signal:

RAM_MEMORY(8)(15)

	From	To	Count	Threshold
Bin	0	1	479	1
Bin	1	0	10714	1

Signal:

RAM_MEMORY(8)(14)

	From	To	Count	Threshold
Bin	0	1	358	1
Bin	1	0	10679	1

Signal:

RAM_MEMORY(8)(13)

	From	To	Count	Threshold
Bin	0	1	381	1
Bin	1	0	10720	1

Signal:

RAM_MEMORY(8)(12)

	From	To	Count	Threshold
Bin	0	1	484	1
Bin	1	0	10850	1

Signal:

RAM_MEMORY(8)(11)

	From	To	Count	Threshold
Bin	0	1	495	1
Bin	1	0	10794	1

Signal:

RAM_MEMORY(8)(10)

	From	To	Count	Threshold
Bin	0	1	402	1
Bin	1	0	10778	1

Signal:

RAM_MEMORY(8)(9)

	From	To	Count	Threshold
Bin	0	1	452	1
Bin	1	0	10701	1

Signal:

RAM_MEMORY(8)(8)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	10725	1

Signal:

RAM_MEMORY(8)(7)

	From	To	Count	Threshold
Bin	0	1	446	1
Bin	1	0	10742	1

Signal:

RAM_MEMORY(8)(6)

	From	To	Count	Threshold
Bin	0	1	438	1
Bin	1	0	10743	1

Signal:

RAM_MEMORY(8)(5)

	From	To	Count	Threshold
Bin	0	1	405	1
Bin	1	0	10753	1

Signal:

RAM_MEMORY(8)(4)

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	10721	1

Signal:

RAM_MEMORY(8)(3)

	From	To	Count	Threshold
Bin	0	1	462	1
Bin	1	0	10714	1

Signal:

RAM_MEMORY(8)(2)

	From	To	Count	Threshold
Bin	0	1	493	1
Bin	1	0	10755	1

Signal:

RAM_MEMORY(8)(1)

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	10759	1

Signal:

RAM_MEMORY(8)(0)

	From	To	Count	Threshold
Bin	0	1	285	1
Bin	1	0	10652	1

Signal:

RAM_MEMORY(9)(31)

	From	To	Count	Threshold
Bin	0	1	487	1
Bin	1	0	10161	1

Signal:

RAM_MEMORY(9)(30)

	From	To	Count	Threshold
Bin	0	1	438	1
Bin	1	0	10192	1

Signal:

RAM_MEMORY(9)(29)

	From	To	Count	Threshold
Bin	0	1	364	1
Bin	1	0	10176	1

Signal:

RAM_MEMORY(9)(28)

	From	To	Count	Threshold
Bin	0	1	356	1
Bin	1	0	10234	1

Signal:

RAM_MEMORY(9)(27)

	From	To	Count	Threshold
Bin	0	1	466	1
Bin	1	0	10179	1

Signal:

RAM_MEMORY(9)(26)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	10228	1

Signal:

RAM_MEMORY(9)(25)

	From	To	Count	Threshold
Bin	0	1	317	1
Bin	1	0	10117	1

Signal:

RAM_MEMORY(9)(24)

	From	To	Count	Threshold
Bin	0	1	345	1
Bin	1	0	10184	1

Signal:

RAM_MEMORY(9)(23)

	From	To	Count	Threshold
Bin	0	1	385	1
Bin	1	0	10215	1

Signal:

RAM_MEMORY(9)(22)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	10156	1

Signal:

RAM_MEMORY(9)(21)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	10138	1

Signal:

RAM_MEMORY(9)(20)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	10128	1

Signal:

RAM_MEMORY(9)(19)

	From	To	Count	Threshold
Bin	0	1	409	1
Bin	1	0	10154	1

Signal:

RAM_MEMORY(9)(18)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	10155	1

Signal:

RAM_MEMORY(9)(17)

	From	To	Count	Threshold
Bin	0	1	377	1
Bin	1	0	10130	1

Signal:

RAM_MEMORY(9)(16)

	From	To	Count	Threshold
Bin	0	1	327	1
Bin	1	0	10182	1

Signal:

RAM_MEMORY(9)(15)

	From	To	Count	Threshold
Bin	0	1	413	1
Bin	1	0	10186	1

Signal:

RAM_MEMORY(9)(14)

	From	To	Count	Threshold
Bin	0	1	419	1
Bin	1	0	10096	1

Signal:

RAM_MEMORY(9)(13)

	From	To	Count	Threshold
Bin	0	1	436	1
Bin	1	0	10133	1

Signal:

RAM_MEMORY(9)(12)

	From	To	Count	Threshold
Bin	0	1	280	1
Bin	1	0	10193	1

Signal:

RAM_MEMORY(9)(11)

	From	To	Count	Threshold
Bin	0	1	478	1
Bin	1	0	10286	1

Signal:

RAM_MEMORY(9)(10)

	From	To	Count	Threshold
Bin	0	1	344	1
Bin	1	0	10124	1

Signal:

RAM_MEMORY(9)(9)

	From	To	Count	Threshold
Bin	0	1	426	1
Bin	1	0	10209	1

Signal:

RAM_MEMORY(9)(8)

	From	To	Count	Threshold
Bin	0	1	455	1
Bin	1	0	10263	1

Signal:

RAM_MEMORY(9)(7)

	From	To	Count	Threshold
Bin	0	1	493	1
Bin	1	0	10303	1

Signal:

RAM_MEMORY(9)(6)

	From	To	Count	Threshold
Bin	0	1	383	1
Bin	1	0	10201	1

Signal:

RAM_MEMORY(9)(5)

	From	To	Count	Threshold
Bin	0	1	475	1
Bin	1	0	10244	1

Signal:

RAM_MEMORY(9)(4)

	From	To	Count	Threshold
Bin	0	1	394	1
Bin	1	0	10169	1

Signal:

RAM_MEMORY(9)(3)

	From	To	Count	Threshold
Bin	0	1	471	1
Bin	1	0	10151	1

Signal:

RAM_MEMORY(9)(2)

	From	To	Count	Threshold
Bin	0	1	322	1
Bin	1	0	10155	1

Signal:

RAM_MEMORY(9)(1)

	From	To	Count	Threshold
Bin	0	1	406	1
Bin	1	0	10190	1

Signal:

RAM_MEMORY(9)(0)

	From	To	Count	Threshold
Bin	0	1	436	1
Bin	1	0	10264	1

Signal:

RAM_MEMORY(10)(31)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	9701	1

Signal:

RAM_MEMORY(10)(30)

	From	To	Count	Threshold
Bin	0	1	411	1
Bin	1	0	9767	1

Signal:

RAM_MEMORY(10)(29)

	From	To	Count	Threshold
Bin	0	1	346	1
Bin	1	0	9721	1

Signal:

RAM_MEMORY(10)(28)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	9684	1

Signal:

RAM_MEMORY(10)(27)

	From	To	Count	Threshold
Bin	0	1	346	1
Bin	1	0	9767	1

Signal:

RAM_MEMORY(10)(26)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	9779	1

Signal:

RAM_MEMORY(10)(25)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	9701	1

Signal:

RAM_MEMORY(10)(24)

	From	To	Count	Threshold
Bin	0	1	434	1
Bin	1	0	9836	1

Signal:

RAM_MEMORY(10)(23)

	From	To	Count	Threshold
Bin	0	1	423	1
Bin	1	0	9836	1

Signal:

RAM_MEMORY(10)(22)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	9816	1

Signal:

RAM_MEMORY(10)(21)

	From	To	Count	Threshold
Bin	0	1	392	1
Bin	1	0	9799	1

Signal:

RAM_MEMORY(10)(20)

	From	To	Count	Threshold
Bin	0	1	313	1
Bin	1	0	9770	1

Signal:

RAM_MEMORY(10)(19)

	From	To	Count	Threshold
Bin	0	1	389	1
Bin	1	0	9721	1

Signal:

RAM_MEMORY(10)(18)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	9826	1

Signal:

RAM_MEMORY(10)(17)

	From	To	Count	Threshold
Bin	0	1	281	1
Bin	1	0	9733	1

Signal:

RAM_MEMORY(10)(16)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	9674	1

Signal:

RAM_MEMORY(10)(15)

	From	To	Count	Threshold
Bin	0	1	407	1
Bin	1	0	9816	1

Signal:

RAM_MEMORY(10)(14)

	From	To	Count	Threshold
Bin	0	1	313	1
Bin	1	0	9799	1

Signal:

RAM_MEMORY(10)(13)

	From	To	Count	Threshold
Bin	0	1	419	1
Bin	1	0	9809	1

Signal:

RAM_MEMORY(10)(12)

	From	To	Count	Threshold
Bin	0	1	398	1
Bin	1	0	9743	1

Signal:

RAM_MEMORY(10)(11)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	9750	1

Signal:

RAM_MEMORY(10)(10)

	From	To	Count	Threshold
Bin	0	1	358	1
Bin	1	0	9750	1

Signal:

RAM_MEMORY(10)(9)

	From	To	Count	Threshold
Bin	0	1	312	1
Bin	1	0	9740	1

Signal:

RAM_MEMORY(10)(8)

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	9740	1

Signal:

RAM_MEMORY(10)(7)

	From	To	Count	Threshold
Bin	0	1	425	1
Bin	1	0	9770	1

Signal:

RAM_MEMORY(10)(6)

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	9701	1

Signal:

RAM_MEMORY(10)(5)

	From	To	Count	Threshold
Bin	0	1	387	1
Bin	1	0	9740	1

Signal:

RAM_MEMORY(10)(4)

	From	To	Count	Threshold
Bin	0	1	267	1
Bin	1	0	9721	1

Signal:

RAM_MEMORY(10)(3)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	9747	1

Signal:

RAM_MEMORY(10)(2)

	From	To	Count	Threshold
Bin	0	1	355	1
Bin	1	0	9721	1

Signal:

RAM_MEMORY(10)(1)

	From	To	Count	Threshold
Bin	0	1	392	1
Bin	1	0	9740	1

Signal:

RAM_MEMORY(10)(0)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	9733	1

Signal:

RAM_MEMORY(11)(31)

	From	To	Count	Threshold
Bin	0	1	295	1
Bin	1	0	9154	1

Signal:

RAM_MEMORY(11)(30)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	9105	1

Signal:

RAM_MEMORY(11)(29)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	9079	1

Signal:

RAM_MEMORY(11)(28)

	From	To	Count	Threshold
Bin	0	1	368	1
Bin	1	0	9218	1

Signal:

RAM_MEMORY(11)(27)

	From	To	Count	Threshold
Bin	0	1	379	1
Bin	1	0	9143	1

Signal:

RAM_MEMORY(11)(26)

	From	To	Count	Threshold
Bin	0	1	278	1
Bin	1	0	9209	1

Signal:

RAM_MEMORY(11)(25)

	From	To	Count	Threshold
Bin	0	1	330	1
Bin	1	0	9145	1

Signal:

RAM_MEMORY(11)(24)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	9061	1

Signal:

RAM_MEMORY(11)(23)

	From	To	Count	Threshold
Bin	0	1	411	1
Bin	1	0	9128	1

Signal:

RAM_MEMORY(11)(22)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	9151	1

Signal:

RAM_MEMORY(11)(21)

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	9114	1

Signal:

RAM_MEMORY(11)(20)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	9160	1

Signal:

RAM_MEMORY(11)(19)

	From	To	Count	Threshold
Bin	0	1	365	1
Bin	1	0	9174	1

Signal:

RAM_MEMORY(11)(18)

	From	To	Count	Threshold
Bin	0	1	388	1
Bin	1	0	9154	1

Signal:

RAM_MEMORY(11)(17)

	From	To	Count	Threshold
Bin	0	1	402	1
Bin	1	0	9209	1

Signal:

RAM_MEMORY(11)(16)

	From	To	Count	Threshold
Bin	0	1	305	1
Bin	1	0	9079	1

Signal:

RAM_MEMORY(11)(15)

	From	To	Count	Threshold
Bin	0	1	448	1
Bin	1	0	9218	1

Signal:

RAM_MEMORY(11)(14)

	From	To	Count	Threshold
Bin	0	1	368	1
Bin	1	0	9137	1

Signal:

RAM_MEMORY(11)(13)

	From	To	Count	Threshold
Bin	0	1	290	1
Bin	1	0	9154	1

Signal:

RAM_MEMORY(11)(12)

	From	To	Count	Threshold
Bin	0	1	359	1
Bin	1	0	9123	1

Signal:

RAM_MEMORY(11)(11)

	From	To	Count	Threshold
Bin	0	1	363	1
Bin	1	0	9169	1

Signal:

RAM_MEMORY(11)(10)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	9125	1

Signal:

RAM_MEMORY(11)(9)

	From	To	Count	Threshold
Bin	0	1	428	1
Bin	1	0	9209	1

Signal:

RAM_MEMORY(11)(8)

	From	To	Count	Threshold
Bin	0	1	294	1
Bin	1	0	9125	1

Signal:

RAM_MEMORY(11)(7)

	From	To	Count	Threshold
Bin	0	1	290	1
Bin	1	0	9191	1

Signal:

RAM_MEMORY(11)(6)

	From	To	Count	Threshold
Bin	0	1	355	1
Bin	1	0	9174	1

Signal:

RAM_MEMORY(11)(5)

	From	To	Count	Threshold
Bin	0	1	420	1
Bin	1	0	9145	1

Signal:

RAM_MEMORY(11)(4)

	From	To	Count	Threshold
Bin	0	1	414	1
Bin	1	0	9192	1

Signal:

RAM_MEMORY(11)(3)

	From	To	Count	Threshold
Bin	0	1	333	1
Bin	1	0	9163	1

Signal:

RAM_MEMORY(11)(2)

	From	To	Count	Threshold
Bin	0	1	250	1
Bin	1	0	9134	1

Signal:

RAM_MEMORY(11)(1)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	9119	1

Signal:

RAM_MEMORY(11)(0)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	9114	1

Signal:

RAM_MEMORY(12)(31)

	From	To	Count	Threshold
Bin	0	1	402	1
Bin	1	0	8483	1

Signal:

RAM_MEMORY(12)(30)

	From	To	Count	Threshold
Bin	0	1	305	1
Bin	1	0	8578	1

Signal:

RAM_MEMORY(12)(29)

	From	To	Count	Threshold
Bin	0	1	395	1
Bin	1	0	8516	1

Signal:

RAM_MEMORY(12)(28)

	From	To	Count	Threshold
Bin	0	1	326	1
Bin	1	0	8611	1

Signal:

RAM_MEMORY(12)(27)

	From	To	Count	Threshold
Bin	0	1	337	1
Bin	1	0	8483	1

Signal:

RAM_MEMORY(12)(26)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	8549	1

Signal:

RAM_MEMORY(12)(25)

	From	To	Count	Threshold
Bin	0	1	358	1
Bin	1	0	8586	1

Signal:

RAM_MEMORY(12)(24)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	8508	1

Signal:

RAM_MEMORY(12)(23)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	8467	1

Signal:

RAM_MEMORY(12)(22)

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	8578	1

Signal:

RAM_MEMORY(12)(21)

	From	To	Count	Threshold
Bin	0	1	381	1
Bin	1	0	8492	1

Signal:

RAM_MEMORY(12)(20)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	8603	1

Signal:

RAM_MEMORY(12)(19)

	From	To	Count	Threshold
Bin	0	1	279	1
Bin	1	0	8516	1

Signal:

RAM_MEMORY(12)(18)

	From	To	Count	Threshold
Bin	0	1	404	1
Bin	1	0	8557	1

Signal:

RAM_MEMORY(12)(17)

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	8586	1

Signal:

RAM_MEMORY(12)(16)

	From	To	Count	Threshold
Bin	0	1	357	1
Bin	1	0	8483	1

Signal:

RAM_MEMORY(12)(15)

	From	To	Count	Threshold
Bin	0	1	262	1
Bin	1	0	8604	1

Signal:

RAM_MEMORY(12)(14)

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	8637	1

Signal:

RAM_MEMORY(12)(13)

	From	To	Count	Threshold
Bin	0	1	270	1
Bin	1	0	8563	1

Signal:

RAM_MEMORY(12)(12)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	8637	1

Signal:

RAM_MEMORY(12)(11)

	From	To	Count	Threshold
Bin	0	1	420	1
Bin	1	0	8661	1

Signal:

RAM_MEMORY(12)(10)

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	8637	1

Signal:

RAM_MEMORY(12)(9)

	From	To	Count	Threshold
Bin	0	1	339	1
Bin	1	0	8583	1

Signal:

RAM_MEMORY(12)(8)

	From	To	Count	Threshold
Bin	0	1	357	1
Bin	1	0	8591	1

Signal:

RAM_MEMORY(12)(7)

	From	To	Count	Threshold
Bin	0	1	389	1
Bin	1	0	8483	1

Signal:

RAM_MEMORY(12)(6)

	From	To	Count	Threshold
Bin	0	1	372	1
Bin	1	0	8532	1

Signal:

RAM_MEMORY(12)(5)

	From	To	Count	Threshold
Bin	0	1	352	1
Bin	1	0	8483	1

Signal:

RAM_MEMORY(12)(4)

	From	To	Count	Threshold
Bin	0	1	331	1
Bin	1	0	8578	1

Signal:

RAM_MEMORY(12)(3)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	8475	1

Signal:

RAM_MEMORY(12)(2)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	8557	1

Signal:

RAM_MEMORY(12)(1)

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	8524	1

Signal:

RAM_MEMORY(12)(0)

	From	To	Count	Threshold
Bin	0	1	357	1
Bin	1	0	8540	1

Signal:

RAM_MEMORY(13)(31)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	7918	1

Signal:

RAM_MEMORY(13)(30)

	From	To	Count	Threshold
Bin	0	1	317	1
Bin	1	0	7900	1

Signal:

RAM_MEMORY(13)(29)

	From	To	Count	Threshold
Bin	0	1	302	1
Bin	1	0	7862	1

Signal:

RAM_MEMORY(13)(28)

	From	To	Count	Threshold
Bin	0	1	410	1
Bin	1	0	7960	1

Signal:

RAM_MEMORY(13)(27)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	7904	1

Signal:

RAM_MEMORY(13)(26)

	From	To	Count	Threshold
Bin	0	1	380	1
Bin	1	0	7995	1

Signal:

RAM_MEMORY(13)(25)

	From	To	Count	Threshold
Bin	0	1	348	1
Bin	1	0	7953	1

Signal:

RAM_MEMORY(13)(24)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	7911	1

Signal:

RAM_MEMORY(13)(23)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	7893	1

Signal:

RAM_MEMORY(13)(22)

	From	To	Count	Threshold
Bin	0	1	379	1
Bin	1	0	8002	1

Signal:

RAM_MEMORY(13)(21)

	From	To	Count	Threshold
Bin	0	1	362	1
Bin	1	0	7918	1

Signal:

RAM_MEMORY(13)(20)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	7971	1

Signal:

RAM_MEMORY(13)(19)

	From	To	Count	Threshold
Bin	0	1	286	1
Bin	1	0	7862	1

Signal:

RAM_MEMORY(13)(18)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	7922	1

Signal:

RAM_MEMORY(13)(17)

	From	To	Count	Threshold
Bin	0	1	291	1
Bin	1	0	7915	1

Signal:

RAM_MEMORY(13)(16)

	From	To	Count	Threshold
Bin	0	1	292	1
Bin	1	0	7953	1

Signal:

RAM_MEMORY(13)(15)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	7942	1

Signal:

RAM_MEMORY(13)(14)

	From	To	Count	Threshold
Bin	0	1	288	1
Bin	1	0	7886	1

Signal:

RAM_MEMORY(13)(13)

	From	To	Count	Threshold
Bin	0	1	299	1
Bin	1	0	7995	1

Signal:

RAM_MEMORY(13)(12)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	7928	1

Signal:

RAM_MEMORY(13)(11)

	From	To	Count	Threshold
Bin	0	1	323	1
Bin	1	0	7932	1

Signal:

RAM_MEMORY(13)(10)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	7971	1

Signal:

RAM_MEMORY(13)(9)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	7876	1

Signal:

RAM_MEMORY(13)(8)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	7985	1

Signal:

RAM_MEMORY(13)(7)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	7918	1

Signal:

RAM_MEMORY(13)(6)

	From	To	Count	Threshold
Bin	0	1	303	1
Bin	1	0	7935	1

Signal:

RAM_MEMORY(13)(5)

	From	To	Count	Threshold
Bin	0	1	286	1
Bin	1	0	7946	1

Signal:

RAM_MEMORY(13)(4)

	From	To	Count	Threshold
Bin	0	1	363	1
Bin	1	0	7918	1

Signal:

RAM_MEMORY(13)(3)

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	7978	1

Signal:

RAM_MEMORY(13)(2)

	From	To	Count	Threshold
Bin	0	1	299	1
Bin	1	0	7900	1

Signal:

RAM_MEMORY(13)(1)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	7918	1

Signal:

RAM_MEMORY(13)(0)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	7946	1

Signal:

RAM_MEMORY(14)(31)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	7309	1

Signal:

RAM_MEMORY(14)(30)

	From	To	Count	Threshold
Bin	0	1	300	1
Bin	1	0	7292	1

Signal:

RAM_MEMORY(14)(29)

	From	To	Count	Threshold
Bin	0	1	326	1
Bin	1	0	7393	1

Signal:

RAM_MEMORY(14)(28)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	7257	1

Signal:

RAM_MEMORY(14)(27)

	From	To	Count	Threshold
Bin	0	1	415	1
Bin	1	0	7318	1

Signal:

RAM_MEMORY(14)(26)

	From	To	Count	Threshold
Bin	0	1	336	1
Bin	1	0	7315	1

Signal:

RAM_MEMORY(14)(25)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	7269	1

Signal:

RAM_MEMORY(14)(24)

	From	To	Count	Threshold
Bin	0	1	299	1
Bin	1	0	7329	1

Signal:

RAM_MEMORY(14)(23)

	From	To	Count	Threshold
Bin	0	1	326	1
Bin	1	0	7381	1

Signal:

RAM_MEMORY(14)(22)

	From	To	Count	Threshold
Bin	0	1	344	1
Bin	1	0	7263	1

Signal:

RAM_MEMORY(14)(21)

	From	To	Count	Threshold
Bin	0	1	409	1
Bin	1	0	7344	1

Signal:

RAM_MEMORY(14)(20)

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	7309	1

Signal:

RAM_MEMORY(14)(19)

	From	To	Count	Threshold
Bin	0	1	330	1
Bin	1	0	7393	1

Signal:

RAM_MEMORY(14)(18)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	7332	1

Signal:

RAM_MEMORY(14)(17)

	From	To	Count	Threshold
Bin	0	1	346	1
Bin	1	0	7335	1

Signal:

RAM_MEMORY(14)(16)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	7315	1

Signal:

RAM_MEMORY(14)(15)

	From	To	Count	Threshold
Bin	0	1	285	1
Bin	1	0	7321	1

Signal:

RAM_MEMORY(14)(14)

	From	To	Count	Threshold
Bin	0	1	377	1
Bin	1	0	7387	1

Signal:

RAM_MEMORY(14)(13)

	From	To	Count	Threshold
Bin	0	1	308	1
Bin	1	0	7309	1

Signal:

RAM_MEMORY(14)(12)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	7335	1

Signal:

RAM_MEMORY(14)(11)

	From	To	Count	Threshold
Bin	0	1	312	1
Bin	1	0	7321	1

Signal:

RAM_MEMORY(14)(10)

	From	To	Count	Threshold
Bin	0	1	338	1
Bin	1	0	7315	1

Signal:

RAM_MEMORY(14)(9)

	From	To	Count	Threshold
Bin	0	1	333	1
Bin	1	0	7315	1

Signal:

RAM_MEMORY(14)(8)

	From	To	Count	Threshold
Bin	0	1	303	1
Bin	1	0	7332	1

Signal:

RAM_MEMORY(14)(7)

	From	To	Count	Threshold
Bin	0	1	286	1
Bin	1	0	7312	1

Signal:

RAM_MEMORY(14)(6)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	7269	1

Signal:

RAM_MEMORY(14)(5)

	From	To	Count	Threshold
Bin	0	1	380	1
Bin	1	0	7286	1

Signal:

RAM_MEMORY(14)(4)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	7292	1

Signal:

RAM_MEMORY(14)(3)

	From	To	Count	Threshold
Bin	0	1	377	1
Bin	1	0	7292	1

Signal:

RAM_MEMORY(14)(2)

	From	To	Count	Threshold
Bin	0	1	297	1
Bin	1	0	7269	1

Signal:

RAM_MEMORY(14)(1)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	7306	1

Signal:

RAM_MEMORY(14)(0)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	7381	1

Signal:

RAM_MEMORY(15)(31)

	From	To	Count	Threshold
Bin	0	1	382	1
Bin	1	0	6757	1

Signal:

RAM_MEMORY(15)(30)

	From	To	Count	Threshold
Bin	0	1	334	1
Bin	1	0	6730	1

Signal:

RAM_MEMORY(15)(29)

	From	To	Count	Threshold
Bin	0	1	322	1
Bin	1	0	6657	1

Signal:

RAM_MEMORY(15)(28)

	From	To	Count	Threshold
Bin	0	1	336	1
Bin	1	0	6769	1

Signal:

RAM_MEMORY(15)(27)

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	6723	1

Signal:

RAM_MEMORY(15)(26)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	6730	1

Signal:

RAM_MEMORY(15)(25)

	From	To	Count	Threshold
Bin	0	1	326	1
Bin	1	0	6738	1

Signal:

RAM_MEMORY(15)(24)

	From	To	Count	Threshold
Bin	0	1	356	1
Bin	1	0	6762	1

Signal:

RAM_MEMORY(15)(23)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	6774	1

Signal:

RAM_MEMORY(15)(22)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	6735	1

Signal:

RAM_MEMORY(15)(21)

	From	To	Count	Threshold
Bin	0	1	259	1
Bin	1	0	6708	1

Signal:

RAM_MEMORY(15)(20)

	From	To	Count	Threshold
Bin	0	1	345	1
Bin	1	0	6716	1

Signal:

RAM_MEMORY(15)(19)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	6703	1

Signal:

RAM_MEMORY(15)(18)

	From	To	Count	Threshold
Bin	0	1	321	1
Bin	1	0	6733	1

Signal:

RAM_MEMORY(15)(17)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	6774	1

Signal:

RAM_MEMORY(15)(16)

	From	To	Count	Threshold
Bin	0	1	228	1
Bin	1	0	6674	1

Signal:

RAM_MEMORY(15)(15)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	6774	1

Signal:

RAM_MEMORY(15)(14)

	From	To	Count	Threshold
Bin	0	1	255	1
Bin	1	0	6662	1

Signal:

RAM_MEMORY(15)(13)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	6779	1

Signal:

RAM_MEMORY(15)(12)

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	6723	1

Signal:

RAM_MEMORY(15)(11)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	6706	1

Signal:

RAM_MEMORY(15)(10)

	From	To	Count	Threshold
Bin	0	1	343	1
Bin	1	0	6738	1

Signal:

RAM_MEMORY(15)(9)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	6674	1

Signal:

RAM_MEMORY(15)(8)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	6784	1

Signal:

RAM_MEMORY(15)(7)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	6713	1

Signal:

RAM_MEMORY(15)(6)

	From	To	Count	Threshold
Bin	0	1	375	1
Bin	1	0	6779	1

Signal:

RAM_MEMORY(15)(5)

	From	To	Count	Threshold
Bin	0	1	418	1
Bin	1	0	6779	1

Signal:

RAM_MEMORY(15)(4)

	From	To	Count	Threshold
Bin	0	1	361	1
Bin	1	0	6757	1

Signal:

RAM_MEMORY(15)(3)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	6701	1

Signal:

RAM_MEMORY(15)(2)

	From	To	Count	Threshold
Bin	0	1	376	1
Bin	1	0	6740	1

Signal:

RAM_MEMORY(15)(1)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	6747	1

Signal:

RAM_MEMORY(15)(0)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	6723	1

Signal:

RAM_MEMORY(16)(31)

	From	To	Count	Threshold
Bin	0	1	292	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(30)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(29)

	From	To	Count	Threshold
Bin	0	1	350	1
Bin	1	0	6217	1

Signal:

RAM_MEMORY(16)(28)

	From	To	Count	Threshold
Bin	0	1	210	1
Bin	1	0	6163	1

Signal:

RAM_MEMORY(16)(27)

	From	To	Count	Threshold
Bin	0	1	323	1
Bin	1	0	6167	1

Signal:

RAM_MEMORY(16)(26)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	6159	1

Signal:

RAM_MEMORY(16)(25)

	From	To	Count	Threshold
Bin	0	1	319	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(24)

	From	To	Count	Threshold
Bin	0	1	330	1
Bin	1	0	6209	1

Signal:

RAM_MEMORY(16)(23)

	From	To	Count	Threshold
Bin	0	1	341	1
Bin	1	0	6217	1

Signal:

RAM_MEMORY(16)(22)

	From	To	Count	Threshold
Bin	0	1	324	1
Bin	1	0	6163	1

Signal:

RAM_MEMORY(16)(21)

	From	To	Count	Threshold
Bin	0	1	263	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(20)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(19)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	6209	1

Signal:

RAM_MEMORY(16)(18)

	From	To	Count	Threshold
Bin	0	1	324	1
Bin	1	0	6163	1

Signal:

RAM_MEMORY(16)(17)

	From	To	Count	Threshold
Bin	0	1	351	1
Bin	1	0	6167	1

Signal:

RAM_MEMORY(16)(16)

	From	To	Count	Threshold
Bin	0	1	324	1
Bin	1	0	6217	1

Signal:

RAM_MEMORY(16)(15)

	From	To	Count	Threshold
Bin	0	1	232	1
Bin	1	0	6209	1

Signal:

RAM_MEMORY(16)(14)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	6209	1

Signal:

RAM_MEMORY(16)(13)

	From	To	Count	Threshold
Bin	0	1	330	1
Bin	1	0	6163	1

Signal:

RAM_MEMORY(16)(12)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	6217	1

Signal:

RAM_MEMORY(16)(11)

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	6221	1

Signal:

RAM_MEMORY(16)(10)

	From	To	Count	Threshold
Bin	0	1	309	1
Bin	1	0	6171	1

Signal:

RAM_MEMORY(16)(9)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(8)

	From	To	Count	Threshold
Bin	0	1	285	1
Bin	1	0	6213	1

Signal:

RAM_MEMORY(16)(7)

	From	To	Count	Threshold
Bin	0	1	274	1
Bin	1	0	6163	1

Signal:

RAM_MEMORY(16)(6)

	From	To	Count	Threshold
Bin	0	1	258	1
Bin	1	0	6217	1

Signal:

RAM_MEMORY(16)(5)

	From	To	Count	Threshold
Bin	0	1	319	1
Bin	1	0	6159	1

Signal:

RAM_MEMORY(16)(4)

	From	To	Count	Threshold
Bin	0	1	250	1
Bin	1	0	6167	1

Signal:

RAM_MEMORY(16)(3)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	6163	1

Signal:

RAM_MEMORY(16)(2)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	6159	1

Signal:

RAM_MEMORY(16)(1)

	From	To	Count	Threshold
Bin	0	1	361	1
Bin	1	0	6167	1

Signal:

RAM_MEMORY(16)(0)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	6159	1

Signal:

RAM_MEMORY(17)(31)

	From	To	Count	Threshold
Bin	0	1	341	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(30)

	From	To	Count	Threshold
Bin	0	1	285	1
Bin	1	0	5557	1

Signal:

RAM_MEMORY(17)(29)

	From	To	Count	Threshold
Bin	0	1	363	1
Bin	1	0	5606	1

Signal:

RAM_MEMORY(17)(28)

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	5600	1

Signal:

RAM_MEMORY(17)(27)

	From	To	Count	Threshold
Bin	0	1	384	1
Bin	1	0	5609	1

Signal:

RAM_MEMORY(17)(26)

	From	To	Count	Threshold
Bin	0	1	347	1
Bin	1	0	5603	1

Signal:

RAM_MEMORY(17)(25)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(24)

	From	To	Count	Threshold
Bin	0	1	257	1
Bin	1	0	5606	1

Signal:

RAM_MEMORY(17)(23)

	From	To	Count	Threshold
Bin	0	1	201	1
Bin	1	0	5551	1

Signal:

RAM_MEMORY(17)(22)

	From	To	Count	Threshold
Bin	0	1	321	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(21)

	From	To	Count	Threshold
Bin	0	1	284	1
Bin	1	0	5600	1

Signal:

RAM_MEMORY(17)(20)

	From	To	Count	Threshold
Bin	0	1	293	1
Bin	1	0	5603	1

Signal:

RAM_MEMORY(17)(19)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(18)

	From	To	Count	Threshold
Bin	0	1	247	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(17)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	5603	1

Signal:

RAM_MEMORY(17)(16)

	From	To	Count	Threshold
Bin	0	1	294	1
Bin	1	0	5606	1

Signal:

RAM_MEMORY(17)(15)

	From	To	Count	Threshold
Bin	0	1	209	1
Bin	1	0	5551	1

Signal:

RAM_MEMORY(17)(14)

	From	To	Count	Threshold
Bin	0	1	231	1
Bin	1	0	5557	1

Signal:

RAM_MEMORY(17)(13)

	From	To	Count	Threshold
Bin	0	1	293	1
Bin	1	0	5600	1

Signal:

RAM_MEMORY(17)(12)

	From	To	Count	Threshold
Bin	0	1	350	1
Bin	1	0	5557	1

Signal:

RAM_MEMORY(17)(11)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	5603	1

Signal:

RAM_MEMORY(17)(10)

	From	To	Count	Threshold
Bin	0	1	203	1
Bin	1	0	5597	1

Signal:

RAM_MEMORY(17)(9)

	From	To	Count	Threshold
Bin	0	1	293	1
Bin	1	0	5600	1

Signal:

RAM_MEMORY(17)(8)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	5557	1

Signal:

RAM_MEMORY(17)(7)

	From	To	Count	Threshold
Bin	0	1	259	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(6)

	From	To	Count	Threshold
Bin	0	1	289	1
Bin	1	0	5560	1

Signal:

RAM_MEMORY(17)(5)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	5600	1

Signal:

RAM_MEMORY(17)(4)

	From	To	Count	Threshold
Bin	0	1	362	1
Bin	1	0	5560	1

Signal:

RAM_MEMORY(17)(3)

	From	To	Count	Threshold
Bin	0	1	289	1
Bin	1	0	5557	1

Signal:

RAM_MEMORY(17)(2)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(1)

	From	To	Count	Threshold
Bin	0	1	324	1
Bin	1	0	5554	1

Signal:

RAM_MEMORY(17)(0)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	5551	1

Signal:

RAM_MEMORY(18)(31)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(30)

	From	To	Count	Threshold
Bin	0	1	331	1
Bin	1	0	4947	1

Signal:

RAM_MEMORY(18)(29)

	From	To	Count	Threshold
Bin	0	1	301	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(28)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(27)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(26)

	From	To	Count	Threshold
Bin	0	1	271	1
Bin	1	0	4993	1

Signal:

RAM_MEMORY(18)(25)

	From	To	Count	Threshold
Bin	0	1	265	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(24)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(23)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	4943	1

Signal:

RAM_MEMORY(18)(22)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	4943	1

Signal:

RAM_MEMORY(18)(21)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(20)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(19)

	From	To	Count	Threshold
Bin	0	1	230	1
Bin	1	0	4991	1

Signal:

RAM_MEMORY(18)(18)

	From	To	Count	Threshold
Bin	0	1	293	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(17)

	From	To	Count	Threshold
Bin	0	1	318	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(16)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(15)

	From	To	Count	Threshold
Bin	0	1	259	1
Bin	1	0	4991	1

Signal:

RAM_MEMORY(18)(14)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(13)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(12)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(11)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(10)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	4947	1

Signal:

RAM_MEMORY(18)(9)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	4995	1

Signal:

RAM_MEMORY(18)(8)

	From	To	Count	Threshold
Bin	0	1	233	1
Bin	1	0	4943	1

Signal:

RAM_MEMORY(18)(7)

	From	To	Count	Threshold
Bin	0	1	310	1
Bin	1	0	4947	1

Signal:

RAM_MEMORY(18)(6)

	From	To	Count	Threshold
Bin	0	1	317	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(5)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	4993	1

Signal:

RAM_MEMORY(18)(4)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	4945	1

Signal:

RAM_MEMORY(18)(3)

	From	To	Count	Threshold
Bin	0	1	308	1
Bin	1	0	4993	1

Signal:

RAM_MEMORY(18)(2)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	4991	1

Signal:

RAM_MEMORY(18)(1)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	4993	1

Signal:

RAM_MEMORY(18)(0)

	From	To	Count	Threshold
Bin	0	1	285	1
Bin	1	0	4997	1

Signal:

RAM_MEMORY(19)(31)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	4336	1

Signal:

RAM_MEMORY(19)(30)

	From	To	Count	Threshold
Bin	0	1	326	1
Bin	1	0	4383	1

Signal:

RAM_MEMORY(19)(29)

	From	To	Count	Threshold
Bin	0	1	234	1
Bin	1	0	4335	1

Signal:

RAM_MEMORY(19)(28)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(27)

	From	To	Count	Threshold
Bin	0	1	220	1
Bin	1	0	4334	1

Signal:

RAM_MEMORY(19)(26)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(25)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	4335	1

Signal:

RAM_MEMORY(19)(24)

	From	To	Count	Threshold
Bin	0	1	276	1
Bin	1	0	4383	1

Signal:

RAM_MEMORY(19)(23)

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(22)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	4383	1

Signal:

RAM_MEMORY(19)(21)

	From	To	Count	Threshold
Bin	0	1	372	1
Bin	1	0	4385	1

Signal:

RAM_MEMORY(19)(20)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(19)

	From	To	Count	Threshold
Bin	0	1	309	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(18)

	From	To	Count	Threshold
Bin	0	1	336	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(17)

	From	To	Count	Threshold
Bin	0	1	287	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(16)

	From	To	Count	Threshold
Bin	0	1	259	1
Bin	1	0	4335	1

Signal:

RAM_MEMORY(19)(15)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	4335	1

Signal:

RAM_MEMORY(19)(14)

	From	To	Count	Threshold
Bin	0	1	279	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(13)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(12)

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(11)

	From	To	Count	Threshold
Bin	0	1	333	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(10)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	4336	1

Signal:

RAM_MEMORY(19)(9)

	From	To	Count	Threshold
Bin	0	1	346	1
Bin	1	0	4337	1

Signal:

RAM_MEMORY(19)(8)

	From	To	Count	Threshold
Bin	0	1	315	1
Bin	1	0	4336	1

Signal:

RAM_MEMORY(19)(7)

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	4336	1

Signal:

RAM_MEMORY(19)(6)

	From	To	Count	Threshold
Bin	0	1	283	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(5)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	4336	1

Signal:

RAM_MEMORY(19)(4)

	From	To	Count	Threshold
Bin	0	1	305	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(3)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	4383	1

Signal:

RAM_MEMORY(19)(2)

	From	To	Count	Threshold
Bin	0	1	293	1
Bin	1	0	4338	1

Signal:

RAM_MEMORY(19)(1)

	From	To	Count	Threshold
Bin	0	1	309	1
Bin	1	0	4382	1

Signal:

RAM_MEMORY(19)(0)

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	4384	1

Signal:

RAM_MEMORY(20)(31)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	4066	1

Signal:

RAM_MEMORY(20)(30)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3902	1

Signal:

RAM_MEMORY(20)(29)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3986	1

Signal:

RAM_MEMORY(20)(28)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3902	1

Signal:

RAM_MEMORY(20)(27)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3944	1

Signal:

RAM_MEMORY(20)(26)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3923	1

Signal:

RAM_MEMORY(20)(25)

	From	To	Count	Threshold
Bin	0	1	370	1
Bin	1	0	4066	1

Signal:

RAM_MEMORY(20)(24)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	3902	1

Signal:

RAM_MEMORY(20)(23)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	4066	1

Signal:

RAM_MEMORY(20)(22)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3902	1

Signal:

RAM_MEMORY(20)(21)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3986	1

Signal:

RAM_MEMORY(20)(20)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3965	1

Signal:

RAM_MEMORY(20)(19)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3986	1

Signal:

RAM_MEMORY(20)(18)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3944	1

Signal:

RAM_MEMORY(20)(17)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	4066	1

Signal:

RAM_MEMORY(20)(16)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3902	1

Signal:

RAM_MEMORY(20)(15)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	3201	1

Signal:

RAM_MEMORY(20)(14)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	3037	1

Signal:

RAM_MEMORY(20)(13)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3079	1

Signal:

RAM_MEMORY(20)(12)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	3114	1

Signal:

RAM_MEMORY(20)(11)

	From	To	Count	Threshold
Bin	0	1	432	1
Bin	1	0	3206	1

Signal:

RAM_MEMORY(20)(10)

	From	To	Count	Threshold
Bin	0	1	435	1
Bin	1	0	3217	1

Signal:

RAM_MEMORY(20)(9)

	From	To	Count	Threshold
Bin	0	1	582	1
Bin	1	0	3509	1

Signal:

RAM_MEMORY(20)(8)

	From	To	Count	Threshold
Bin	0	1	396	1
Bin	1	0	3310	1

Signal:

RAM_MEMORY(20)(7)

	From	To	Count	Threshold
Bin	0	1	370	1
Bin	1	0	3179	1

Signal:

RAM_MEMORY(20)(6)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	3015	1

Signal:

RAM_MEMORY(20)(5)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3036	1

Signal:

RAM_MEMORY(20)(4)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3078	1

Signal:

RAM_MEMORY(20)(3)

	From	To	Count	Threshold
Bin	0	1	328	1
Bin	1	0	3057	1

Signal:

RAM_MEMORY(20)(2)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	3260	1

Signal:

RAM_MEMORY(20)(1)

	From	To	Count	Threshold
Bin	0	1	558	1
Bin	1	0	3220	1

Signal:

RAM_MEMORY(20)(0)

	From	To	Count	Threshold
Bin	0	1	400	1
Bin	1	0	3175	1

Signal:

INT_READ_DATA(31)

	From	To	Count	Threshold
Bin	0	1	988	1
Bin	1	0	1607	1

Signal:

INT_READ_DATA(30)

	From	To	Count	Threshold
Bin	0	1	1106	1
Bin	1	0	1725	1

Signal:

INT_READ_DATA(29)

	From	To	Count	Threshold
Bin	0	1	1004	1
Bin	1	0	1622	1

Signal:

INT_READ_DATA(28)

	From	To	Count	Threshold
Bin	0	1	3632	1
Bin	1	0	4251	1

Signal:

INT_READ_DATA(27)

	From	To	Count	Threshold
Bin	0	1	3631	1
Bin	1	0	4249	1

Signal:

INT_READ_DATA(26)

	From	To	Count	Threshold
Bin	0	1	3723	1
Bin	1	0	4341	1

Signal:

INT_READ_DATA(25)

	From	To	Count	Threshold
Bin	0	1	3467	1
Bin	1	0	4086	1

Signal:

INT_READ_DATA(24)

	From	To	Count	Threshold
Bin	0	1	3546	1
Bin	1	0	4165	1

Signal:

INT_READ_DATA(23)

	From	To	Count	Threshold
Bin	0	1	4133	1
Bin	1	0	4751	1

Signal:

INT_READ_DATA(22)

	From	To	Count	Threshold
Bin	0	1	3858	1
Bin	1	0	4477	1

Signal:

INT_READ_DATA(21)

	From	To	Count	Threshold
Bin	0	1	4400	1
Bin	1	0	5019	1

Signal:

INT_READ_DATA(20)

	From	To	Count	Threshold
Bin	0	1	3922	1
Bin	1	0	4542	1

Signal:

INT_READ_DATA(19)

	From	To	Count	Threshold
Bin	0	1	4513	1
Bin	1	0	5133	1

Signal:

INT_READ_DATA(18)

	From	To	Count	Threshold
Bin	0	1	4121	1
Bin	1	0	4738	1

Signal:

INT_READ_DATA(17)

	From	To	Count	Threshold
Bin	0	1	2884	1
Bin	1	0	3503	1

Signal:

INT_READ_DATA(16)

	From	To	Count	Threshold
Bin	0	1	2546	1
Bin	1	0	3165	1

Signal:

INT_READ_DATA(15)

	From	To	Count	Threshold
Bin	0	1	2404	1
Bin	1	0	3023	1

Signal:

INT_READ_DATA(14)

	From	To	Count	Threshold
Bin	0	1	2905	1
Bin	1	0	3523	1

Signal:

INT_READ_DATA(13)

	From	To	Count	Threshold
Bin	0	1	2477	1
Bin	1	0	3095	1

Signal:

INT_READ_DATA(12)

	From	To	Count	Threshold
Bin	0	1	2969	1
Bin	1	0	3586	1

Signal:

INT_READ_DATA(11)

	From	To	Count	Threshold
Bin	0	1	2488	1
Bin	1	0	3106	1

Signal:

INT_READ_DATA(10)

	From	To	Count	Threshold
Bin	0	1	2985	1
Bin	1	0	3604	1

Signal:

INT_READ_DATA(9)

	From	To	Count	Threshold
Bin	0	1	3753	1
Bin	1	0	4371	1

Signal:

INT_READ_DATA(8)

	From	To	Count	Threshold
Bin	0	1	2573	1
Bin	1	0	3191	1

Signal:

INT_READ_DATA(7)

	From	To	Count	Threshold
Bin	0	1	4933	1
Bin	1	0	5550	1

Signal:

INT_READ_DATA(6)

	From	To	Count	Threshold
Bin	0	1	3796	1
Bin	1	0	4413	1

Signal:

INT_READ_DATA(5)

	From	To	Count	Threshold
Bin	0	1	3872	1
Bin	1	0	4489	1

Signal:

INT_READ_DATA(4)

	From	To	Count	Threshold
Bin	0	1	2248	1
Bin	1	0	2867	1

Signal:

INT_READ_DATA(3)

	From	To	Count	Threshold
Bin	0	1	3235	1
Bin	1	0	3855	1

Signal:

INT_READ_DATA(2)

	From	To	Count	Threshold
Bin	0	1	3821	1
Bin	1	0	4439	1

Signal:

INT_READ_DATA(1)

	From	To	Count	Threshold
Bin	0	1	3216	1
Bin	1	0	3834	1

Signal:

INT_READ_DATA(0)

	From	To	Count	Threshold
Bin	0	1	4214	1
Bin	1	0	4834	1

Signal:

BYTE_WE(3)

	From	To	Count	Threshold
Bin	0	1	46503	1
Bin	1	0	47163	1

Signal:

BYTE_WE(2)

	From	To	Count	Threshold
Bin	0	1	46503	1
Bin	1	0	47163	1

Signal:

BYTE_WE(1)

	From	To	Count	Threshold
Bin	0	1	46503	1
Bin	1	0	47163	1

Signal:

BYTE_WE(0)

	From	To	Count	Threshold
Bin	0	1	46503	1
Bin	1	0	47163	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: