| Nested Instances | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| RX_SHIFT_RES_REG_INST | 100.0 % (3/3) | 100.0 % (4/4) | 100.0 % (8/8) | 100.0 % (2/2) | N.A. | N.A. | 100.0 % (17/17) |
| MUX2_RES_TST_INST | 100.0 % (3/3) | 100.0 % (2/2) | 100.0 % (8/8) | N.A. | N.A. | N.A. | 100.0 % (13/13) |
| Current Instance | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.RST_REG_INST | N.A. | N.A. | 100.0 % (12/12) | N.A. | N.A. | N.A. | 100.0 % (12/12) |
| Statement | Branch | Toggle | Expression | FSM state | Functional |
|---|
CLK| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
ARST| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
D| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
SCAN_ENABLE| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
| Bin | 1 | 0 | 0 | 1 | Exclude file |
Q| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 14720 | 1 |
| Bin | 1 | 0 | 14709 | 1 |
Q_I| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 14720 | 1 |
| Bin | 1 | 0 | 14709 | 1 |