NVC code coverage report

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i; 
Count: 5445
Threshold: 1

---

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 
Count: 1602
Threshold: 1

---

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 73
Threshold: 1

---

Signal assignment statement on line 280:

280:               '0'; 
Count: 1529
Threshold: 1

---

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 10156520
Threshold: 1

---

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 10141553
Threshold: 1

---

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 14967
Threshold: 1

---

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 
Count: 96902
Threshold: 1

---

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 95939
Threshold: 1

---

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb; 
Count: 963
Threshold: 1

---

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 
Count: 705538
Threshold: 1

---

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 696468
Threshold: 1

---

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata; 
Count: 9070
Threshold: 1

---

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 85904
Threshold: 1

---

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 84645
Threshold: 1

---

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 1259
Threshold: 1

---

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 
Count: 5756
Threshold: 1

---

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 544
Threshold: 1

---

Signal assignment statement on line 302:

302:                                     (others => '0'); 
Count: 5212
Threshold: 1

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

	Evaluated to	Count	Threshold
Bin	True	73	1
Bin	False	1529	1

---

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	10141553	1
Bin	False	14967	1

---

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	95939	1
Bin	False	963	1

---

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	696468	1
Bin	False	9070	1

---

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	84645	1
Bin	False	1259	1

---

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	544	1
Bin	False	5212	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_BE

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	128	1
Bin	(31)	1	0	293	1
Bin	(30)	0	1	122	1
Bin	(30)	1	0	287	1
Bin	(29)	0	1	124	1
Bin	(29)	1	0	289	1
Bin	(28)	0	1	119	1
Bin	(28)	1	0	284	1
Bin	(27)	0	1	123	1
Bin	(27)	1	0	288	1
Bin	(26)	0	1	125	1
Bin	(26)	1	0	290	1
Bin	(25)	0	1	136	1
Bin	(25)	1	0	301	1
Bin	(24)	0	1	125	1
Bin	(24)	1	0	290	1
Bin	(23)	0	1	132	1
Bin	(23)	1	0	297	1
Bin	(22)	0	1	118	1
Bin	(22)	1	0	283	1
Bin	(21)	0	1	117	1
Bin	(21)	1	0	282	1
Bin	(20)	0	1	126	1
Bin	(20)	1	0	291	1
Bin	(19)	0	1	131	1
Bin	(19)	1	0	296	1
Bin	(18)	0	1	126	1
Bin	(18)	1	0	291	1
Bin	(17)	0	1	123	1
Bin	(17)	1	0	288	1
Bin	(16)	0	1	131	1
Bin	(16)	1	0	296	1
Bin	(15)	0	1	113	1
Bin	(15)	1	0	278	1
Bin	(14)	0	1	130	1
Bin	(14)	1	0	295	1
Bin	(13)	0	1	124	1
Bin	(13)	1	0	289	1
Bin	(12)	0	1	120	1
Bin	(12)	1	0	285	1
Bin	(11)	0	1	113	1
Bin	(11)	1	0	278	1
Bin	(10)	0	1	120	1
Bin	(10)	1	0	285	1
Bin	(9)	0	1	134	1
Bin	(9)	1	0	299	1
Bin	(8)	0	1	124	1
Bin	(8)	1	0	289	1
Bin	(7)	0	1	134	1
Bin	(7)	1	0	299	1
Bin	(6)	0	1	120	1
Bin	(6)	1	0	285	1
Bin	(5)	0	1	120	1
Bin	(5)	1	0	285	1
Bin	(4)	0	1	122	1
Bin	(4)	1	0	287	1
Bin	(3)	0	1	131	1
Bin	(3)	1	0	296	1
Bin	(2)	0	1	131	1
Bin	(2)	1	0	296	1
Bin	(1)	0	1	128	1
Bin	(1)	1	0	293	1
Bin	(0)	0	1	128	1
Bin	(0)	1	0	293	1

---

Port:

 TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	316	1
Bin	(31)	1	0	471	1
Bin	(30)	0	1	300	1
Bin	(30)	1	0	455	1
Bin	(29)	0	1	385	1
Bin	(29)	1	0	540	1
Bin	(28)	0	1	713	1
Bin	(28)	1	0	864	1
Bin	(27)	0	1	652	1
Bin	(27)	1	0	802	1
Bin	(26)	0	1	644	1
Bin	(26)	1	0	796	1
Bin	(25)	0	1	690	1
Bin	(25)	1	0	841	1
Bin	(24)	0	1	891	1
Bin	(24)	1	0	1043	1
Bin	(23)	0	1	946	1
Bin	(23)	1	0	1097	1
Bin	(22)	0	1	935	1
Bin	(22)	1	0	1086	1
Bin	(21)	0	1	841	1
Bin	(21)	1	0	991	1
Bin	(20)	0	1	821	1
Bin	(20)	1	0	975	1
Bin	(19)	0	1	922	1
Bin	(19)	1	0	1073	1
Bin	(18)	0	1	747	1
Bin	(18)	1	0	900	1
Bin	(17)	0	1	489	1
Bin	(17)	1	0	641	1
Bin	(16)	0	1	547	1
Bin	(16)	1	0	700	1
Bin	(15)	0	1	527	1
Bin	(15)	1	0	680	1
Bin	(14)	0	1	553	1
Bin	(14)	1	0	706	1
Bin	(13)	0	1	644	1
Bin	(13)	1	0	795	1
Bin	(12)	0	1	583	1
Bin	(12)	1	0	738	1
Bin	(11)	0	1	606	1
Bin	(11)	1	0	760	1
Bin	(10)	0	1	580	1
Bin	(10)	1	0	733	1
Bin	(9)	0	1	682	1
Bin	(9)	1	0	830	1
Bin	(8)	0	1	553	1
Bin	(8)	1	0	706	1
Bin	(7)	0	1	1087	1
Bin	(7)	1	0	1228	1
Bin	(6)	0	1	873	1
Bin	(6)	1	0	1019	1
Bin	(5)	0	1	949	1
Bin	(5)	1	0	1099	1
Bin	(4)	0	1	608	1
Bin	(4)	1	0	761	1
Bin	(3)	0	1	681	1
Bin	(3)	1	0	830	1
Bin	(2)	0	1	919	1
Bin	(2)	1	0	1067	1
Bin	(1)	0	1	816	1
Bin	(1)	1	0	966	1
Bin	(0)	0	1	956	1
Bin	(0)	1	0	1104	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	483	1
Bin	1	0	648	1

---

Signal:

 TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101691	1
Bin	(4)	1	0	4940946	1
Bin	(3)	0	1	136075	1
Bin	(3)	1	0	4906552	1
Bin	(2)	0	1	116597	1
Bin	(2)	1	0	4926166	1
Bin	(1)	0	1	4798135	1
Bin	(1)	1	0	244912	1
Bin	(0)	0	1	3686863	1
Bin	(0)	1	0	1356798	1

---

Signal:

 TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11853	1
Bin	1	0	12045	1

---

Signal:

 TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	23091	1
Bin	(31)	1	0	322692	1
Bin	(30)	0	1	23811	1
Bin	(30)	1	0	321974	1
Bin	(29)	0	1	23512	1
Bin	(29)	1	0	322289	1
Bin	(28)	0	1	30230	1
Bin	(28)	1	0	315563	1
Bin	(27)	0	1	28526	1
Bin	(27)	1	0	317271	1
Bin	(26)	0	1	30059	1
Bin	(26)	1	0	315738	1
Bin	(25)	0	1	29553	1
Bin	(25)	1	0	316240	1
Bin	(24)	0	1	27494	1
Bin	(24)	1	0	318295	1
Bin	(23)	0	1	26726	1
Bin	(23)	1	0	319075	1
Bin	(22)	0	1	27176	1
Bin	(22)	1	0	318605	1
Bin	(21)	0	1	24795	1
Bin	(21)	1	0	321000	1
Bin	(20)	0	1	26977	1
Bin	(20)	1	0	318828	1
Bin	(19)	0	1	40084	1
Bin	(19)	1	0	305717	1
Bin	(18)	0	1	43870	1
Bin	(18)	1	0	301930	1
Bin	(17)	0	1	43340	1
Bin	(17)	1	0	302463	1
Bin	(16)	0	1	87223	1
Bin	(16)	1	0	258585	1
Bin	(15)	0	1	24215	1
Bin	(15)	1	0	321568	1
Bin	(14)	0	1	28108	1
Bin	(14)	1	0	317693	1
Bin	(13)	0	1	25080	1
Bin	(13)	1	0	320727	1
Bin	(12)	0	1	26092	1
Bin	(12)	1	0	319699	1
Bin	(11)	0	1	45969	1
Bin	(11)	1	0	299828	1
Bin	(10)	0	1	48230	1
Bin	(10)	1	0	297565	1
Bin	(9)	0	1	55865	1
Bin	(9)	1	0	289944	1
Bin	(8)	0	1	55351	1
Bin	(8)	1	0	290442	1
Bin	(7)	0	1	50516	1
Bin	(7)	1	0	295289	1
Bin	(6)	0	1	48405	1
Bin	(6)	1	0	297386	1
Bin	(5)	0	1	50344	1
Bin	(5)	1	0	295451	1
Bin	(4)	0	1	54676	1
Bin	(4)	1	0	291121	1
Bin	(3)	0	1	61031	1
Bin	(3)	1	0	284770	1
Bin	(2)	0	1	63083	1
Bin	(2)	1	0	282722	1
Bin	(1)	0	1	99128	1
Bin	(1)	1	0	246663	1
Bin	(0)	0	1	86875	1
Bin	(0)	1	0	258942	1

---

Signal:

 TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3340	1
Bin	(4)	1	0	3505	1
Bin	(3)	0	1	179	1
Bin	(3)	1	0	344	1
Bin	(2)	0	1	5252	1
Bin	(2)	1	0	5417	1
Bin	(1)	0	1	4031	1
Bin	(1)	1	0	4031	1
Bin	(0)	0	1	11348	1
Bin	(0)	1	0	11513	1

---

Signal:

 TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	316	1
Bin	(31)	1	0	471	1
Bin	(30)	0	1	300	1
Bin	(30)	1	0	455	1
Bin	(29)	0	1	385	1
Bin	(29)	1	0	540	1
Bin	(28)	0	1	713	1
Bin	(28)	1	0	864	1
Bin	(27)	0	1	652	1
Bin	(27)	1	0	802	1
Bin	(26)	0	1	644	1
Bin	(26)	1	0	796	1
Bin	(25)	0	1	690	1
Bin	(25)	1	0	841	1
Bin	(24)	0	1	891	1
Bin	(24)	1	0	1043	1
Bin	(23)	0	1	946	1
Bin	(23)	1	0	1097	1
Bin	(22)	0	1	935	1
Bin	(22)	1	0	1086	1
Bin	(21)	0	1	841	1
Bin	(21)	1	0	991	1
Bin	(20)	0	1	821	1
Bin	(20)	1	0	975	1
Bin	(19)	0	1	922	1
Bin	(19)	1	0	1073	1
Bin	(18)	0	1	747	1
Bin	(18)	1	0	900	1
Bin	(17)	0	1	489	1
Bin	(17)	1	0	641	1
Bin	(16)	0	1	547	1
Bin	(16)	1	0	700	1
Bin	(15)	0	1	527	1
Bin	(15)	1	0	680	1
Bin	(14)	0	1	553	1
Bin	(14)	1	0	706	1
Bin	(13)	0	1	644	1
Bin	(13)	1	0	795	1
Bin	(12)	0	1	583	1
Bin	(12)	1	0	738	1
Bin	(11)	0	1	606	1
Bin	(11)	1	0	760	1
Bin	(10)	0	1	580	1
Bin	(10)	1	0	733	1
Bin	(9)	0	1	682	1
Bin	(9)	1	0	830	1
Bin	(8)	0	1	553	1
Bin	(8)	1	0	706	1
Bin	(7)	0	1	1087	1
Bin	(7)	1	0	1228	1
Bin	(6)	0	1	873	1
Bin	(6)	1	0	1019	1
Bin	(5)	0	1	949	1
Bin	(5)	1	0	1099	1
Bin	(4)	0	1	608	1
Bin	(4)	1	0	761	1
Bin	(3)	0	1	681	1
Bin	(3)	1	0	830	1
Bin	(2)	0	1	919	1
Bin	(2)	1	0	1067	1
Bin	(1)	0	1	816	1
Bin	(1)	1	0	966	1
Bin	(0)	0	1	956	1
Bin	(0)	1	0	1104	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	238	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	38	1
Bin	(20)	1	0	697	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	734	1
Bin	(18)	0	1	2	1
Bin	(18)	1	0	733	1
Bin	(17)	0	1	25	1
Bin	(17)	1	0	710	1
Bin	(16)	0	1	27	1
Bin	(16)	1	0	708	1
Bin	(15)	0	1	29	1
Bin	(15)	1	0	706	1
Bin	(14)	0	1	31	1
Bin	(14)	1	0	704	1
Bin	(13)	0	1	7	1
Bin	(13)	1	0	728	1
Bin	(12)	0	1	8	1
Bin	(12)	1	0	727	1
Bin	(11)	0	1	35	1
Bin	(11)	1	0	700	1
Bin	(10)	0	1	37	1
Bin	(10)	1	0	698	1
Bin	(9)	0	1	54	1
Bin	(9)	1	0	681	1
Bin	(8)	0	1	32	1
Bin	(8)	1	0	703	1
Bin	(7)	0	1	69	1
Bin	(7)	1	0	666	1
Bin	(6)	0	1	83	1
Bin	(6)	1	0	652	1
Bin	(5)	0	1	117	1
Bin	(5)	1	0	618	1
Bin	(4)	0	1	199	1
Bin	(4)	1	0	536	1
Bin	(3)	0	1	334	1
Bin	(3)	1	0	401	1
Bin	(2)	0	1	412	1
Bin	(2)	1	0	323	1
Bin	(1)	0	1	295	1
Bin	(1)	1	0	440	1
Bin	(0)	0	1	277	1
Bin	(0)	1	0	458	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1394	1
Bin	1	0	1250	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	1274	1
Bin	1	0	1439	1

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1	Copy to Clipboard

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold
Bin	True	False	598	1
Bin	True	True	73	1

---

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

---

"=" expression on line 283:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	14967	1
Bin	True	10141553	1

---

"=" expression on line 287:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	963	1
Bin	True	95939	1

---

"=" expression on line 291:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	9070	1
Bin	True	696468	1

---

"=" expression on line 296:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1259	1
Bin	True	84645	1

---

"=" expression on line 300:

 tst_ena = '1' 

	Evaluated to	Count	Threshold
Bin	False	5212	1
Bin	True	544	1