NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ADDRESS_DECODER_TEST_REGISTERS_COMP	100.0 % (16/16)	100.0 % (10/10)	100.0 % (42/42)	100.0 % (2/2)	N.A.	N.A.	100.0 % (70/70)
TST_CONTROL_TMAENA_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (18/18)	100.0 % (10/10)	N.A.	N.A.	100.0 % (40/40)
TST_CONTROL_TWRSTB_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (33/33)
TST_DEST_TST_ADDR_SLICE_1_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
TST_DEST_TST_ADDR_SLICE_2_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
TST_DEST_TST_MTGT_REG_COMP	100.0 % (18/18)	100.0 % (24/24)	100.0 % (36/36)	100.0 % (22/22)	N.A.	N.A.	100.0 % (100/100)
TST_WDATA_TST_WDATA_SLICE_1_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
TST_WDATA_TST_WDATA_SLICE_2_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
TST_WDATA_TST_WDATA_SLICE_3_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
TST_WDATA_TST_WDATA_SLICE_4_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP	100.0 % (15/15)	100.0 % (13/13)	100.0 % (590/590)	100.0 % (16/16)	N.A.	100.0 % (7/7)	100.0 % (641/641)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 55680578
Threshold: 1

Signal assignment statement on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 219383
Threshold: 1

Signal assignment statement on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 55461195
Threshold: 1

Sequential statement on lines 311 to 320:

311:    with address(7 downto 2) select r_data_comb <= 
312:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
...
319:        test_registers_in.tst_rdata_tst_rdata when "000011", 
320:        (others => '0') when others;

Count: 55319228
Threshold: 1

Signal assignment statement on lines 312 to 314:

312:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
313:        test_registers_out_i.tst_control_twrstb & 
314:        test_registers_out_i.tst_control_tmaena when "000000",

Count: 138437
Threshold: 1

Signal assignment statement on lines 315 to 317:

315:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
316:        test_registers_out_i.tst_dest_tst_mtgt & 
317:        test_registers_out_i.tst_dest_tst_addr when "000001",

Count: 398062
Threshold: 1

Signal assignment statement on line 318:

318: test_registers_out_i.tst_wdata_tst_wdata when "000010",
Count: 9461839
Threshold: 1

Signal assignment statement on line 319:

319: test_registers_in.tst_rdata_tst_rdata when "000011",
Count: 149571
Threshold: 1

Signal assignment statement on line 320:

320: (others => '0') when others;
Count: 45171319
Threshold: 1

If statement on lines 327 to 333:

327:        if (res_n = '0') then 
328:            r_data <= (others => '0'); 
...
332:            end if; 
333:        end if;

Count: 28943557
Threshold: 1

Signal assignment statement on line 328:

328: r_data <= (others => '0');
Count: 15862
Threshold: 1

If statement on lines 330 to 332:

330:            if (cs = '1' and read = '1') then 
331:                r_data <= r_data_comb and read_data_mask_n; 
332:            end if;

Count: 14457430
Threshold: 1

Signal assignment statement on line 331:

331: r_data <= r_data_comb and read_data_mask_n;
Count: 93793
Threshold: 1

Signal assignment statement on lines 340 to 343:

340:      be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &  
341:      be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &  
342:      be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &  
343:      be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;

Count: 55052625
Threshold: 1

Signal assignment statement on line 345:

345: Test_registers_out <= Test_registers_out_i;
Count: 202562
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 116:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');

	Evaluated to	Count	Threshold
Bin	True	219383	1
Bin	False	55461195	1

"case" / "with" / "select" choice on line 314:

314: test_registers_out_i.tst_control_tmaena when "000000",

	Choice of	Count	Threshold
Bin	`"000000"`	138437	1

"case" / "with" / "select" choice on line 317:

317: test_registers_out_i.tst_dest_tst_addr when "000001",

	Choice of	Count	Threshold
Bin	`"000001"`	398062	1

"case" / "with" / "select" choice on line 318:

318: test_registers_out_i.tst_wdata_tst_wdata when "000010",

	Choice of	Count	Threshold
Bin	`"000010"`	9461839	1

"case" / "with" / "select" choice on line 319:

319: test_registers_in.tst_rdata_tst_rdata when "000011",

	Choice of	Count	Threshold
Bin	`"000011"`	149571	1

"case" / "with" / "select" choice on line 320:

320: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	45171319	1

"if" / "when" / "else" condition on line 327:

327: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	15862	1
Bin	False	28927695	1

"if" / "when" / "else" condition on line 329:

329: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	14457430	1
Bin	False	14470265	1

"if" / "when" / "else" condition on line 330:

330: if (cs = '1' and read = '1') then

	Evaluated to	Count	Threshold
Bin	True	93793	1
Bin	False	14363637	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

W_DATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

LOCK_1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOCK_2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

R_DATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1346	1
Bin	(31)	1	0	2947	1
Bin	(30)	0	1	1292	1
Bin	(30)	1	0	2893	1
Bin	(29)	0	1	1332	1
Bin	(29)	1	0	2933	1
Bin	(28)	0	1	1452	1
Bin	(28)	1	0	3053	1
Bin	(27)	0	1	1463	1
Bin	(27)	1	0	3064	1
Bin	(26)	0	1	1445	1
Bin	(26)	1	0	3046	1
Bin	(25)	0	1	1476	1
Bin	(25)	1	0	3077	1
Bin	(24)	0	1	1518	1
Bin	(24)	1	0	3119	1
Bin	(23)	0	1	1407	1
Bin	(23)	1	0	3008	1
Bin	(22)	0	1	1359	1
Bin	(22)	1	0	2960	1
Bin	(21)	0	1	1389	1
Bin	(21)	1	0	2990	1
Bin	(20)	0	1	1466	1
Bin	(20)	1	0	3067	1
Bin	(19)	0	1	1491	1
Bin	(19)	1	0	3092	1
Bin	(18)	0	1	1478	1
Bin	(18)	1	0	3079	1
Bin	(17)	0	1	1444	1
Bin	(17)	1	0	3045	1
Bin	(16)	0	1	1491	1
Bin	(16)	1	0	3092	1
Bin	(15)	0	1	1417	1
Bin	(15)	1	0	3018	1
Bin	(14)	0	1	1345	1
Bin	(14)	1	0	2946	1
Bin	(13)	0	1	1426	1
Bin	(13)	1	0	3027	1
Bin	(12)	0	1	1501	1
Bin	(12)	1	0	3102	1
Bin	(11)	0	1	1503	1
Bin	(11)	1	0	3104	1
Bin	(10)	0	1	1454	1
Bin	(10)	1	0	3055	1
Bin	(9)	0	1	1514	1
Bin	(9)	1	0	3115	1
Bin	(8)	0	1	1538	1
Bin	(8)	1	0	3139	1
Bin	(7)	0	1	1443	1
Bin	(7)	1	0	3044	1
Bin	(6)	0	1	1389	1
Bin	(6)	1	0	2990	1
Bin	(5)	0	1	1417	1
Bin	(5)	1	0	3018	1
Bin	(4)	0	1	1479	1
Bin	(4)	1	0	3080	1
Bin	(3)	0	1	1492	1
Bin	(3)	1	0	3093	1
Bin	(2)	0	1	1494	1
Bin	(2)	1	0	3095	1
Bin	(1)	0	1	1531	1
Bin	(1)	1	0	3132	1
Bin	(0)	0	1	1539	1
Bin	(0)	1	0	3140	1

Port:

TEST_REGISTERS_OUT

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32343	1
Bin	TST_CONTROL_TWRSTB	1	0	35235	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	1606	1
Bin	TST_DEST_TST_ADDR(11)	0	1	15	1
Bin	TST_DEST_TST_ADDR(11)	1	0	1616	1
Bin	TST_DEST_TST_ADDR(10)	0	1	25	1
Bin	TST_DEST_TST_ADDR(10)	1	0	1626	1
Bin	TST_DEST_TST_ADDR(9)	0	1	45	1
Bin	TST_DEST_TST_ADDR(9)	1	0	1646	1
Bin	TST_DEST_TST_ADDR(8)	0	1	85	1
Bin	TST_DEST_TST_ADDR(8)	1	0	1686	1
Bin	TST_DEST_TST_ADDR(7)	0	1	165	1
Bin	TST_DEST_TST_ADDR(7)	1	0	1766	1
Bin	TST_DEST_TST_ADDR(6)	0	1	355	1
Bin	TST_DEST_TST_ADDR(6)	1	0	1956	1
Bin	TST_DEST_TST_ADDR(5)	0	1	705	1
Bin	TST_DEST_TST_ADDR(5)	1	0	2306	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3617	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5218	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5036	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6637	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10348	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11949	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22453	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24054	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44900	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46501	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	373	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1974	1
Bin	TST_DEST_TST_MTGT(1)	0	1	514	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2115	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1524	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3125	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1474	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3075	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1522	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3123	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1636	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3237	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3239	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1628	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3229	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1652	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3253	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1686	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3287	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1580	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3181	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3130	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1580	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3181	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1659	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3260	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1673	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3274	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1660	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3261	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1624	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3225	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1658	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3259	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1598	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3199	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1523	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3124	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1588	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3189	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1665	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1665	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1644	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3245	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1680	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3281	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1711	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3312	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1605	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3206	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1553	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3154	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1586	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3187	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1660	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3261	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1643	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3244	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1661	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3262	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1697	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3298	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1695	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3296	1

Port:

TEST_REGISTERS_IN

	Element	From	To	Count	Threshold
Bin	TST_RDATA_TST_RDATA(31)	0	1	24008	1
Bin	TST_RDATA_TST_RDATA(31)	1	0	21102	1
Bin	TST_RDATA_TST_RDATA(30)	0	1	15026	1
Bin	TST_RDATA_TST_RDATA(30)	1	0	21139	1
Bin	TST_RDATA_TST_RDATA(29)	0	1	19384	1
Bin	TST_RDATA_TST_RDATA(29)	1	0	16478	1
Bin	TST_RDATA_TST_RDATA(28)	0	1	19767	1
Bin	TST_RDATA_TST_RDATA(28)	1	0	25880	1
Bin	TST_RDATA_TST_RDATA(27)	0	1	19869	1
Bin	TST_RDATA_TST_RDATA(27)	1	0	16963	1
Bin	TST_RDATA_TST_RDATA(26)	0	1	19815	1
Bin	TST_RDATA_TST_RDATA(26)	1	0	25928	1
Bin	TST_RDATA_TST_RDATA(25)	0	1	24459	1
Bin	TST_RDATA_TST_RDATA(25)	1	0	21553	1
Bin	TST_RDATA_TST_RDATA(24)	0	1	15515	1
Bin	TST_RDATA_TST_RDATA(24)	1	0	21628	1
Bin	TST_RDATA_TST_RDATA(23)	0	1	24270	1
Bin	TST_RDATA_TST_RDATA(23)	1	0	21364	1
Bin	TST_RDATA_TST_RDATA(22)	0	1	15248	1
Bin	TST_RDATA_TST_RDATA(22)	1	0	21361	1
Bin	TST_RDATA_TST_RDATA(21)	0	1	19742	1
Bin	TST_RDATA_TST_RDATA(21)	1	0	16836	1
Bin	TST_RDATA_TST_RDATA(20)	0	1	19820	1
Bin	TST_RDATA_TST_RDATA(20)	1	0	25933	1
Bin	TST_RDATA_TST_RDATA(19)	0	1	19961	1
Bin	TST_RDATA_TST_RDATA(19)	1	0	17055	1
Bin	TST_RDATA_TST_RDATA(18)	0	1	19943	1
Bin	TST_RDATA_TST_RDATA(18)	1	0	26056	1
Bin	TST_RDATA_TST_RDATA(17)	0	1	24384	1
Bin	TST_RDATA_TST_RDATA(17)	1	0	21478	1
Bin	TST_RDATA_TST_RDATA(16)	0	1	15261	1
Bin	TST_RDATA_TST_RDATA(16)	1	0	21374	1
Bin	TST_RDATA_TST_RDATA(15)	0	1	24180	1
Bin	TST_RDATA_TST_RDATA(15)	1	0	21274	1
Bin	TST_RDATA_TST_RDATA(14)	0	1	15199	1
Bin	TST_RDATA_TST_RDATA(14)	1	0	21312	1
Bin	TST_RDATA_TST_RDATA(13)	0	1	19671	1
Bin	TST_RDATA_TST_RDATA(13)	1	0	16765	1
Bin	TST_RDATA_TST_RDATA(12)	0	1	19754	1
Bin	TST_RDATA_TST_RDATA(12)	1	0	25867	1
Bin	TST_RDATA_TST_RDATA(11)	0	1	19865	1
Bin	TST_RDATA_TST_RDATA(11)	1	0	16959	1
Bin	TST_RDATA_TST_RDATA(10)	0	1	19770	1
Bin	TST_RDATA_TST_RDATA(10)	1	0	25883	1
Bin	TST_RDATA_TST_RDATA(9)	0	1	24487	1
Bin	TST_RDATA_TST_RDATA(9)	1	0	21581	1
Bin	TST_RDATA_TST_RDATA(8)	0	1	15360	1
Bin	TST_RDATA_TST_RDATA(8)	1	0	21473	1
Bin	TST_RDATA_TST_RDATA(7)	0	1	24311	1
Bin	TST_RDATA_TST_RDATA(7)	1	0	21405	1
Bin	TST_RDATA_TST_RDATA(6)	0	1	15276	1
Bin	TST_RDATA_TST_RDATA(6)	1	0	21389	1
Bin	TST_RDATA_TST_RDATA(5)	0	1	19636	1
Bin	TST_RDATA_TST_RDATA(5)	1	0	16730	1
Bin	TST_RDATA_TST_RDATA(4)	0	1	19726	1
Bin	TST_RDATA_TST_RDATA(4)	1	0	25839	1
Bin	TST_RDATA_TST_RDATA(3)	0	1	19890	1
Bin	TST_RDATA_TST_RDATA(3)	1	0	16984	1
Bin	TST_RDATA_TST_RDATA(2)	0	1	19821	1
Bin	TST_RDATA_TST_RDATA(2)	1	0	25934	1
Bin	TST_RDATA_TST_RDATA(1)	0	1	24534	1
Bin	TST_RDATA_TST_RDATA(1)	1	0	21628	1
Bin	TST_RDATA_TST_RDATA(0)	0	1	15397	1
Bin	TST_RDATA_TST_RDATA(0)	1	0	21510	1

Signal:

REG_SEL

	Element	From	To	Count	Threshold
Bin	(3)	0	1	93763	1
Bin	(3)	1	0	534190	1
Bin	(2)	0	1	41383	1
Bin	(2)	1	0	586570	1
Bin	(1)	0	1	135146	1
Bin	(1)	1	0	492807	1
Bin	(0)	0	1	42884	1
Bin	(0)	1	0	585069	1

Signal:

R_DATA_COMB

	Element	From	To	Count	Threshold
Bin	(31)	0	1	61817	1
Bin	(31)	1	0	63418	1
Bin	(30)	0	1	64320	1
Bin	(30)	1	0	65921	1
Bin	(29)	0	1	52689	1
Bin	(29)	1	0	54290	1
Bin	(28)	0	1	53007	1
Bin	(28)	1	0	54608	1
Bin	(27)	0	1	59233	1
Bin	(27)	1	0	60834	1
Bin	(26)	0	1	68854	1
Bin	(26)	1	0	70455	1
Bin	(25)	0	1	69277	1
Bin	(25)	1	0	70878	1
Bin	(24)	0	1	64161	1
Bin	(24)	1	0	65762	1
Bin	(23)	0	1	68181	1
Bin	(23)	1	0	69782	1
Bin	(22)	0	1	74880	1
Bin	(22)	1	0	76481	1
Bin	(21)	0	1	77350	1
Bin	(21)	1	0	78951	1
Bin	(20)	0	1	74968	1
Bin	(20)	1	0	76569	1
Bin	(19)	0	1	88183	1
Bin	(19)	1	0	89784	1
Bin	(18)	0	1	112340	1
Bin	(18)	1	0	113941	1
Bin	(17)	0	1	97281	1
Bin	(17)	1	0	98882	1
Bin	(16)	0	1	136794	1
Bin	(16)	1	0	138395	1
Bin	(15)	0	1	88751	1
Bin	(15)	1	0	90352	1
Bin	(14)	0	1	79018	1
Bin	(14)	1	0	80619	1
Bin	(13)	0	1	78646	1
Bin	(13)	1	0	80247	1
Bin	(12)	0	1	84973	1
Bin	(12)	1	0	86574	1
Bin	(11)	0	1	107132	1
Bin	(11)	1	0	108733	1
Bin	(10)	0	1	85855	1
Bin	(10)	1	0	87456	1
Bin	(9)	0	1	90720	1
Bin	(9)	1	0	92321	1
Bin	(8)	0	1	94803	1
Bin	(8)	1	0	96404	1
Bin	(7)	0	1	110343	1
Bin	(7)	1	0	111944	1
Bin	(6)	0	1	117632	1
Bin	(6)	1	0	119233	1
Bin	(5)	0	1	89868	1
Bin	(5)	1	0	91469	1
Bin	(4)	0	1	147263	1
Bin	(4)	1	0	148864	1
Bin	(3)	0	1	127878	1
Bin	(3)	1	0	129479	1
Bin	(2)	0	1	140095	1
Bin	(2)	1	0	141696	1
Bin	(1)	0	1	212662	1
Bin	(1)	1	0	214263	1
Bin	(0)	0	1	256237	1
Bin	(0)	1	0	257838	1

Signal:

READ_DATA_MASK_N

	Element	From	To	Count	Threshold
Bin	(31)	0	1	27488021	1
Bin	(31)	1	0	37491	1
Bin	(30)	0	1	27488021	1
Bin	(30)	1	0	37491	1
Bin	(29)	0	1	27488021	1
Bin	(29)	1	0	37491	1
Bin	(28)	0	1	27488021	1
Bin	(28)	1	0	37491	1
Bin	(27)	0	1	27488021	1
Bin	(27)	1	0	37491	1
Bin	(26)	0	1	27488021	1
Bin	(26)	1	0	37491	1
Bin	(25)	0	1	27488021	1
Bin	(25)	1	0	37491	1
Bin	(24)	0	1	27488021	1
Bin	(24)	1	0	37491	1
Bin	(23)	0	1	27488403	1
Bin	(23)	1	0	37109	1
Bin	(22)	0	1	27488403	1
Bin	(22)	1	0	37109	1
Bin	(21)	0	1	27488403	1
Bin	(21)	1	0	37109	1
Bin	(20)	0	1	27488403	1
Bin	(20)	1	0	37109	1
Bin	(19)	0	1	27488403	1
Bin	(19)	1	0	37109	1
Bin	(18)	0	1	27488403	1
Bin	(18)	1	0	37109	1
Bin	(17)	0	1	27488403	1
Bin	(17)	1	0	37109	1
Bin	(16)	0	1	27488403	1
Bin	(16)	1	0	37109	1
Bin	(15)	0	1	27389228	1
Bin	(15)	1	0	136284	1
Bin	(14)	0	1	27389228	1
Bin	(14)	1	0	136284	1
Bin	(13)	0	1	27389228	1
Bin	(13)	1	0	136284	1
Bin	(12)	0	1	27389228	1
Bin	(12)	1	0	136284	1
Bin	(11)	0	1	27389228	1
Bin	(11)	1	0	136284	1
Bin	(10)	0	1	27389228	1
Bin	(10)	1	0	136284	1
Bin	(9)	0	1	27389228	1
Bin	(9)	1	0	136284	1
Bin	(8)	0	1	27389228	1
Bin	(8)	1	0	136284	1
Bin	(7)	0	1	27390472	1
Bin	(7)	1	0	135040	1
Bin	(6)	0	1	27390472	1
Bin	(6)	1	0	135040	1
Bin	(5)	0	1	27390472	1
Bin	(5)	1	0	135040	1
Bin	(4)	0	1	27390472	1
Bin	(4)	1	0	135040	1
Bin	(3)	0	1	27390472	1
Bin	(3)	1	0	135040	1
Bin	(2)	0	1	27390472	1
Bin	(2)	1	0	135040	1
Bin	(1)	0	1	27390472	1
Bin	(1)	1	0	135040	1
Bin	(0)	0	1	27390472	1
Bin	(0)	1	0	135040	1

Signal:

TEST_REGISTERS_OUT_I

	Element	From	To	Count	Threshold
Bin	TST_CONTROL_TMAENA	0	1	648	1
Bin	TST_CONTROL_TMAENA	1	0	2249	1
Bin	TST_CONTROL_TWRSTB	0	1	32343	1
Bin	TST_CONTROL_TWRSTB	1	0	35235	1
Bin	TST_DEST_TST_ADDR(15)	0	1	5	1
Bin	TST_DEST_TST_ADDR(15)	1	0	51015	1
Bin	TST_DEST_TST_ADDR(14)	0	1	5	1
Bin	TST_DEST_TST_ADDR(14)	1	0	51015	1
Bin	TST_DEST_TST_ADDR(13)	0	1	5	1
Bin	TST_DEST_TST_ADDR(13)	1	0	51015	1
Bin	TST_DEST_TST_ADDR(12)	0	1	5	1
Bin	TST_DEST_TST_ADDR(12)	1	0	51015	1
Bin	TST_DEST_TST_ADDR(11)	0	1	2565	1
Bin	TST_DEST_TST_ADDR(11)	1	0	53320	1
Bin	TST_DEST_TST_ADDR(10)	0	1	5125	1
Bin	TST_DEST_TST_ADDR(10)	1	0	55880	1
Bin	TST_DEST_TST_ADDR(9)	0	1	10245	1
Bin	TST_DEST_TST_ADDR(9)	1	0	61000	1
Bin	TST_DEST_TST_ADDR(8)	0	1	20485	1
Bin	TST_DEST_TST_ADDR(8)	1	0	71240	1
Bin	TST_DEST_TST_ADDR(7)	0	1	165	1
Bin	TST_DEST_TST_ADDR(7)	1	0	1766	1
Bin	TST_DEST_TST_ADDR(6)	0	1	355	1
Bin	TST_DEST_TST_ADDR(6)	1	0	1956	1
Bin	TST_DEST_TST_ADDR(5)	0	1	705	1
Bin	TST_DEST_TST_ADDR(5)	1	0	2306	1
Bin	TST_DEST_TST_ADDR(4)	0	1	3617	1
Bin	TST_DEST_TST_ADDR(4)	1	0	5218	1
Bin	TST_DEST_TST_ADDR(3)	0	1	5036	1
Bin	TST_DEST_TST_ADDR(3)	1	0	6637	1
Bin	TST_DEST_TST_ADDR(2)	0	1	10348	1
Bin	TST_DEST_TST_ADDR(2)	1	0	11949	1
Bin	TST_DEST_TST_ADDR(1)	0	1	22453	1
Bin	TST_DEST_TST_ADDR(1)	1	0	24054	1
Bin	TST_DEST_TST_ADDR(0)	0	1	44900	1
Bin	TST_DEST_TST_ADDR(0)	1	0	46501	1
Bin	TST_DEST_TST_MTGT(3)	0	1	236	1
Bin	TST_DEST_TST_MTGT(3)	1	0	1837	1
Bin	TST_DEST_TST_MTGT(2)	0	1	373	1
Bin	TST_DEST_TST_MTGT(2)	1	0	1974	1
Bin	TST_DEST_TST_MTGT(1)	0	1	514	1
Bin	TST_DEST_TST_MTGT(1)	1	0	2115	1
Bin	TST_DEST_TST_MTGT(0)	0	1	979	1
Bin	TST_DEST_TST_MTGT(0)	1	0	2580	1
Bin	TST_WDATA_TST_WDATA(31)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(31)	1	0	3183	1
Bin	TST_WDATA_TST_WDATA(30)	0	1	1478	1
Bin	TST_WDATA_TST_WDATA(30)	1	0	3163	1
Bin	TST_WDATA_TST_WDATA(29)	0	1	1525	1
Bin	TST_WDATA_TST_WDATA(29)	1	0	3196	1
Bin	TST_WDATA_TST_WDATA(28)	0	1	1641	1
Bin	TST_WDATA_TST_WDATA(28)	1	0	3347	1
Bin	TST_WDATA_TST_WDATA(27)	0	1	1650	1
Bin	TST_WDATA_TST_WDATA(27)	1	0	3340	1
Bin	TST_WDATA_TST_WDATA(26)	0	1	1638	1
Bin	TST_WDATA_TST_WDATA(26)	1	0	3326	1
Bin	TST_WDATA_TST_WDATA(25)	0	1	1654	1
Bin	TST_WDATA_TST_WDATA(25)	1	0	3373	1
Bin	TST_WDATA_TST_WDATA(24)	0	1	1690	1
Bin	TST_WDATA_TST_WDATA(24)	1	0	3411	1
Bin	TST_WDATA_TST_WDATA(23)	0	1	1587	1
Bin	TST_WDATA_TST_WDATA(23)	1	0	3295	1
Bin	TST_WDATA_TST_WDATA(22)	0	1	1532	1
Bin	TST_WDATA_TST_WDATA(22)	1	0	3219	1
Bin	TST_WDATA_TST_WDATA(21)	0	1	1585	1
Bin	TST_WDATA_TST_WDATA(21)	1	0	3304	1
Bin	TST_WDATA_TST_WDATA(20)	0	1	1662	1
Bin	TST_WDATA_TST_WDATA(20)	1	0	3356	1
Bin	TST_WDATA_TST_WDATA(19)	0	1	1686	1
Bin	TST_WDATA_TST_WDATA(19)	1	0	3365	1
Bin	TST_WDATA_TST_WDATA(18)	0	1	1674	1
Bin	TST_WDATA_TST_WDATA(18)	1	0	3388	1
Bin	TST_WDATA_TST_WDATA(17)	0	1	1625	1
Bin	TST_WDATA_TST_WDATA(17)	1	0	3310	1
Bin	TST_WDATA_TST_WDATA(16)	0	1	1659	1
Bin	TST_WDATA_TST_WDATA(16)	1	0	3342	1
Bin	TST_WDATA_TST_WDATA(15)	0	1	1602	1
Bin	TST_WDATA_TST_WDATA(15)	1	0	3266	1
Bin	TST_WDATA_TST_WDATA(14)	0	1	1529	1
Bin	TST_WDATA_TST_WDATA(14)	1	0	3196	1
Bin	TST_WDATA_TST_WDATA(13)	0	1	1594	1
Bin	TST_WDATA_TST_WDATA(13)	1	0	3284	1
Bin	TST_WDATA_TST_WDATA(12)	0	1	1668	1
Bin	TST_WDATA_TST_WDATA(12)	1	0	3343	1
Bin	TST_WDATA_TST_WDATA(11)	0	1	1678	1
Bin	TST_WDATA_TST_WDATA(11)	1	0	3358	1
Bin	TST_WDATA_TST_WDATA(10)	0	1	1657	1
Bin	TST_WDATA_TST_WDATA(10)	1	0	3321	1
Bin	TST_WDATA_TST_WDATA(9)	0	1	1685	1
Bin	TST_WDATA_TST_WDATA(9)	1	0	3373	1
Bin	TST_WDATA_TST_WDATA(8)	0	1	1714	1
Bin	TST_WDATA_TST_WDATA(8)	1	0	3423	1
Bin	TST_WDATA_TST_WDATA(7)	0	1	1608	1
Bin	TST_WDATA_TST_WDATA(7)	1	0	3277	1
Bin	TST_WDATA_TST_WDATA(6)	0	1	1557	1
Bin	TST_WDATA_TST_WDATA(6)	1	0	3235	1
Bin	TST_WDATA_TST_WDATA(5)	0	1	1589	1
Bin	TST_WDATA_TST_WDATA(5)	1	0	3243	1
Bin	TST_WDATA_TST_WDATA(4)	0	1	1662	1
Bin	TST_WDATA_TST_WDATA(4)	1	0	3323	1
Bin	TST_WDATA_TST_WDATA(3)	0	1	1653	1
Bin	TST_WDATA_TST_WDATA(3)	1	0	3305	1
Bin	TST_WDATA_TST_WDATA(2)	0	1	1678	1
Bin	TST_WDATA_TST_WDATA(2)	1	0	3328	1
Bin	TST_WDATA_TST_WDATA(1)	0	1	1701	1
Bin	TST_WDATA_TST_WDATA(1)	1	0	3389	1
Bin	TST_WDATA_TST_WDATA(0)	0	1	1696	1
Bin	TST_WDATA_TST_WDATA(0)	1	0	3367	1

Signal:

WRITE_EN

	Element	From	To	Count	Threshold
Bin	(3)	0	1	219383	1
Bin	(3)	1	0	220984	1
Bin	(2)	0	1	219383	1
Bin	(2)	1	0	220984	1
Bin	(1)	0	1	219383	1
Bin	(1)	1	0	220984	1
Bin	(0)	0	1	219383	1
Bin	(0)	1	0	220984	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 116:

 write = '1' and cs = '1' 
 <---LHS--->     <-RHS-->

	LHS	RHS	Count	Threshold
Bin	False	True	406969	1
Bin	True	False	1107198	1
Bin	True	True	219383	1

"=" expression on line 116:

write = '1'

	Evaluated to	Count	Threshold
Bin	False	54353997	1
Bin	True	1326581	1

"=" expression on line 116:

cs = '1'

	Evaluated to	Count	Threshold
Bin	False	55054226	1
Bin	True	626352	1

"=" expression on line 327:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	28927695	1
Bin	True	15862	1

"and" expression on line 330:

 cs = '1' and read = '1' 
 <-LHS-->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	2991543	1
Bin	True	False	219383	1
Bin	True	True	93793	1

"=" expression on line 330:

cs = '1'

	Evaluated to	Count	Threshold
Bin	False	14144254	1
Bin	True	313176	1

"=" expression on line 330:

read = '1'

	Evaluated to	Count	Threshold
Bin	False	11372094	1
Bin	True	3085336	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 352 to 353:

352:    -- psl tst_control_write_access_cov : cover 
353:    -- {((cs='1') and (write='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 42874
Threshold: 1

PSL cover point on lines 355 to 356:

355:    -- psl tst_control_read_access_cov : cover 
356:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point on lines 358 to 359:

358:    -- psl tst_dest_write_access_cov : cover 
359:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 135136
Threshold: 1

PSL cover point on lines 361 to 362:

361:    -- psl tst_dest_read_access_cov : cover 
362:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point on lines 364 to 365:

364:    -- psl tst_wdata_write_access_cov : cover 
365:    -- {((cs='1') and (write='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 41373
Threshold: 1

PSL cover point on lines 367 to 368:

367:    -- psl tst_wdata_read_access_cov : cover 
368:    -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point on lines 370 to 371:

370:    -- psl tst_rdata_read_access_cov : cover 
371:    -- {((cs='1') and (read='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 93763
Threshold: 1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on line 116:

Signal assignment statement on line 116:

Signal assignment statement on line 116:

Sequential statement on lines 311 to 320:

Signal assignment statement on lines 312 to 314:

Signal assignment statement on lines 315 to 317:

Signal assignment statement on line 318:

Signal assignment statement on line 319:

Signal assignment statement on line 320:

If statement on lines 327 to 333:

Signal assignment statement on line 328:

If statement on lines 330 to 332:

Signal assignment statement on line 331:

Signal assignment statement on lines 340 to 343:

Signal assignment statement on line 345:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 116:

"case" / "with" / "select" choice on line 314:

"case" / "with" / "select" choice on line 317:

"case" / "with" / "select" choice on line 318:

"case" / "with" / "select" choice on line 319:

"case" / "with" / "select" choice on line 320:

"if" / "when" / "else" condition on line 327:

"if" / "when" / "else" condition on line 329:

"if" / "when" / "else" condition on line 330:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 116:

"=" expression on line 116:

"=" expression on line 116:

"=" expression on line 327:

"and" expression on line 330:

"=" expression on line 330:

"=" expression on line 330:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 352 to 353:

PSL cover point on lines 355 to 356:

PSL cover point on lines 358 to 359:

PSL cover point on lines 361 to 362:

PSL cover point on lines 364 to 365:

PSL cover point on lines 367 to 368:

PSL cover point on lines 370 to 371: