NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ADDRESS_DECODER_TEST_REGISTERS_COMP	100.0 % (15/15)	100.0 % (10/10)	100.0 % (42/42)	100.0 % (2/2)	N.A.	N.A.	100.0 % (69/69)
TST_CONTROL_TMAENA_REG_COMP	100.0 % (5/5)	100.0 % (6/6)	100.0 % (18/18)	100.0 % (10/10)	N.A.	N.A.	100.0 % (39/39)
TST_CONTROL_TWRSTB_REG_COMP	100.0 % (4/4)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (32/32)
TST_DEST_TST_ADDR_SLICE_1_REG_COMP	100.0 % (33/33)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (179/179)
TST_DEST_TST_ADDR_SLICE_2_REG_COMP	100.0 % (33/33)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (179/179)
TST_DEST_TST_MTGT_REG_COMP	100.0 % (17/17)	100.0 % (24/24)	100.0 % (36/36)	100.0 % (22/22)	N.A.	N.A.	100.0 % (99/99)
TST_WDATA_TST_WDATA_SLICE_1_REG_COMP	100.0 % (33/33)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (179/179)
TST_WDATA_TST_WDATA_SLICE_2_REG_COMP	100.0 % (33/33)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (179/179)
TST_WDATA_TST_WDATA_SLICE_3_REG_COMP	100.0 % (33/33)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (179/179)
TST_WDATA_TST_WDATA_SLICE_4_REG_COMP	100.0 % (33/33)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (179/179)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP	100.0 % (15/15)	100.0 % (13/13)	100.0 % (590/590)	100.0 % (16/16)	N.A.	100.0 % (7/7)	100.0 % (641/641)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 56217278
Threshold: 1

Signal assignment statement:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 219247
Threshold: 1

Signal assignment statement:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');
Count: 55998031
Threshold: 1

Sequential statement:

311:    with address(7 downto 2) select r_data_comb <= 
312:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
...
319:        test_registers_in.tst_rdata_tst_rdata when "000011", 
320:        (others => '0') when others;

Count: 55856041
Threshold: 1

Signal assignment statement:

312:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
313:        test_registers_out_i.tst_control_twrstb & 
314:        test_registers_out_i.tst_control_tmaena when "000000",

Count: 137909
Threshold: 1

Signal assignment statement:

315:        '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & 
316:        test_registers_out_i.tst_dest_tst_mtgt & 
317:        test_registers_out_i.tst_dest_tst_addr when "000001",

Count: 397465
Threshold: 1

Signal assignment statement:

318: test_registers_out_i.tst_wdata_tst_wdata when "000010",
Count: 9675571
Threshold: 1

Signal assignment statement:

319: test_registers_in.tst_rdata_tst_rdata when "000011",
Count: 149084
Threshold: 1

Signal assignment statement:

320: (others => '0') when others;
Count: 45496012
Threshold: 1

If statement:

327:        if (res_n = '0') then 
328:            r_data <= (others => '0'); 
...
332:            end if; 
333:        end if;

Count: 26555802
Threshold: 1

Signal assignment statement:

328: r_data <= (others => '0');
Count: 15860
Threshold: 1

If statement:

330:            if (cs = '1' and read = '1') then 
331:                r_data <= r_data_comb and read_data_mask_n; 
332:            end if;

Count: 13263556
Threshold: 1

Signal assignment statement:

331: r_data <= r_data_comb and read_data_mask_n;
Count: 93759
Threshold: 1

Signal assignment statement:

340:      be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &  
341:      be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &  
342:      be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &  
343:      be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;

Count: 55589666
Threshold: 1

Signal assignment statement:

345: Test_registers_out <= Test_registers_out_i;
Count: 202367
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');

	Evaluated to	Count	Threshold
Bin	True	219247	1
Bin	False	55998031	1

"case" / "with" / "select" choice:

314: test_registers_out_i.tst_control_tmaena when "000000",

	Choice of	Count	Threshold
Bin	`"000000"`	137909	1

"case" / "with" / "select" choice:

317: test_registers_out_i.tst_dest_tst_addr when "000001",

	Choice of	Count	Threshold
Bin	`"000001"`	397465	1

"case" / "with" / "select" choice:

318: test_registers_out_i.tst_wdata_tst_wdata when "000010",

	Choice of	Count	Threshold
Bin	`"000010"`	9675571	1

"case" / "with" / "select" choice:

319: test_registers_in.tst_rdata_tst_rdata when "000011",

	Choice of	Count	Threshold
Bin	`"000011"`	149084	1

"case" / "with" / "select" choice:

320: (others => '0') when others;

	Choice of	Count	Threshold
Bin	`others`	45496012	1

"if" / "when" / "else" condition:

327: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	15860	1
Bin	False	26539942	1

"if" / "when" / "else" condition:

329: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	13263556	1
Bin	False	13276386	1

"if" / "when" / "else" condition:

330: if (cs = '1' and read = '1') then

	Evaluated to	Count	Threshold
Bin	True	93759	1
Bin	False	13169797	1

Uncovered toggles:

Excluded toggles:

Port:

ADDRESS(1)

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file

Port:

ADDRESS(0)

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13267459	1
Bin	1	0	13269059	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

ADDRESS(7)

	From	To	Count	Threshold
Bin	0	1	16744778	1
Bin	1	0	11049255	1

Port:

ADDRESS(6)

	From	To	Count	Threshold
Bin	0	1	328560	1
Bin	1	0	27465473	1

Port:

ADDRESS(5)

	From	To	Count	Threshold
Bin	0	1	576099	1
Bin	1	0	27217934	1

Port:

ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	436079	1
Bin	1	0	27357954	1

Port:

ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	27015237	1
Bin	1	0	778796	1

Port:

ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	17655249	1
Bin	1	0	10138784	1

Port:

ADDRESS(1)

	From	To	Count	Threshold
Bin	1	0	27794033	1

Port:

ADDRESS(0)

	From	To	Count	Threshold
Bin	1	0	27794033	1

Port:

W_DATA(31)

	From	To	Count	Threshold
Bin	0	1	61362	1
Bin	1	0	1028483	1

Port:

W_DATA(30)

	From	To	Count	Threshold
Bin	0	1	67108	1
Bin	1	0	1022737	1

Port:

W_DATA(29)

	From	To	Count	Threshold
Bin	0	1	63097	1
Bin	1	0	1026748	1

Port:

W_DATA(28)

	From	To	Count	Threshold
Bin	0	1	91439	1
Bin	1	0	998406	1

Port:

W_DATA(27)

	From	To	Count	Threshold
Bin	0	1	79643	1
Bin	1	0	1010202	1

Port:

W_DATA(26)

	From	To	Count	Threshold
Bin	0	1	76527	1
Bin	1	0	1013318	1

Port:

W_DATA(25)

	From	To	Count	Threshold
Bin	0	1	88276	1
Bin	1	0	1001569	1

Port:

W_DATA(24)

	From	To	Count	Threshold
Bin	0	1	78188	1
Bin	1	0	1011657	1

Port:

W_DATA(23)

	From	To	Count	Threshold
Bin	0	1	70931	1
Bin	1	0	1018914	1

Port:

W_DATA(22)

	From	To	Count	Threshold
Bin	0	1	108138	1
Bin	1	0	981707	1

Port:

W_DATA(21)

	From	To	Count	Threshold
Bin	0	1	74867	1
Bin	1	0	1014978	1

Port:

W_DATA(20)

	From	To	Count	Threshold
Bin	0	1	80468	1
Bin	1	0	1009377	1

Port:

W_DATA(19)

	From	To	Count	Threshold
Bin	0	1	110009	1
Bin	1	0	979836	1

Port:

W_DATA(18)

	From	To	Count	Threshold
Bin	0	1	131558	1
Bin	1	0	958287	1

Port:

W_DATA(17)

	From	To	Count	Threshold
Bin	0	1	123951	1
Bin	1	0	965894	1

Port:

W_DATA(16)

	From	To	Count	Threshold
Bin	0	1	193513	1
Bin	1	0	896332	1

Port:

W_DATA(15)

	From	To	Count	Threshold
Bin	0	1	72382	1
Bin	1	0	1017463	1

Port:

W_DATA(14)

	From	To	Count	Threshold
Bin	0	1	86120	1
Bin	1	0	1003725	1

Port:

W_DATA(13)

	From	To	Count	Threshold
Bin	0	1	76572	1
Bin	1	0	1013273	1

Port:

W_DATA(12)

	From	To	Count	Threshold
Bin	0	1	80428	1
Bin	1	0	1009417	1

Port:

W_DATA(11)

	From	To	Count	Threshold
Bin	0	1	97296	1
Bin	1	0	992549	1

Port:

W_DATA(10)

	From	To	Count	Threshold
Bin	0	1	116973	1
Bin	1	0	972872	1

Port:

W_DATA(9)

	From	To	Count	Threshold
Bin	0	1	170870	1
Bin	1	0	918975	1

Port:

W_DATA(8)

	From	To	Count	Threshold
Bin	0	1	150526	1
Bin	1	0	939319	1

Port:

W_DATA(7)

	From	To	Count	Threshold
Bin	0	1	126416	1
Bin	1	0	963429	1

Port:

W_DATA(6)

	From	To	Count	Threshold
Bin	0	1	109550	1
Bin	1	0	980295	1

Port:

W_DATA(5)

	From	To	Count	Threshold
Bin	0	1	103929	1
Bin	1	0	985916	1

Port:

W_DATA(4)

	From	To	Count	Threshold
Bin	0	1	162358	1
Bin	1	0	927487	1

Port:

W_DATA(3)

	From	To	Count	Threshold
Bin	0	1	135873	1
Bin	1	0	953972	1

Port:

W_DATA(2)

	From	To	Count	Threshold
Bin	0	1	159944	1
Bin	1	0	929901	1

Port:

W_DATA(1)

	From	To	Count	Threshold
Bin	0	1	236123	1
Bin	1	0	853722	1

Port:

W_DATA(0)

	From	To	Count	Threshold
Bin	0	1	198401	1
Bin	1	0	891444	1

Port:

R_DATA(31)

	From	To	Count	Threshold
Bin	0	1	1353	1
Bin	1	0	2953	1

Port:

R_DATA(30)

	From	To	Count	Threshold
Bin	0	1	1291	1
Bin	1	0	2891	1

Port:

R_DATA(29)

	From	To	Count	Threshold
Bin	0	1	1302	1
Bin	1	0	2902	1

Port:

R_DATA(28)

	From	To	Count	Threshold
Bin	0	1	1449	1
Bin	1	0	3049	1

Port:

R_DATA(27)

	From	To	Count	Threshold
Bin	0	1	1470	1
Bin	1	0	3070	1

Port:

R_DATA(26)

	From	To	Count	Threshold
Bin	0	1	1449	1
Bin	1	0	3049	1

Port:

R_DATA(25)

	From	To	Count	Threshold
Bin	0	1	1458	1
Bin	1	0	3058	1

Port:

R_DATA(24)

	From	To	Count	Threshold
Bin	0	1	1527	1
Bin	1	0	3127	1

Port:

R_DATA(23)

	From	To	Count	Threshold
Bin	0	1	1407	1
Bin	1	0	3007	1

Port:

R_DATA(22)

	From	To	Count	Threshold
Bin	0	1	1336	1
Bin	1	0	2936	1

Port:

R_DATA(21)

	From	To	Count	Threshold
Bin	0	1	1386	1
Bin	1	0	2986	1

Port:

R_DATA(20)

	From	To	Count	Threshold
Bin	0	1	1483	1
Bin	1	0	3083	1

Port:

R_DATA(19)

	From	To	Count	Threshold
Bin	0	1	1469	1
Bin	1	0	3069	1

Port:

R_DATA(18)

	From	To	Count	Threshold
Bin	0	1	1460	1
Bin	1	0	3060	1

Port:

R_DATA(17)

	From	To	Count	Threshold
Bin	0	1	1451	1
Bin	1	0	3051	1

Port:

R_DATA(16)

	From	To	Count	Threshold
Bin	0	1	1484	1
Bin	1	0	3084	1

Port:

R_DATA(15)

	From	To	Count	Threshold
Bin	0	1	1399	1
Bin	1	0	2999	1

Port:

R_DATA(14)

	From	To	Count	Threshold
Bin	0	1	1325	1
Bin	1	0	2925	1

Port:

R_DATA(13)

	From	To	Count	Threshold
Bin	0	1	1392	1
Bin	1	0	2992	1

Port:

R_DATA(12)

	From	To	Count	Threshold
Bin	0	1	1477	1
Bin	1	0	3077	1

Port:

R_DATA(11)

	From	To	Count	Threshold
Bin	0	1	1502	1
Bin	1	0	3102	1

Port:

R_DATA(10)

	From	To	Count	Threshold
Bin	0	1	1472	1
Bin	1	0	3072	1

Port:

R_DATA(9)

	From	To	Count	Threshold
Bin	0	1	1505	1
Bin	1	0	3105	1

Port:

R_DATA(8)

	From	To	Count	Threshold
Bin	0	1	1510	1
Bin	1	0	3110	1

Port:

R_DATA(7)

	From	To	Count	Threshold
Bin	0	1	1463	1
Bin	1	0	3063	1

Port:

R_DATA(6)

	From	To	Count	Threshold
Bin	0	1	1404	1
Bin	1	0	3004	1

Port:

R_DATA(5)

	From	To	Count	Threshold
Bin	0	1	1428	1
Bin	1	0	3028	1

Port:

R_DATA(4)

	From	To	Count	Threshold
Bin	0	1	1454	1
Bin	1	0	3054	1

Port:

R_DATA(3)

	From	To	Count	Threshold
Bin	0	1	1477	1
Bin	1	0	3077	1

Port:

R_DATA(2)

	From	To	Count	Threshold
Bin	0	1	1485	1
Bin	1	0	3085	1

Port:

R_DATA(1)

	From	To	Count	Threshold
Bin	0	1	1484	1
Bin	1	0	3084	1

Port:

R_DATA(0)

	From	To	Count	Threshold
Bin	0	1	1549	1
Bin	1	0	3149	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	313006	1
Bin	1	0	314606	1

Port:

READ

	From	To	Count	Threshold
Bin	0	1	26704188	1
Bin	1	0	1089845	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	1089845	1
Bin	1	0	26704188	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Port:

LOCK_1

	From	To	Count	Threshold
Bin	0	1	2626	1
Bin	1	0	1027	1

Port:

LOCK_2

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

TEST_REGISTERS_OUT.TST_CONTROL_TMAENA

	From	To	Count	Threshold
Bin	0	1	648	1
Bin	1	0	2248	1

Port:

TEST_REGISTERS_OUT.TST_CONTROL_TWRSTB

	From	To	Count	Threshold
Bin	0	1	32309	1
Bin	1	0	35200	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(15)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(14)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(13)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(12)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(11)

	From	To	Count	Threshold
Bin	0	1	15	1
Bin	1	0	1615	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(10)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(9)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1645	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(8)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1685	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(7)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	1765	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(6)

	From	To	Count	Threshold
Bin	0	1	355	1
Bin	1	0	1955	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(5)

	From	To	Count	Threshold
Bin	0	1	705	1
Bin	1	0	2305	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(4)

	From	To	Count	Threshold
Bin	0	1	3617	1
Bin	1	0	5217	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(3)

	From	To	Count	Threshold
Bin	0	1	5031	1
Bin	1	0	6631	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(2)

	From	To	Count	Threshold
Bin	0	1	10323	1
Bin	1	0	11923	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(1)

	From	To	Count	Threshold
Bin	0	1	22448	1
Bin	1	0	24048	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_ADDR(0)

	From	To	Count	Threshold
Bin	0	1	44884	1
Bin	1	0	46484	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_MTGT(3)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	1835	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_MTGT(2)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	1974	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_MTGT(1)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	2114	1

Port:

TEST_REGISTERS_OUT.TST_DEST_TST_MTGT(0)

	From	To	Count	Threshold
Bin	0	1	979	1
Bin	1	0	2579	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(31)

	From	To	Count	Threshold
Bin	0	1	1535	1
Bin	1	0	3135	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(30)

	From	To	Count	Threshold
Bin	0	1	1484	1
Bin	1	0	3084	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(29)

	From	To	Count	Threshold
Bin	0	1	1491	1
Bin	1	0	3091	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(28)

	From	To	Count	Threshold
Bin	0	1	1631	1
Bin	1	0	3231	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(27)

	From	To	Count	Threshold
Bin	0	1	1645	1
Bin	1	0	3245	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(26)

	From	To	Count	Threshold
Bin	0	1	1629	1
Bin	1	0	3229	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(25)

	From	To	Count	Threshold
Bin	0	1	1641	1
Bin	1	0	3241	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(24)

	From	To	Count	Threshold
Bin	0	1	1713	1
Bin	1	0	3313	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(23)

	From	To	Count	Threshold
Bin	0	1	1587	1
Bin	1	0	3187	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(22)

	From	To	Count	Threshold
Bin	0	1	1526	1
Bin	1	0	3126	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(21)

	From	To	Count	Threshold
Bin	0	1	1560	1
Bin	1	0	3160	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(20)

	From	To	Count	Threshold
Bin	0	1	1658	1
Bin	1	0	3258	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(19)

	From	To	Count	Threshold
Bin	0	1	1646	1
Bin	1	0	3246	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(18)

	From	To	Count	Threshold
Bin	0	1	1636	1
Bin	1	0	3236	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(17)

	From	To	Count	Threshold
Bin	0	1	1632	1
Bin	1	0	3232	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(16)

	From	To	Count	Threshold
Bin	0	1	1670	1
Bin	1	0	3270	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(15)

	From	To	Count	Threshold
Bin	0	1	1575	1
Bin	1	0	3175	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(14)

	From	To	Count	Threshold
Bin	0	1	1501	1
Bin	1	0	3101	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(13)

	From	To	Count	Threshold
Bin	0	1	1559	1
Bin	1	0	3159	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(12)

	From	To	Count	Threshold
Bin	0	1	1640	1
Bin	1	0	3240	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(11)

	From	To	Count	Threshold
Bin	0	1	1646	1
Bin	1	0	3246	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(10)

	From	To	Count	Threshold
Bin	0	1	1646	1
Bin	1	0	3246	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(9)

	From	To	Count	Threshold
Bin	0	1	1672	1
Bin	1	0	3272	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(8)

	From	To	Count	Threshold
Bin	0	1	1681	1
Bin	1	0	3281	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(7)

	From	To	Count	Threshold
Bin	0	1	1633	1
Bin	1	0	3233	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(6)

	From	To	Count	Threshold
Bin	0	1	1567	1
Bin	1	0	3167	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(5)

	From	To	Count	Threshold
Bin	0	1	1601	1
Bin	1	0	3201	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(4)

	From	To	Count	Threshold
Bin	0	1	1637	1
Bin	1	0	3237	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(3)

	From	To	Count	Threshold
Bin	0	1	1640	1
Bin	1	0	3240	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(2)

	From	To	Count	Threshold
Bin	0	1	1655	1
Bin	1	0	3255	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(1)

	From	To	Count	Threshold
Bin	0	1	1656	1
Bin	1	0	3256	1

Port:

TEST_REGISTERS_OUT.TST_WDATA_TST_WDATA(0)

	From	To	Count	Threshold
Bin	0	1	1722	1
Bin	1	0	3322	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(31)

	From	To	Count	Threshold
Bin	0	1	23976	1
Bin	1	0	21069	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(30)

	From	To	Count	Threshold
Bin	0	1	14991	1
Bin	1	0	21103	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(29)

	From	To	Count	Threshold
Bin	0	1	19372	1
Bin	1	0	16465	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(28)

	From	To	Count	Threshold
Bin	0	1	19815	1
Bin	1	0	25927	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(27)

	From	To	Count	Threshold
Bin	0	1	19917	1
Bin	1	0	17010	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(26)

	From	To	Count	Threshold
Bin	0	1	19815	1
Bin	1	0	25927	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(25)

	From	To	Count	Threshold
Bin	0	1	24517	1
Bin	1	0	21610	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(24)

	From	To	Count	Threshold
Bin	0	1	15554	1
Bin	1	0	21666	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(23)

	From	To	Count	Threshold
Bin	0	1	24236	1
Bin	1	0	21329	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(22)

	From	To	Count	Threshold
Bin	0	1	15250	1
Bin	1	0	21362	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(21)

	From	To	Count	Threshold
Bin	0	1	19719	1
Bin	1	0	16812	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(20)

	From	To	Count	Threshold
Bin	0	1	19825	1
Bin	1	0	25937	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(19)

	From	To	Count	Threshold
Bin	0	1	19878	1
Bin	1	0	16971	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(18)

	From	To	Count	Threshold
Bin	0	1	19831	1
Bin	1	0	25943	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(17)

	From	To	Count	Threshold
Bin	0	1	24351	1
Bin	1	0	21444	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(16)

	From	To	Count	Threshold
Bin	0	1	15283	1
Bin	1	0	21395	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(15)

	From	To	Count	Threshold
Bin	0	1	24152	1
Bin	1	0	21245	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(14)

	From	To	Count	Threshold
Bin	0	1	15142	1
Bin	1	0	21254	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(13)

	From	To	Count	Threshold
Bin	0	1	19605	1
Bin	1	0	16698	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(12)

	From	To	Count	Threshold
Bin	0	1	19767	1
Bin	1	0	25879	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(11)

	From	To	Count	Threshold
Bin	0	1	19913	1
Bin	1	0	17006	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(10)

	From	To	Count	Threshold
Bin	0	1	19798	1
Bin	1	0	25910	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(9)

	From	To	Count	Threshold
Bin	0	1	24437	1
Bin	1	0	21530	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(8)

	From	To	Count	Threshold
Bin	0	1	15329	1
Bin	1	0	21441	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(7)

	From	To	Count	Threshold
Bin	0	1	24318	1
Bin	1	0	21411	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(6)

	From	To	Count	Threshold
Bin	0	1	15262	1
Bin	1	0	21374	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(5)

	From	To	Count	Threshold
Bin	0	1	19698	1
Bin	1	0	16791	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(4)

	From	To	Count	Threshold
Bin	0	1	19654	1
Bin	1	0	25766	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(3)

	From	To	Count	Threshold
Bin	0	1	19827	1
Bin	1	0	16920	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(2)

	From	To	Count	Threshold
Bin	0	1	19835	1
Bin	1	0	25947	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(1)

	From	To	Count	Threshold
Bin	0	1	24452	1
Bin	1	0	21545	1

Port:

TEST_REGISTERS_IN.TST_RDATA_TST_RDATA(0)

	From	To	Count	Threshold
Bin	0	1	15418	1
Bin	1	0	21530	1

Signal:

REG_SEL(3)

	From	To	Count	Threshold
Bin	0	1	93729	1
Bin	1	0	533883	1

Signal:

REG_SEL(2)

	From	To	Count	Threshold
Bin	0	1	41349	1
Bin	1	0	586263	1

Signal:

REG_SEL(1)

	From	To	Count	Threshold
Bin	0	1	135078	1
Bin	1	0	492534	1

Signal:

REG_SEL(0)

	From	To	Count	Threshold
Bin	0	1	42850	1
Bin	1	0	584762	1

Signal:

R_DATA_COMB(31)

	From	To	Count	Threshold
Bin	0	1	80833	1
Bin	1	0	82433	1

Signal:

R_DATA_COMB(30)

	From	To	Count	Threshold
Bin	0	1	56489	1
Bin	1	0	58089	1

Signal:

R_DATA_COMB(29)

	From	To	Count	Threshold
Bin	0	1	62703	1
Bin	1	0	64303	1

Signal:

R_DATA_COMB(28)

	From	To	Count	Threshold
Bin	0	1	63287	1
Bin	1	0	64887	1

Signal:

R_DATA_COMB(27)

	From	To	Count	Threshold
Bin	0	1	73258	1
Bin	1	0	74858	1

Signal:

R_DATA_COMB(26)

	From	To	Count	Threshold
Bin	0	1	98885	1
Bin	1	0	100485	1

Signal:

R_DATA_COMB(25)

	From	To	Count	Threshold
Bin	0	1	74606	1
Bin	1	0	76206	1

Signal:

R_DATA_COMB(24)

	From	To	Count	Threshold
Bin	0	1	75120	1
Bin	1	0	76720	1

Signal:

R_DATA_COMB(23)

	From	To	Count	Threshold
Bin	0	1	66243	1
Bin	1	0	67843	1

Signal:

R_DATA_COMB(22)

	From	To	Count	Threshold
Bin	0	1	85739	1
Bin	1	0	87339	1

Signal:

R_DATA_COMB(21)

	From	To	Count	Threshold
Bin	0	1	76389	1
Bin	1	0	77989	1

Signal:

R_DATA_COMB(20)

	From	To	Count	Threshold
Bin	0	1	77436	1
Bin	1	0	79036	1

Signal:

R_DATA_COMB(19)

	From	To	Count	Threshold
Bin	0	1	130243	1
Bin	1	0	131843	1

Signal:

R_DATA_COMB(18)

	From	To	Count	Threshold
Bin	0	1	139271	1
Bin	1	0	140871	1

Signal:

R_DATA_COMB(17)

	From	To	Count	Threshold
Bin	0	1	136281	1
Bin	1	0	137881	1

Signal:

R_DATA_COMB(16)

	From	To	Count	Threshold
Bin	0	1	142694	1
Bin	1	0	144294	1

Signal:

R_DATA_COMB(15)

	From	To	Count	Threshold
Bin	0	1	73812	1
Bin	1	0	75412	1

Signal:

R_DATA_COMB(14)

	From	To	Count	Threshold
Bin	0	1	113126	1
Bin	1	0	114726	1

Signal:

R_DATA_COMB(13)

	From	To	Count	Threshold
Bin	0	1	88661	1
Bin	1	0	90261	1

Signal:

R_DATA_COMB(12)

	From	To	Count	Threshold
Bin	0	1	94037	1
Bin	1	0	95637	1

Signal:

R_DATA_COMB(11)

	From	To	Count	Threshold
Bin	0	1	113543	1
Bin	1	0	115143	1

Signal:

R_DATA_COMB(10)

	From	To	Count	Threshold
Bin	0	1	89948	1
Bin	1	0	91548	1

Signal:

R_DATA_COMB(9)

	From	To	Count	Threshold
Bin	0	1	137506	1
Bin	1	0	139106	1

Signal:

R_DATA_COMB(8)

	From	To	Count	Threshold
Bin	0	1	111449	1
Bin	1	0	113049	1

Signal:

R_DATA_COMB(7)

	From	To	Count	Threshold
Bin	0	1	141248	1
Bin	1	0	142848	1

Signal:

R_DATA_COMB(6)

	From	To	Count	Threshold
Bin	0	1	162248	1
Bin	1	0	163848	1

Signal:

R_DATA_COMB(5)

	From	To	Count	Threshold
Bin	0	1	125904	1
Bin	1	0	127504	1

Signal:

R_DATA_COMB(4)

	From	To	Count	Threshold
Bin	0	1	168537	1
Bin	1	0	170137	1

Signal:

R_DATA_COMB(3)

	From	To	Count	Threshold
Bin	0	1	148401	1
Bin	1	0	150001	1

Signal:

R_DATA_COMB(2)

	From	To	Count	Threshold
Bin	0	1	136179	1
Bin	1	0	137779	1

Signal:

R_DATA_COMB(1)

	From	To	Count	Threshold
Bin	0	1	241901	1
Bin	1	0	243501	1

Signal:

R_DATA_COMB(0)

	From	To	Count	Threshold
Bin	0	1	267758	1
Bin	1	0	269358	1

Signal:

READ_DATA_MASK_N(31)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(30)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(29)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(28)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(27)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(26)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(25)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(24)

	From	To	Count	Threshold
Bin	0	1	27758245	1
Bin	1	0	35788	1

Signal:

READ_DATA_MASK_N(23)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(22)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(21)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(20)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(19)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(18)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(17)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(16)

	From	To	Count	Threshold
Bin	0	1	27758627	1
Bin	1	0	35406	1

Signal:

READ_DATA_MASK_N(15)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(14)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(13)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(12)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(11)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(10)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(9)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(8)

	From	To	Count	Threshold
Bin	0	1	27658880	1
Bin	1	0	135153	1

Signal:

READ_DATA_MASK_N(7)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(6)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(5)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(4)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(3)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(2)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(1)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Signal:

READ_DATA_MASK_N(0)

	From	To	Count	Threshold
Bin	0	1	27660120	1
Bin	1	0	133913	1

Port:

TEST_REGISTERS_OUT_I.TST_CONTROL_TMAENA

	From	To	Count	Threshold
Bin	0	1	648	1
Bin	1	0	2248	1

Port:

TEST_REGISTERS_OUT_I.TST_CONTROL_TWRSTB

	From	To	Count	Threshold
Bin	0	1	32309	1
Bin	1	0	35200	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(15)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	50962	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(14)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	50962	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(13)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	50962	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(12)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	50962	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(11)

	From	To	Count	Threshold
Bin	0	1	2565	1
Bin	1	0	53267	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(10)

	From	To	Count	Threshold
Bin	0	1	5125	1
Bin	1	0	55827	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(9)

	From	To	Count	Threshold
Bin	0	1	10245	1
Bin	1	0	60947	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(8)

	From	To	Count	Threshold
Bin	0	1	20485	1
Bin	1	0	71187	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(7)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	1765	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(6)

	From	To	Count	Threshold
Bin	0	1	355	1
Bin	1	0	1955	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(5)

	From	To	Count	Threshold
Bin	0	1	705	1
Bin	1	0	2305	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(4)

	From	To	Count	Threshold
Bin	0	1	3617	1
Bin	1	0	5217	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(3)

	From	To	Count	Threshold
Bin	0	1	5031	1
Bin	1	0	6631	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(2)

	From	To	Count	Threshold
Bin	0	1	10323	1
Bin	1	0	11923	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(1)

	From	To	Count	Threshold
Bin	0	1	22448	1
Bin	1	0	24048	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_ADDR(0)

	From	To	Count	Threshold
Bin	0	1	44884	1
Bin	1	0	46484	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_MTGT(3)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	1835	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_MTGT(2)

	From	To	Count	Threshold
Bin	0	1	374	1
Bin	1	0	1974	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_MTGT(1)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	2114	1

Port:

TEST_REGISTERS_OUT_I.TST_DEST_TST_MTGT(0)

	From	To	Count	Threshold
Bin	0	1	979	1
Bin	1	0	2579	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(31)

	From	To	Count	Threshold
Bin	0	1	1542	1
Bin	1	0	3194	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(30)

	From	To	Count	Threshold
Bin	0	1	1487	1
Bin	1	0	3194	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(29)

	From	To	Count	Threshold
Bin	0	1	1499	1
Bin	1	0	3167	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(28)

	From	To	Count	Threshold
Bin	0	1	1634	1
Bin	1	0	3363	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(27)

	From	To	Count	Threshold
Bin	0	1	1661	1
Bin	1	0	3363	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(26)

	From	To	Count	Threshold
Bin	0	1	1642	1
Bin	1	0	3365	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(25)

	From	To	Count	Threshold
Bin	0	1	1649	1
Bin	1	0	3362	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(24)

	From	To	Count	Threshold
Bin	0	1	1719	1
Bin	1	0	3453	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(23)

	From	To	Count	Threshold
Bin	0	1	1594	1
Bin	1	0	3312	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(22)

	From	To	Count	Threshold
Bin	0	1	1534	1
Bin	1	0	3244	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(21)

	From	To	Count	Threshold
Bin	0	1	1566	1
Bin	1	0	3273	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(20)

	From	To	Count	Threshold
Bin	0	1	1667	1
Bin	1	0	3374	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(19)

	From	To	Count	Threshold
Bin	0	1	1661	1
Bin	1	0	3352	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(18)

	From	To	Count	Threshold
Bin	0	1	1648	1
Bin	1	0	3339	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(17)

	From	To	Count	Threshold
Bin	0	1	1633	1
Bin	1	0	3321	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(16)

	From	To	Count	Threshold
Bin	0	1	1673	1
Bin	1	0	3367	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(15)

	From	To	Count	Threshold
Bin	0	1	1578	1
Bin	1	0	3249	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(14)

	From	To	Count	Threshold
Bin	0	1	1505	1
Bin	1	0	3169	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(13)

	From	To	Count	Threshold
Bin	0	1	1562	1
Bin	1	0	3248	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(12)

	From	To	Count	Threshold
Bin	0	1	1644	1
Bin	1	0	3328	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(11)

	From	To	Count	Threshold
Bin	0	1	1658	1
Bin	1	0	3324	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(10)

	From	To	Count	Threshold
Bin	0	1	1659	1
Bin	1	0	3336	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(9)

	From	To	Count	Threshold
Bin	0	1	1675	1
Bin	1	0	3367	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(8)

	From	To	Count	Threshold
Bin	0	1	1685	1
Bin	1	0	3369	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(7)

	From	To	Count	Threshold
Bin	0	1	1637	1
Bin	1	0	3293	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(6)

	From	To	Count	Threshold
Bin	0	1	1570	1
Bin	1	0	3233	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(5)

	From	To	Count	Threshold
Bin	0	1	1606	1
Bin	1	0	3273	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(4)

	From	To	Count	Threshold
Bin	0	1	1639	1
Bin	1	0	3296	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(3)

	From	To	Count	Threshold
Bin	0	1	1653	1
Bin	1	0	3300	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(2)

	From	To	Count	Threshold
Bin	0	1	1668	1
Bin	1	0	3319	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(1)

	From	To	Count	Threshold
Bin	0	1	1658	1
Bin	1	0	3332	1

Port:

TEST_REGISTERS_OUT_I.TST_WDATA_TST_WDATA(0)

	From	To	Count	Threshold
Bin	0	1	1725	1
Bin	1	0	3401	1

Signal:

WRITE_EN(3)

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Signal:

WRITE_EN(2)

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Signal:

WRITE_EN(1)

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Signal:

WRITE_EN(0)

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');

	Evaluated to	Count	Threshold
Bin	False	54908186	1
Bin	True	1309092	1

"=" expression

116: write_en <= be when (write = '1' and cs = '1') else (others => '0');

	Evaluated to	Count	Threshold
Bin	False	55591266	1
Bin	True	626012	1

"and" expression

116:    write_en <= be when (write = '1' and cs = '1') else (others => '0'); 
                             <---LHS--->     <-RHS-->

	LHS	RHS	Count	Threshold
Bin	False	True	406765	1
Bin	True	False	1089845	1
Bin	True	True	219247	1

"=" expression

327: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	26539942	1
Bin	True	15860	1

"=" expression

330: if (cs = '1' and read = '1') then

	Evaluated to	Count	Threshold
Bin	False	12950550	1
Bin	True	313006	1

"=" expression

330: if (cs = '1' and read = '1') then

	Evaluated to	Count	Threshold
Bin	False	10624489	1
Bin	True	2639067	1

"and" expression

330:            if (cs = '1' and read = '1') then 
                    <-LHS-->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	2545308	1
Bin	True	False	219247	1
Bin	True	True	93759	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

352:    -- psl tst_control_write_access_cov : cover 
353:    -- {((cs='1') and (write='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 42840
Threshold: 1

PSL cover point:

355:    -- psl tst_control_read_access_cov : cover 
356:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point:

358:    -- psl tst_dest_write_access_cov : cover 
359:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 135068
Threshold: 1

PSL cover point:

361:    -- psl tst_dest_read_access_cov : cover 
362:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point:

364:    -- psl tst_wdata_write_access_cov : cover 
365:    -- {((cs='1') and (write='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 41339
Threshold: 1

PSL cover point:

367:    -- psl tst_wdata_read_access_cov : cover 
368:    -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 10
Threshold: 1

PSL cover point:

370:    -- psl tst_rdata_read_access_cov : cover 
371:    -- {((cs='1') and (read='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 93729
Threshold: 1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/test_registers_reg_map.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Sequential statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

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Covered toggles:

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