NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.FEATURE_TEST_AGENT_GEN.FEATURE_TEST_AGENT_INST.TEST_NODE_INST.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_3_REG_COMP.BIT_GEN(4)

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.FEATURE_TEST_AGENT_GEN.FEATURE_TEST_AGENT_INST.TEST_NODE_INST.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_WDATA_TST_WDATA_SLICE_3_REG_COMP.BIT_GEN(4)	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

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