NVC code coverage report

NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_GEN(0)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(2)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
BYTE_GEN(3)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)
RAM_RST_FALSE_GEN	100.0 % (4/4)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (10/10)
SYNC_READ_GEN	100.0 % (2/2)	100.0 % (2/2)	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST	100.0 % (1/1)	N.A.	100.0 % (1578/1578)	N.A.	N.A.	N.A.	100.0 % (1579/1579)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

191: int_read_data <= ram_memory(to_integer(unsigned(addr_B)));
Count: 32874
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	327611	1
Bin	1	0	327776	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	723	1
Bin	1	0	723	1

Port:

ADDR_A(4)

	From	To	Count	Threshold
Bin	0	1	101815	1
Bin	1	0	4957398	1

Port:

ADDR_A(3)

	From	To	Count	Threshold
Bin	0	1	128238	1
Bin	1	0	4930965	1

Port:

ADDR_A(2)

	From	To	Count	Threshold
Bin	0	1	109939	1
Bin	1	0	4949398	1

Port:

ADDR_A(1)

	From	To	Count	Threshold
Bin	0	1	4816611	1
Bin	1	0	243008	1

Port:

ADDR_A(0)

	From	To	Count	Threshold
Bin	0	1	3626278	1
Bin	1	0	1433940	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	11426	1
Bin	1	0	11613	1

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	16783	1
Bin	1	0	320755	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	18844	1
Bin	1	0	318696	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	16452	1
Bin	1	0	321080	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	25026	1
Bin	1	0	312514	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	19144	1
Bin	1	0	318390	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	21478	1
Bin	1	0	316058	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	26411	1
Bin	1	0	311131	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	21324	1
Bin	1	0	316214	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	20390	1
Bin	1	0	317146	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	23890	1
Bin	1	0	313640	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	22631	1
Bin	1	0	314899	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	20976	1
Bin	1	0	316566	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	34294	1
Bin	1	0	303245	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	43933	1
Bin	1	0	293607	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	41162	1
Bin	1	0	296380	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	83913	1
Bin	1	0	253634	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	18491	1
Bin	1	0	319065	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	21901	1
Bin	1	0	315647	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	19182	1
Bin	1	0	318370	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	22320	1
Bin	1	0	315238	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	40358	1
Bin	1	0	297184	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	41685	1
Bin	1	0	295853	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	49710	1
Bin	1	0	287842	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	50852	1
Bin	1	0	286682	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	44613	1
Bin	1	0	292925	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	42561	1
Bin	1	0	294985	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	44969	1
Bin	1	0	292577	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	49514	1
Bin	1	0	288016	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	52994	1
Bin	1	0	284552	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	55861	1
Bin	1	0	281684	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	96406	1
Bin	1	0	241137	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	83266	1
Bin	1	0	254287	1

Port:

BE(3)

	From	To	Count	Threshold
Bin	0	1	5053365	1
Bin	1	0	7925	1

Port:

BE(2)

	From	To	Count	Threshold
Bin	0	1	5053445	1
Bin	1	0	7845	1

Port:

BE(1)

	From	To	Count	Threshold
Bin	0	1	5039204	1
Bin	1	0	22086	1

Port:

BE(0)

	From	To	Count	Threshold
Bin	0	1	5039488	1
Bin	1	0	21802	1

Port:

ADDR_B(4)

	From	To	Count	Threshold
Bin	0	1	3248	1
Bin	1	0	3413	1

Port:

ADDR_B(3)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	329	1

Port:

ADDR_B(2)

	From	To	Count	Threshold
Bin	0	1	5043	1
Bin	1	0	5208	1

Port:

ADDR_B(1)

	From	To	Count	Threshold
Bin	0	1	3996	1
Bin	1	0	3996	1

Port:

ADDR_B(0)

	From	To	Count	Threshold
Bin	0	1	11127	1
Bin	1	0	11292	1

Port:

DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	339	1
Bin	1	0	494	1

Port:

DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	359	1

Port:

DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	361	1

Port:

DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	621	1
Bin	1	0	771	1

Port:

DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	557	1
Bin	1	0	706	1

Port:

DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	525	1
Bin	1	0	678	1

Port:

DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	544	1
Bin	1	0	694	1

Port:

DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	561	1
Bin	1	0	709	1

Port:

DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	427	1
Bin	1	0	575	1

Port:

DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	604	1
Bin	1	0	755	1

Port:

DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	570	1
Bin	1	0	722	1

Port:

DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	774	1

Port:

DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	661	1
Bin	1	0	810	1

Port:

DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	506	1
Bin	1	0	655	1

Port:

DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	313	1
Bin	1	0	467	1

Port:

DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	329	1
Bin	1	0	484	1

Port:

DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	495	1

Port:

DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	520	1
Bin	1	0	674	1

Port:

DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	389	1
Bin	1	0	542	1

Port:

DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	481	1
Bin	1	0	634	1

Port:

DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	345	1
Bin	1	0	498	1

Port:

DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	442	1
Bin	1	0	594	1

Port:

DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	821	1
Bin	1	0	971	1

Port:

DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	672	1

Port:

DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	922	1
Bin	1	0	1066	1

Port:

DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	600	1
Bin	1	0	746	1

Port:

DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	568	1
Bin	1	0	719	1

Port:

DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	291	1
Bin	1	0	444	1

Port:

DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	435	1
Bin	1	0	585	1

Port:

DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	782	1
Bin	1	0	932	1

Port:

DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	608	1
Bin	1	0	754	1

Port:

DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	452	1
Bin	1	0	598	1

Signal:

RAM_MEMORY(0)(31)

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	3991	1

Signal:

RAM_MEMORY(0)(30)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(29)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3991	1

Signal:

RAM_MEMORY(0)(28)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	4031	1

Signal:

RAM_MEMORY(0)(27)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4010	1

Signal:

RAM_MEMORY(0)(26)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(25)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(24)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	4011	1

Signal:

RAM_MEMORY(0)(23)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3919	1

Signal:

RAM_MEMORY(0)(22)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	4030	1

Signal:

RAM_MEMORY(0)(21)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3939	1

Signal:

RAM_MEMORY(0)(20)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3919	1

Signal:

RAM_MEMORY(0)(19)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3939	1

Signal:

RAM_MEMORY(0)(18)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3939	1

Signal:

RAM_MEMORY(0)(17)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	3939	1

Signal:

RAM_MEMORY(0)(16)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	3938	1

Signal:

RAM_MEMORY(0)(15)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3450	1

Signal:

RAM_MEMORY(0)(14)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	3449	1

Signal:

RAM_MEMORY(0)(13)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3469	1

Signal:

RAM_MEMORY(0)(12)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(0)(11)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(0)(10)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(0)(9)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	3810	1

Signal:

RAM_MEMORY(0)(8)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(0)(7)

	From	To	Count	Threshold
Bin	0	1	312	1
Bin	1	0	3490	1

Signal:

RAM_MEMORY(0)(6)

	From	To	Count	Threshold
Bin	0	1	235	1
Bin	1	0	3508	1

Signal:

RAM_MEMORY(0)(5)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	3406	1

Signal:

RAM_MEMORY(0)(4)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	3299	1

Signal:

RAM_MEMORY(0)(3)

	From	To	Count	Threshold
Bin	0	1	184	1
Bin	1	0	3403	1

Signal:

RAM_MEMORY(0)(2)

	From	To	Count	Threshold
Bin	0	1	253	1
Bin	1	0	3445	1

Signal:

RAM_MEMORY(0)(1)

	From	To	Count	Threshold
Bin	0	1	242	1
Bin	1	0	3410	1

Signal:

RAM_MEMORY(0)(0)

	From	To	Count	Threshold
Bin	0	1	241	1
Bin	1	0	3427	1

Signal:

RAM_MEMORY(1)(31)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3189	1

Signal:

RAM_MEMORY(1)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3208	1

Signal:

RAM_MEMORY(1)(29)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3189	1

Signal:

RAM_MEMORY(1)(28)

	From	To	Count	Threshold
Bin	0	1	226	1
Bin	1	0	3332	1

Signal:

RAM_MEMORY(1)(27)

	From	To	Count	Threshold
Bin	0	1	218	1
Bin	1	0	3330	1

Signal:

RAM_MEMORY(1)(26)

	From	To	Count	Threshold
Bin	0	1	230	1
Bin	1	0	3340	1

Signal:

RAM_MEMORY(1)(25)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	3340	1

Signal:

RAM_MEMORY(1)(24)

	From	To	Count	Threshold
Bin	0	1	191	1
Bin	1	0	3326	1

Signal:

RAM_MEMORY(1)(23)

	From	To	Count	Threshold
Bin	0	1	238	1
Bin	1	0	3359	1

Signal:

RAM_MEMORY(1)(22)

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	3356	1

Signal:

RAM_MEMORY(1)(21)

	From	To	Count	Threshold
Bin	0	1	230	1
Bin	1	0	3356	1

Signal:

RAM_MEMORY(1)(20)

	From	To	Count	Threshold
Bin	0	1	242	1
Bin	1	0	3331	1

Signal:

RAM_MEMORY(1)(19)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	3370	1

Signal:

RAM_MEMORY(1)(18)

	From	To	Count	Threshold
Bin	0	1	256	1
Bin	1	0	3371	1

Signal:

RAM_MEMORY(1)(17)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	3268	1

Signal:

RAM_MEMORY(1)(16)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	3290	1

Signal:

RAM_MEMORY(1)(15)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	3505	1

Signal:

RAM_MEMORY(1)(14)

	From	To	Count	Threshold
Bin	0	1	159	1
Bin	1	0	3579	1

Signal:

RAM_MEMORY(1)(13)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	3579	1

Signal:

RAM_MEMORY(1)(12)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	3513	1

Signal:

RAM_MEMORY(1)(11)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	3534	1

Signal:

RAM_MEMORY(1)(10)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	3504	1

Signal:

RAM_MEMORY(1)(9)

	From	To	Count	Threshold
Bin	0	1	118	1
Bin	1	0	3452	1

Signal:

RAM_MEMORY(1)(8)

	From	To	Count	Threshold
Bin	0	1	150	1
Bin	1	0	3576	1

Signal:

RAM_MEMORY(1)(7)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	3501	1

Signal:

RAM_MEMORY(1)(6)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	3456	1

Signal:

RAM_MEMORY(1)(5)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	3497	1

Signal:

RAM_MEMORY(1)(4)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	3495	1

Signal:

RAM_MEMORY(1)(3)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	3452	1

Signal:

RAM_MEMORY(1)(2)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	3561	1

Signal:

RAM_MEMORY(1)(1)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	3492	1

Signal:

RAM_MEMORY(1)(0)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	3576	1

Signal:

RAM_MEMORY(2)(31)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3686	1

Signal:

RAM_MEMORY(2)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3704	1

Signal:

RAM_MEMORY(2)(29)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3704	1

Signal:

RAM_MEMORY(2)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3704	1

Signal:

RAM_MEMORY(2)(27)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3704	1

Signal:

RAM_MEMORY(2)(26)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3686	1

Signal:

RAM_MEMORY(2)(25)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3704	1

Signal:

RAM_MEMORY(2)(24)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3686	1

Signal:

RAM_MEMORY(2)(23)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3641	1

Signal:

RAM_MEMORY(2)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3641	1

Signal:

RAM_MEMORY(2)(21)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3641	1

Signal:

RAM_MEMORY(2)(20)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	3685	1

Signal:

RAM_MEMORY(2)(19)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3641	1

Signal:

RAM_MEMORY(2)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3641	1

Signal:

RAM_MEMORY(2)(17)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3623	1

Signal:

RAM_MEMORY(2)(16)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3623	1

Signal:

RAM_MEMORY(2)(15)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(13)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3680	1

Signal:

RAM_MEMORY(2)(12)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3682	1

Signal:

RAM_MEMORY(2)(11)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(10)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3700	1

Signal:

RAM_MEMORY(2)(9)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(8)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3700	1

Signal:

RAM_MEMORY(2)(7)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(6)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3700	1

Signal:

RAM_MEMORY(2)(5)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3682	1

Signal:

RAM_MEMORY(2)(4)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3682	1

Signal:

RAM_MEMORY(2)(3)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3680	1

Signal:

RAM_MEMORY(2)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3698	1

Signal:

RAM_MEMORY(2)(1)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3682	1

Signal:

RAM_MEMORY(2)(0)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3680	1

Signal:

RAM_MEMORY(3)(31)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(30)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(29)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(27)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3527	1

Signal:

RAM_MEMORY(3)(26)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(25)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(24)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(23)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(22)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(21)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(20)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(19)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(18)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(17)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(16)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(3)(15)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	3527	1

Signal:

RAM_MEMORY(3)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3469	1

Signal:

RAM_MEMORY(3)(13)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3486	1

Signal:

RAM_MEMORY(3)(12)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(3)(11)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3487	1

Signal:

RAM_MEMORY(3)(10)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(3)(9)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3486	1

Signal:

RAM_MEMORY(3)(8)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3470	1

Signal:

RAM_MEMORY(3)(7)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3527	1

Signal:

RAM_MEMORY(3)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(5)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(4)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	3527	1

Signal:

RAM_MEMORY(3)(3)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3544	1

Signal:

RAM_MEMORY(3)(1)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3545	1

Signal:

RAM_MEMORY(3)(0)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	3528	1

Signal:

RAM_MEMORY(4)(31)

	From	To	Count	Threshold
Bin	0	1	203	1
Bin	1	0	2960	1

Signal:

RAM_MEMORY(4)(30)

	From	To	Count	Threshold
Bin	0	1	194	1
Bin	1	0	3014	1

Signal:

RAM_MEMORY(4)(29)

	From	To	Count	Threshold
Bin	0	1	190	1
Bin	1	0	2982	1

Signal:

RAM_MEMORY(4)(28)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	2969	1

Signal:

RAM_MEMORY(4)(27)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	2976	1

Signal:

RAM_MEMORY(4)(26)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2957	1

Signal:

RAM_MEMORY(4)(25)

	From	To	Count	Threshold
Bin	0	1	245	1
Bin	1	0	3034	1

Signal:

RAM_MEMORY(4)(24)

	From	To	Count	Threshold
Bin	0	1	193	1
Bin	1	0	2982	1

Signal:

RAM_MEMORY(4)(23)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	3001	1

Signal:

RAM_MEMORY(4)(22)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	2969	1

Signal:

RAM_MEMORY(4)(21)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	2939	1

Signal:

RAM_MEMORY(4)(20)

	From	To	Count	Threshold
Bin	0	1	197	1
Bin	1	0	2984	1

Signal:

RAM_MEMORY(4)(19)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	2986	1

Signal:

RAM_MEMORY(4)(18)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	3031	1

Signal:

RAM_MEMORY(4)(17)

	From	To	Count	Threshold
Bin	0	1	191	1
Bin	1	0	2956	1

Signal:

RAM_MEMORY(4)(16)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	2976	1

Signal:

RAM_MEMORY(4)(15)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	2956	1

Signal:

RAM_MEMORY(4)(14)

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	2928	1

Signal:

RAM_MEMORY(4)(13)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	2944	1

Signal:

RAM_MEMORY(4)(12)

	From	To	Count	Threshold
Bin	0	1	246	1
Bin	1	0	2974	1

Signal:

RAM_MEMORY(4)(11)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	2951	1

Signal:

RAM_MEMORY(4)(10)

	From	To	Count	Threshold
Bin	0	1	216	1
Bin	1	0	2992	1

Signal:

RAM_MEMORY(4)(9)

	From	To	Count	Threshold
Bin	0	1	200	1
Bin	1	0	2905	1

Signal:

RAM_MEMORY(4)(8)

	From	To	Count	Threshold
Bin	0	1	189	1
Bin	1	0	2977	1

Signal:

RAM_MEMORY(4)(7)

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	2947	1

Signal:

RAM_MEMORY(4)(6)

	From	To	Count	Threshold
Bin	0	1	182	1
Bin	1	0	2934	1

Signal:

RAM_MEMORY(4)(5)

	From	To	Count	Threshold
Bin	0	1	237	1
Bin	1	0	2888	1

Signal:

RAM_MEMORY(4)(4)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	2966	1

Signal:

RAM_MEMORY(4)(3)

	From	To	Count	Threshold
Bin	0	1	258	1
Bin	1	0	2962	1

Signal:

RAM_MEMORY(4)(2)

	From	To	Count	Threshold
Bin	0	1	217	1
Bin	1	0	2900	1

Signal:

RAM_MEMORY(4)(1)

	From	To	Count	Threshold
Bin	0	1	213	1
Bin	1	0	2866	1

Signal:

RAM_MEMORY(4)(0)

	From	To	Count	Threshold
Bin	0	1	195	1
Bin	1	0	2936	1

Signal:

RAM_MEMORY(5)(31)

	From	To	Count	Threshold
Bin	0	1	170	1
Bin	1	0	2917	1

Signal:

RAM_MEMORY(5)(30)

	From	To	Count	Threshold
Bin	0	1	144	1
Bin	1	0	2958	1

Signal:

RAM_MEMORY(5)(29)

	From	To	Count	Threshold
Bin	0	1	150	1
Bin	1	0	2941	1

Signal:

RAM_MEMORY(5)(28)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2942	1

Signal:

RAM_MEMORY(5)(27)

	From	To	Count	Threshold
Bin	0	1	150	1
Bin	1	0	2962	1

Signal:

RAM_MEMORY(5)(26)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2880	1

Signal:

RAM_MEMORY(5)(25)

	From	To	Count	Threshold
Bin	0	1	167	1
Bin	1	0	2955	1

Signal:

RAM_MEMORY(5)(24)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	2936	1

Signal:

RAM_MEMORY(5)(23)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2859	1

Signal:

RAM_MEMORY(5)(22)

	From	To	Count	Threshold
Bin	0	1	157	1
Bin	1	0	2958	1

Signal:

RAM_MEMORY(5)(21)

	From	To	Count	Threshold
Bin	0	1	172	1
Bin	1	0	2917	1

Signal:

RAM_MEMORY(5)(20)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	2920	1

Signal:

RAM_MEMORY(5)(19)

	From	To	Count	Threshold
Bin	0	1	173	1
Bin	1	0	2935	1

Signal:

RAM_MEMORY(5)(18)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2891	1

Signal:

RAM_MEMORY(5)(17)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	2929	1

Signal:

RAM_MEMORY(5)(16)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	2957	1

Signal:

RAM_MEMORY(5)(15)

	From	To	Count	Threshold
Bin	0	1	177	1
Bin	1	0	2869	1

Signal:

RAM_MEMORY(5)(14)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2843	1

Signal:

RAM_MEMORY(5)(13)

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	2841	1

Signal:

RAM_MEMORY(5)(12)

	From	To	Count	Threshold
Bin	0	1	174	1
Bin	1	0	2883	1

Signal:

RAM_MEMORY(5)(11)

	From	To	Count	Threshold
Bin	0	1	175	1
Bin	1	0	2845	1

Signal:

RAM_MEMORY(5)(10)

	From	To	Count	Threshold
Bin	0	1	154	1
Bin	1	0	2883	1

Signal:

RAM_MEMORY(5)(9)

	From	To	Count	Threshold
Bin	0	1	184	1
Bin	1	0	2839	1

Signal:

RAM_MEMORY(5)(8)

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	2834	1

Signal:

RAM_MEMORY(5)(7)

	From	To	Count	Threshold
Bin	0	1	194	1
Bin	1	0	2848	1

Signal:

RAM_MEMORY(5)(6)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	2874	1

Signal:

RAM_MEMORY(5)(5)

	From	To	Count	Threshold
Bin	0	1	169	1
Bin	1	0	2813	1

Signal:

RAM_MEMORY(5)(4)

	From	To	Count	Threshold
Bin	0	1	161	1
Bin	1	0	2865	1

Signal:

RAM_MEMORY(5)(3)

	From	To	Count	Threshold
Bin	0	1	168	1
Bin	1	0	2821	1

Signal:

RAM_MEMORY(5)(2)

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	2878	1

Signal:

RAM_MEMORY(5)(1)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	2882	1

Signal:

RAM_MEMORY(5)(0)

	From	To	Count	Threshold
Bin	0	1	178	1
Bin	1	0	2855	1

Signal:

RAM_MEMORY(6)(31)

	From	To	Count	Threshold
Bin	0	1	146	1
Bin	1	0	2925	1

Signal:

RAM_MEMORY(6)(30)

	From	To	Count	Threshold
Bin	0	1	148	1
Bin	1	0	2858	1

Signal:

RAM_MEMORY(6)(29)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2850	1

Signal:

RAM_MEMORY(6)(28)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2782	1

Signal:

RAM_MEMORY(6)(27)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2854	1

Signal:

RAM_MEMORY(6)(26)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	2805	1

Signal:

RAM_MEMORY(6)(25)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2892	1

Signal:

RAM_MEMORY(6)(24)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2800	1

Signal:

RAM_MEMORY(6)(23)

	From	To	Count	Threshold
Bin	0	1	142	1
Bin	1	0	2870	1

Signal:

RAM_MEMORY(6)(22)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2913	1

Signal:

RAM_MEMORY(6)(21)

	From	To	Count	Threshold
Bin	0	1	161	1
Bin	1	0	2852	1

Signal:

RAM_MEMORY(6)(20)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	2924	1

Signal:

RAM_MEMORY(6)(19)

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	2920	1

Signal:

RAM_MEMORY(6)(18)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2835	1

Signal:

RAM_MEMORY(6)(17)

	From	To	Count	Threshold
Bin	0	1	122	1
Bin	1	0	2821	1

Signal:

RAM_MEMORY(6)(16)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2866	1

Signal:

RAM_MEMORY(6)(15)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2832	1

Signal:

RAM_MEMORY(6)(14)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2898	1

Signal:

RAM_MEMORY(6)(13)

	From	To	Count	Threshold
Bin	0	1	179	1
Bin	1	0	2943	1

Signal:

RAM_MEMORY(6)(12)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2815	1

Signal:

RAM_MEMORY(6)(11)

	From	To	Count	Threshold
Bin	0	1	157	1
Bin	1	0	2933	1

Signal:

RAM_MEMORY(6)(10)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2801	1

Signal:

RAM_MEMORY(6)(9)

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	2857	1

Signal:

RAM_MEMORY(6)(8)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	2908	1

Signal:

RAM_MEMORY(6)(7)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	2830	1

Signal:

RAM_MEMORY(6)(6)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2860	1

Signal:

RAM_MEMORY(6)(5)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2811	1

Signal:

RAM_MEMORY(6)(4)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2806	1

Signal:

RAM_MEMORY(6)(3)

	From	To	Count	Threshold
Bin	0	1	158	1
Bin	1	0	2950	1

Signal:

RAM_MEMORY(6)(2)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2842	1

Signal:

RAM_MEMORY(6)(1)

	From	To	Count	Threshold
Bin	0	1	126	1
Bin	1	0	2850	1

Signal:

RAM_MEMORY(6)(0)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2892	1

Signal:

RAM_MEMORY(7)(31)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2763	1

Signal:

RAM_MEMORY(7)(30)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2745	1

Signal:

RAM_MEMORY(7)(29)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	2771	1

Signal:

RAM_MEMORY(7)(28)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2796	1

Signal:

RAM_MEMORY(7)(27)

	From	To	Count	Threshold
Bin	0	1	153	1
Bin	1	0	2773	1

Signal:

RAM_MEMORY(7)(26)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2752	1

Signal:

RAM_MEMORY(7)(25)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2732	1

Signal:

RAM_MEMORY(7)(24)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2765	1

Signal:

RAM_MEMORY(7)(23)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2775	1

Signal:

RAM_MEMORY(7)(22)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2768	1

Signal:

RAM_MEMORY(7)(21)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2763	1

Signal:

RAM_MEMORY(7)(20)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	2745	1

Signal:

RAM_MEMORY(7)(19)

	From	To	Count	Threshold
Bin	0	1	145	1
Bin	1	0	2775	1

Signal:

RAM_MEMORY(7)(18)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2768	1

Signal:

RAM_MEMORY(7)(17)

	From	To	Count	Threshold
Bin	0	1	123	1
Bin	1	0	2793	1

Signal:

RAM_MEMORY(7)(16)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2798	1

Signal:

RAM_MEMORY(7)(15)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2757	1

Signal:

RAM_MEMORY(7)(14)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	2799	1

Signal:

RAM_MEMORY(7)(13)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2794	1

Signal:

RAM_MEMORY(7)(12)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2730	1

Signal:

RAM_MEMORY(7)(11)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2791	1

Signal:

RAM_MEMORY(7)(10)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	2753	1

Signal:

RAM_MEMORY(7)(9)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2773	1

Signal:

RAM_MEMORY(7)(8)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(7)(7)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(7)(6)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2740	1

Signal:

RAM_MEMORY(7)(5)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	2742	1

Signal:

RAM_MEMORY(7)(4)

	From	To	Count	Threshold
Bin	0	1	150	1
Bin	1	0	2816	1

Signal:

RAM_MEMORY(7)(3)

	From	To	Count	Threshold
Bin	0	1	117	1
Bin	1	0	2776	1

Signal:

RAM_MEMORY(7)(2)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	2747	1

Signal:

RAM_MEMORY(7)(1)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2758	1

Signal:

RAM_MEMORY(7)(0)

	From	To	Count	Threshold
Bin	0	1	126	1
Bin	1	0	2775	1

Signal:

RAM_MEMORY(8)(31)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2642	1

Signal:

RAM_MEMORY(8)(30)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2660	1

Signal:

RAM_MEMORY(8)(29)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	2680	1

Signal:

RAM_MEMORY(8)(28)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2618	1

Signal:

RAM_MEMORY(8)(27)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2670	1

Signal:

RAM_MEMORY(8)(26)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2650	1

Signal:

RAM_MEMORY(8)(25)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2630	1

Signal:

RAM_MEMORY(8)(24)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2640	1

Signal:

RAM_MEMORY(8)(23)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2658	1

Signal:

RAM_MEMORY(8)(22)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2630	1

Signal:

RAM_MEMORY(8)(21)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2610	1

Signal:

RAM_MEMORY(8)(20)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2628	1

Signal:

RAM_MEMORY(8)(19)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	2630	1

Signal:

RAM_MEMORY(8)(18)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	2660	1

Signal:

RAM_MEMORY(8)(17)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2612	1

Signal:

RAM_MEMORY(8)(16)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	2642	1

Signal:

RAM_MEMORY(8)(15)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2612	1

Signal:

RAM_MEMORY(8)(14)

	From	To	Count	Threshold
Bin	0	1	102	1
Bin	1	0	2638	1

Signal:

RAM_MEMORY(8)(13)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2612	1

Signal:

RAM_MEMORY(8)(12)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2642	1

Signal:

RAM_MEMORY(8)(11)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2658	1

Signal:

RAM_MEMORY(8)(10)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2670	1

Signal:

RAM_MEMORY(8)(9)

	From	To	Count	Threshold
Bin	0	1	143	1
Bin	1	0	2650	1

Signal:

RAM_MEMORY(8)(8)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2630	1

Signal:

RAM_MEMORY(8)(7)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2658	1

Signal:

RAM_MEMORY(8)(6)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2650	1

Signal:

RAM_MEMORY(8)(5)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2602	1

Signal:

RAM_MEMORY(8)(4)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2610	1

Signal:

RAM_MEMORY(8)(3)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2602	1

Signal:

RAM_MEMORY(8)(2)

	From	To	Count	Threshold
Bin	0	1	100	1
Bin	1	0	2658	1

Signal:

RAM_MEMORY(8)(1)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	2652	1

Signal:

RAM_MEMORY(8)(0)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2622	1

Signal:

RAM_MEMORY(9)(31)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(30)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2504	1

Signal:

RAM_MEMORY(9)(29)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2474	1

Signal:

RAM_MEMORY(9)(28)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	2455	1

Signal:

RAM_MEMORY(9)(27)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	2485	1

Signal:

RAM_MEMORY(9)(26)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2502	1

Signal:

RAM_MEMORY(9)(25)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(24)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(23)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	2493	1

Signal:

RAM_MEMORY(9)(22)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2522	1

Signal:

RAM_MEMORY(9)(21)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	2504	1

Signal:

RAM_MEMORY(9)(20)

	From	To	Count	Threshold
Bin	0	1	111	1
Bin	1	0	2523	1

Signal:

RAM_MEMORY(9)(19)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2484	1

Signal:

RAM_MEMORY(9)(18)

	From	To	Count	Threshold
Bin	0	1	98	1
Bin	1	0	2495	1

Signal:

RAM_MEMORY(9)(17)

	From	To	Count	Threshold
Bin	0	1	113	1
Bin	1	0	2523	1

Signal:

RAM_MEMORY(9)(16)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(15)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2465	1

Signal:

RAM_MEMORY(9)(14)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(13)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(12)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(11)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	2523	1

Signal:

RAM_MEMORY(9)(10)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2504	1

Signal:

RAM_MEMORY(9)(9)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2502	1

Signal:

RAM_MEMORY(9)(8)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	2483	1

Signal:

RAM_MEMORY(9)(7)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	2523	1

Signal:

RAM_MEMORY(9)(6)

	From	To	Count	Threshold
Bin	0	1	120	1
Bin	1	0	2513	1

Signal:

RAM_MEMORY(9)(5)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	2505	1

Signal:

RAM_MEMORY(9)(4)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2484	1

Signal:

RAM_MEMORY(9)(3)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2485	1

Signal:

RAM_MEMORY(9)(2)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2512	1

Signal:

RAM_MEMORY(9)(1)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2494	1

Signal:

RAM_MEMORY(9)(0)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	2533	1

Signal:

RAM_MEMORY(10)(31)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(30)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2324	1

Signal:

RAM_MEMORY(10)(29)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2360	1

Signal:

RAM_MEMORY(10)(28)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(27)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(26)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(25)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2324	1

Signal:

RAM_MEMORY(10)(24)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(23)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2306	1

Signal:

RAM_MEMORY(10)(22)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	2296	1

Signal:

RAM_MEMORY(10)(21)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2360	1

Signal:

RAM_MEMORY(10)(20)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(19)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2296	1

Signal:

RAM_MEMORY(10)(18)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2296	1

Signal:

RAM_MEMORY(10)(17)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	2324	1

Signal:

RAM_MEMORY(10)(16)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(15)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2360	1

Signal:

RAM_MEMORY(10)(14)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2388	1

Signal:

RAM_MEMORY(10)(13)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(12)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	2334	1

Signal:

RAM_MEMORY(10)(11)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(10)

	From	To	Count	Threshold
Bin	0	1	99	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(9)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	2360	1

Signal:

RAM_MEMORY(10)(8)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(7)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(6)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	2370	1

Signal:

RAM_MEMORY(10)(5)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	2360	1

Signal:

RAM_MEMORY(10)(4)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	2324	1

Signal:

RAM_MEMORY(10)(3)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	2296	1

Signal:

RAM_MEMORY(10)(2)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(1)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2398	1

Signal:

RAM_MEMORY(10)(0)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2360	1

Signal:

RAM_MEMORY(11)(31)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(30)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	2147	1

Signal:

RAM_MEMORY(11)(29)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(28)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(27)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2174	1

Signal:

RAM_MEMORY(11)(26)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2183	1

Signal:

RAM_MEMORY(11)(25)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2156	1

Signal:

RAM_MEMORY(11)(24)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	2183	1

Signal:

RAM_MEMORY(11)(23)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2174	1

Signal:

RAM_MEMORY(11)(22)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2183	1

Signal:

RAM_MEMORY(11)(21)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2156	1

Signal:

RAM_MEMORY(11)(20)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2247	1

Signal:

RAM_MEMORY(11)(19)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(18)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2247	1

Signal:

RAM_MEMORY(11)(17)

	From	To	Count	Threshold
Bin	0	1	115	1
Bin	1	0	2220	1

Signal:

RAM_MEMORY(11)(16)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	2156	1

Signal:

RAM_MEMORY(11)(15)

	From	To	Count	Threshold
Bin	0	1	95	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(14)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2247	1

Signal:

RAM_MEMORY(11)(13)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2174	1

Signal:

RAM_MEMORY(11)(12)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	2211	1

Signal:

RAM_MEMORY(11)(11)

	From	To	Count	Threshold
Bin	0	1	106	1
Bin	1	0	2220	1

Signal:

RAM_MEMORY(11)(10)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2211	1

Signal:

RAM_MEMORY(11)(9)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	2147	1

Signal:

RAM_MEMORY(11)(8)

	From	To	Count	Threshold
Bin	0	1	97	1
Bin	1	0	2220	1

Signal:

RAM_MEMORY(11)(7)

	From	To	Count	Threshold
Bin	0	1	116	1
Bin	1	0	2247	1

Signal:

RAM_MEMORY(11)(6)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	2174	1

Signal:

RAM_MEMORY(11)(5)

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	2247	1

Signal:

RAM_MEMORY(11)(4)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	2147	1

Signal:

RAM_MEMORY(11)(3)

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(2)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2238	1

Signal:

RAM_MEMORY(11)(1)

	From	To	Count	Threshold
Bin	0	1	92	1
Bin	1	0	2247	1

Signal:

RAM_MEMORY(11)(0)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	2174	1

Signal:

RAM_MEMORY(12)(31)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(30)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(29)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(28)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(27)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(26)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(25)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(24)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(23)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(22)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(21)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(20)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(19)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(18)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(17)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(16)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(15)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(14)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(13)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(12)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(11)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(10)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(9)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(8)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(7)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(6)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(5)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	2108	1

Signal:

RAM_MEMORY(12)(4)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(3)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(1)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(12)(0)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	2116	1

Signal:

RAM_MEMORY(13)(31)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(30)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(29)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(28)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(27)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(26)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(25)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(24)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(23)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(22)

	From	To	Count	Threshold
Bin	0	1	90	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(21)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(20)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(19)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(18)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(17)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(16)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(15)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(14)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(13)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(11)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(10)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(9)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(8)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(7)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(6)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(5)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(4)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(3)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(13)(1)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1958	1

Signal:

RAM_MEMORY(13)(0)

	From	To	Count	Threshold
Bin	0	1	76	1
Bin	1	0	1965	1

Signal:

RAM_MEMORY(14)(31)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(30)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(29)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(28)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(27)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(26)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(25)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(24)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(23)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(22)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(21)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(20)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(19)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(18)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(17)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(16)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(15)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(14)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(13)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(11)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(10)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(9)

	From	To	Count	Threshold
Bin	0	1	93	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(8)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(7)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(6)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(5)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(4)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(3)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1808	1

Signal:

RAM_MEMORY(14)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(1)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(14)(0)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1814	1

Signal:

RAM_MEMORY(15)(31)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(30)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(29)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(27)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(26)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(25)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(24)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(23)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(22)

	From	To	Count	Threshold
Bin	0	1	53	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(21)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(20)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(19)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(17)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(15)

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(13)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(12)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(11)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(10)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(9)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(8)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(7)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(6)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(5)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(4)

	From	To	Count	Threshold
Bin	0	1	84	1
Bin	1	0	1663	1

Signal:

RAM_MEMORY(15)(3)

	From	To	Count	Threshold
Bin	0	1	47	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(1)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(15)(0)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1658	1

Signal:

RAM_MEMORY(16)(31)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(30)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(29)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(28)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(27)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(26)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(25)

	From	To	Count	Threshold
Bin	0	1	81	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(24)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(23)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(22)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(21)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(20)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(19)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(18)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(17)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(16)

	From	To	Count	Threshold
Bin	0	1	77	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(15)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(14)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(13)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(12)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(11)

	From	To	Count	Threshold
Bin	0	1	60	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(9)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(16)(8)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(7)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(6)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(5)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(4)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(3)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(1)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1516	1

Signal:

RAM_MEMORY(16)(0)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1512	1

Signal:

RAM_MEMORY(17)(31)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(30)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(29)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(28)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(27)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(26)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(25)

	From	To	Count	Threshold
Bin	0	1	48	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(24)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(23)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(22)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(21)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(20)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(19)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(18)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(17)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(16)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(15)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(13)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(12)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(11)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(10)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(9)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(7)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(6)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(5)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(4)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(3)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(2)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(17)(1)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1364	1

Signal:

RAM_MEMORY(17)(0)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1361	1

Signal:

RAM_MEMORY(18)(31)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(30)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(29)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(28)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(27)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(26)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(25)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(24)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(23)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(22)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(21)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(19)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(18)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(17)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(16)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(15)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(13)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(12)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(11)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(10)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(9)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(8)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(7)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(6)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(5)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(4)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(3)

	From	To	Count	Threshold
Bin	0	1	54	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(2)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1212	1

Signal:

RAM_MEMORY(18)(1)

	From	To	Count	Threshold
Bin	0	1	52	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(18)(0)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1210	1

Signal:

RAM_MEMORY(19)(31)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(30)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(29)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(28)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(27)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(26)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(25)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(24)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(23)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(22)

	From	To	Count	Threshold
Bin	0	1	70	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(21)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(20)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(19)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(18)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(17)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(16)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(15)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(14)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(13)

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(12)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(11)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(10)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(9)

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(8)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(7)

	From	To	Count	Threshold
Bin	0	1	65	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(6)

	From	To	Count	Threshold
Bin	0	1	71	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(5)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(4)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(3)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(19)(2)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(1)

	From	To	Count	Threshold
Bin	0	1	72	1
Bin	1	0	1060	1

Signal:

RAM_MEMORY(19)(0)

	From	To	Count	Threshold
Bin	0	1	50	1
Bin	1	0	1059	1

Signal:

RAM_MEMORY(20)(31)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(30)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(29)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	936	1

Signal:

RAM_MEMORY(20)(28)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	936	1

Signal:

RAM_MEMORY(20)(27)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(26)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(25)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(24)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(23)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(22)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(21)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(20)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	936	1

Signal:

RAM_MEMORY(20)(19)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	936	1

Signal:

RAM_MEMORY(20)(18)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	936	1

Signal:

RAM_MEMORY(20)(17)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	956	1

Signal:

RAM_MEMORY(20)(16)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	915	1

Signal:

RAM_MEMORY(20)(15)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	772	1

Signal:

RAM_MEMORY(20)(14)

	From	To	Count	Threshold
Bin	0	1	62	1
Bin	1	0	731	1

Signal:

RAM_MEMORY(20)(13)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	731	1

Signal:

RAM_MEMORY(20)(12)

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	732	1

Signal:

RAM_MEMORY(20)(11)

	From	To	Count	Threshold
Bin	0	1	108	1
Bin	1	0	758	1

Signal:

RAM_MEMORY(20)(10)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	779	1

Signal:

RAM_MEMORY(20)(9)

	From	To	Count	Threshold
Bin	0	1	152	1
Bin	1	0	829	1

Signal:

RAM_MEMORY(20)(8)

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	797	1

Signal:

RAM_MEMORY(20)(7)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	771	1

Signal:

RAM_MEMORY(20)(6)

	From	To	Count	Threshold
Bin	0	1	41	1
Bin	1	0	730	1

Signal:

RAM_MEMORY(20)(5)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	751	1

Signal:

RAM_MEMORY(20)(4)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	751	1

Signal:

RAM_MEMORY(20)(3)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	751	1

Signal:

RAM_MEMORY(20)(2)

	From	To	Count	Threshold
Bin	0	1	124	1
Bin	1	0	768	1

Signal:

RAM_MEMORY(20)(1)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	773	1

Signal:

RAM_MEMORY(20)(0)

	From	To	Count	Threshold
Bin	0	1	109	1
Bin	1	0	771	1

Signal:

INT_READ_DATA(31)

	From	To	Count	Threshold
Bin	0	1	343	1
Bin	1	0	498	1

Signal:

INT_READ_DATA(30)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	361	1

Signal:

INT_READ_DATA(29)

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	363	1

Signal:

INT_READ_DATA(28)

	From	To	Count	Threshold
Bin	0	1	875	1
Bin	1	0	1030	1

Signal:

INT_READ_DATA(27)

	From	To	Count	Threshold
Bin	0	1	738	1
Bin	1	0	893	1

Signal:

INT_READ_DATA(26)

	From	To	Count	Threshold
Bin	0	1	661	1
Bin	1	0	816	1

Signal:

INT_READ_DATA(25)

	From	To	Count	Threshold
Bin	0	1	700	1
Bin	1	0	855	1

Signal:

INT_READ_DATA(24)

	From	To	Count	Threshold
Bin	0	1	749	1
Bin	1	0	904	1

Signal:

INT_READ_DATA(23)

	From	To	Count	Threshold
Bin	0	1	613	1
Bin	1	0	768	1

Signal:

INT_READ_DATA(22)

	From	To	Count	Threshold
Bin	0	1	846	1
Bin	1	0	1001	1

Signal:

INT_READ_DATA(21)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	926	1

Signal:

INT_READ_DATA(20)

	From	To	Count	Threshold
Bin	0	1	1022	1
Bin	1	0	1177	1

Signal:

INT_READ_DATA(19)

	From	To	Count	Threshold
Bin	0	1	923	1
Bin	1	0	1078	1

Signal:

INT_READ_DATA(18)

	From	To	Count	Threshold
Bin	0	1	744	1
Bin	1	0	899	1

Signal:

INT_READ_DATA(17)

	From	To	Count	Threshold
Bin	0	1	391	1
Bin	1	0	546	1

Signal:

INT_READ_DATA(16)

	From	To	Count	Threshold
Bin	0	1	420	1
Bin	1	0	575	1

Signal:

INT_READ_DATA(15)

	From	To	Count	Threshold
Bin	0	1	431	1
Bin	1	0	586	1

Signal:

INT_READ_DATA(14)

	From	To	Count	Threshold
Bin	0	1	644	1
Bin	1	0	799	1

Signal:

INT_READ_DATA(13)

	From	To	Count	Threshold
Bin	0	1	515	1
Bin	1	0	670	1

Signal:

INT_READ_DATA(12)

	From	To	Count	Threshold
Bin	0	1	563	1
Bin	1	0	718	1

Signal:

INT_READ_DATA(11)

	From	To	Count	Threshold
Bin	0	1	432	1
Bin	1	0	587	1

Signal:

INT_READ_DATA(10)

	From	To	Count	Threshold
Bin	0	1	534	1
Bin	1	0	689	1

Signal:

INT_READ_DATA(9)

	From	To	Count	Threshold
Bin	0	1	944	1
Bin	1	0	1099	1

Signal:

INT_READ_DATA(8)

	From	To	Count	Threshold
Bin	0	1	638	1
Bin	1	0	793	1

Signal:

INT_READ_DATA(7)

	From	To	Count	Threshold
Bin	0	1	1059	1
Bin	1	0	1214	1

Signal:

INT_READ_DATA(6)

	From	To	Count	Threshold
Bin	0	1	664	1
Bin	1	0	819	1

Signal:

INT_READ_DATA(5)

	From	To	Count	Threshold
Bin	0	1	664	1
Bin	1	0	819	1

Signal:

INT_READ_DATA(4)

	From	To	Count	Threshold
Bin	0	1	364	1
Bin	1	0	519	1

Signal:

INT_READ_DATA(3)

	From	To	Count	Threshold
Bin	0	1	530	1
Bin	1	0	685	1

Signal:

INT_READ_DATA(2)

	From	To	Count	Threshold
Bin	0	1	1026	1
Bin	1	0	1181	1

Signal:

INT_READ_DATA(1)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	926	1

Signal:

INT_READ_DATA(0)

	From	To	Count	Threshold
Bin	0	1	593	1
Bin	1	0	748	1

Signal:

BYTE_WE(3)

	From	To	Count	Threshold
Bin	0	1	11426	1
Bin	1	0	11591	1

Signal:

BYTE_WE(2)

	From	To	Count	Threshold
Bin	0	1	11426	1
Bin	1	0	11591	1

Signal:

BYTE_WE(1)

	From	To	Count	Threshold
Bin	0	1	11426	1
Bin	1	0	11591	1

Signal:

BYTE_WE(0)

	From	To	Count	Threshold
Bin	0	1	11426	1
Bin	1	0	11591	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: