NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	90.0 % (27/30)	N.A.	N.A.	99.8 % (1638/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (13/13)	N.A.	N.A.	100.0 % (105/105)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (516/516)	93.3 % (14/15)	N.A.	N.A.	99.8 % (561/562)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208: txtb_port_b_data_out <= txtb_port_b_data_out_i;
Count: 4582
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 1602
Threshold: 1

Signal assignment statement on line 277:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 89
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 1513
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 10156552
Threshold: 1

Signal assignment statement on line 283:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 10141380
Threshold: 1

Signal assignment statement on line 285:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 15172
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 96252
Threshold: 1

Signal assignment statement on line 287:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 95211
Threshold: 1

Signal assignment statement on line 289:

289: mr_tst_control_twrstb;
Count: 1041
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 705570
Threshold: 1

Signal assignment statement on line 291:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 696338
Threshold: 1

Signal assignment statement on line 293:

293: mr_tst_wdata_tst_wdata;
Count: 9232
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 85936
Threshold: 1

Signal assignment statement on line 296:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 84656
Threshold: 1

Signal assignment statement on line 298:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 1280
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 4925
Threshold: 1

Signal assignment statement on line 300:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 586
Threshold: 1

Signal assignment statement on line 302:

302: (others => '0');
Count: 4339
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	89	1
Bin	False	1513	1

	Evaluated to	Count	Threshold
Bin	True	10141380	1
Bin	False	15172	1

	Evaluated to	Count	Threshold
Bin	True	95211	1
Bin	False	1041	1

	Evaluated to	Count	Threshold
Bin	True	696338	1
Bin	False	9232	1

	Evaluated to	Count	Threshold
Bin	True	84656	1
Bin	False	1280	1

	Evaluated to	Count	Threshold
Bin	True	586	1
Bin	False	4339	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	122	1
Bin	(31)	1	0	287	1
Bin	(30)	0	1	124	1
Bin	(30)	1	0	289	1
Bin	(29)	0	1	119	1
Bin	(29)	1	0	284	1
Bin	(28)	0	1	131	1
Bin	(28)	1	0	296	1
Bin	(27)	0	1	131	1
Bin	(27)	1	0	296	1
Bin	(26)	0	1	134	1
Bin	(26)	1	0	299	1
Bin	(25)	0	1	137	1
Bin	(25)	1	0	302	1
Bin	(24)	0	1	134	1
Bin	(24)	1	0	299	1
Bin	(23)	0	1	143	1
Bin	(23)	1	0	308	1
Bin	(22)	0	1	130	1
Bin	(22)	1	0	295	1
Bin	(21)	0	1	135	1
Bin	(21)	1	0	300	1
Bin	(20)	0	1	143	1
Bin	(20)	1	0	308	1
Bin	(19)	0	1	131	1
Bin	(19)	1	0	296	1
Bin	(18)	0	1	138	1
Bin	(18)	1	0	303	1
Bin	(17)	0	1	134	1
Bin	(17)	1	0	299	1
Bin	(16)	0	1	115	1
Bin	(16)	1	0	280	1
Bin	(15)	0	1	135	1
Bin	(15)	1	0	300	1
Bin	(14)	0	1	113	1
Bin	(14)	1	0	278	1
Bin	(13)	0	1	125	1
Bin	(13)	1	0	290	1
Bin	(12)	0	1	122	1
Bin	(12)	1	0	287	1
Bin	(11)	0	1	126	1
Bin	(11)	1	0	291	1
Bin	(10)	0	1	125	1
Bin	(10)	1	0	290	1
Bin	(9)	0	1	129	1
Bin	(9)	1	0	294	1
Bin	(8)	0	1	131	1
Bin	(8)	1	0	296	1
Bin	(7)	0	1	135	1
Bin	(7)	1	0	300	1
Bin	(6)	0	1	132	1
Bin	(6)	1	0	297	1
Bin	(5)	0	1	129	1
Bin	(5)	1	0	294	1
Bin	(4)	0	1	123	1
Bin	(4)	1	0	288	1
Bin	(3)	0	1	127	1
Bin	(3)	1	0	292	1
Bin	(2)	0	1	123	1
Bin	(2)	1	0	288	1
Bin	(1)	0	1	134	1
Bin	(1)	1	0	299	1
Bin	(0)	0	1	120	1
Bin	(0)	1	0	285	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	266	1
Bin	(31)	1	0	421	1
Bin	(30)	0	1	234	1
Bin	(30)	1	0	389	1
Bin	(29)	0	1	289	1
Bin	(29)	1	0	444	1
Bin	(28)	0	1	774	1
Bin	(28)	1	0	924	1
Bin	(27)	0	1	622	1
Bin	(27)	1	0	773	1
Bin	(26)	0	1	698	1
Bin	(26)	1	0	849	1
Bin	(25)	0	1	529	1
Bin	(25)	1	0	680	1
Bin	(24)	0	1	829	1
Bin	(24)	1	0	978	1
Bin	(23)	0	1	567	1
Bin	(23)	1	0	718	1
Bin	(22)	0	1	679	1
Bin	(22)	1	0	831	1
Bin	(21)	0	1	769	1
Bin	(21)	1	0	919	1
Bin	(20)	0	1	787	1
Bin	(20)	1	0	940	1
Bin	(19)	0	1	861	1
Bin	(19)	1	0	1010	1
Bin	(18)	0	1	600	1
Bin	(18)	1	0	752	1
Bin	(17)	0	1	556	1
Bin	(17)	1	0	708	1
Bin	(16)	0	1	486	1
Bin	(16)	1	0	640	1
Bin	(15)	0	1	618	1
Bin	(15)	1	0	769	1
Bin	(14)	0	1	493	1
Bin	(14)	1	0	645	1
Bin	(13)	0	1	490	1
Bin	(13)	1	0	641	1
Bin	(12)	0	1	502	1
Bin	(12)	1	0	653	1
Bin	(11)	0	1	493	1
Bin	(11)	1	0	647	1
Bin	(10)	0	1	635	1
Bin	(10)	1	0	787	1
Bin	(9)	0	1	759	1
Bin	(9)	1	0	907	1
Bin	(8)	0	1	419	1
Bin	(8)	1	0	572	1
Bin	(7)	0	1	907	1
Bin	(7)	1	0	1048	1
Bin	(6)	0	1	821	1
Bin	(6)	1	0	966	1
Bin	(5)	0	1	601	1
Bin	(5)	1	0	752	1
Bin	(4)	0	1	603	1
Bin	(4)	1	0	754	1
Bin	(3)	0	1	742	1
Bin	(3)	1	0	886	1
Bin	(2)	0	1	1063	1
Bin	(2)	1	0	1209	1
Bin	(1)	0	1	922	1
Bin	(1)	1	0	1071	1
Bin	(0)	0	1	708	1
Bin	(0)	1	0	852	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	446	1
Bin	1	0	611	1

Signal:

TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101691	1
Bin	(4)	1	0	4940854	1
Bin	(3)	0	1	136075	1
Bin	(3)	1	0	4906460	1
Bin	(2)	0	1	116601	1
Bin	(2)	1	0	4926078	1
Bin	(1)	0	1	4798117	1
Bin	(1)	1	0	244858	1
Bin	(0)	0	1	3686814	1
Bin	(0)	1	0	1356763	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11526	1
Bin	1	0	11728	1

Signal:

TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	23097	1
Bin	(31)	1	0	322632	1
Bin	(30)	0	1	23814	1
Bin	(30)	1	0	321909	1
Bin	(29)	0	1	23512	1
Bin	(29)	1	0	322223	1
Bin	(28)	0	1	30234	1
Bin	(28)	1	0	315509	1
Bin	(27)	0	1	28526	1
Bin	(27)	1	0	317215	1
Bin	(26)	0	1	30058	1
Bin	(26)	1	0	315681	1
Bin	(25)	0	1	29564	1
Bin	(25)	1	0	316173	1
Bin	(24)	0	1	27488	1
Bin	(24)	1	0	318239	1
Bin	(23)	0	1	26732	1
Bin	(23)	1	0	319021	1
Bin	(22)	0	1	27175	1
Bin	(22)	1	0	318560	1
Bin	(21)	0	1	24794	1
Bin	(21)	1	0	320943	1
Bin	(20)	0	1	26976	1
Bin	(20)	1	0	318771	1
Bin	(19)	0	1	39053	1
Bin	(19)	1	0	306701	1
Bin	(18)	0	1	44893	1
Bin	(18)	1	0	300848	1
Bin	(17)	0	1	44343	1
Bin	(17)	1	0	301389	1
Bin	(16)	0	1	87811	1
Bin	(16)	1	0	257920	1
Bin	(15)	0	1	24214	1
Bin	(15)	1	0	321523	1
Bin	(14)	0	1	28117	1
Bin	(14)	1	0	317600	1
Bin	(13)	0	1	25091	1
Bin	(13)	1	0	320646	1
Bin	(12)	0	1	26097	1
Bin	(12)	1	0	319640	1
Bin	(11)	0	1	45972	1
Bin	(11)	1	0	299763	1
Bin	(10)	0	1	48232	1
Bin	(10)	1	0	297499	1
Bin	(9)	0	1	55864	1
Bin	(9)	1	0	289879	1
Bin	(8)	0	1	55355	1
Bin	(8)	1	0	290384	1
Bin	(7)	0	1	50517	1
Bin	(7)	1	0	295220	1
Bin	(6)	0	1	48417	1
Bin	(6)	1	0	297328	1
Bin	(5)	0	1	50349	1
Bin	(5)	1	0	295388	1
Bin	(4)	0	1	54679	1
Bin	(4)	1	0	291054	1
Bin	(3)	0	1	61047	1
Bin	(3)	1	0	284698	1
Bin	(2)	0	1	63074	1
Bin	(2)	1	0	282650	1
Bin	(1)	0	1	99115	1
Bin	(1)	1	0	246638	1
Bin	(0)	0	1	86858	1
Bin	(0)	1	0	258914	1

Signal:

TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3341	1
Bin	(4)	1	0	3506	1
Bin	(3)	0	1	179	1
Bin	(3)	1	0	344	1
Bin	(2)	0	1	5257	1
Bin	(2)	1	0	5422	1
Bin	(1)	0	1	4042	1
Bin	(1)	1	0	4042	1
Bin	(0)	0	1	11356	1
Bin	(0)	1	0	11521	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	266	1
Bin	(31)	1	0	421	1
Bin	(30)	0	1	234	1
Bin	(30)	1	0	389	1
Bin	(29)	0	1	289	1
Bin	(29)	1	0	444	1
Bin	(28)	0	1	774	1
Bin	(28)	1	0	924	1
Bin	(27)	0	1	622	1
Bin	(27)	1	0	773	1
Bin	(26)	0	1	698	1
Bin	(26)	1	0	849	1
Bin	(25)	0	1	529	1
Bin	(25)	1	0	680	1
Bin	(24)	0	1	829	1
Bin	(24)	1	0	978	1
Bin	(23)	0	1	567	1
Bin	(23)	1	0	718	1
Bin	(22)	0	1	679	1
Bin	(22)	1	0	831	1
Bin	(21)	0	1	769	1
Bin	(21)	1	0	919	1
Bin	(20)	0	1	787	1
Bin	(20)	1	0	940	1
Bin	(19)	0	1	861	1
Bin	(19)	1	0	1010	1
Bin	(18)	0	1	600	1
Bin	(18)	1	0	752	1
Bin	(17)	0	1	556	1
Bin	(17)	1	0	708	1
Bin	(16)	0	1	486	1
Bin	(16)	1	0	640	1
Bin	(15)	0	1	618	1
Bin	(15)	1	0	769	1
Bin	(14)	0	1	493	1
Bin	(14)	1	0	645	1
Bin	(13)	0	1	490	1
Bin	(13)	1	0	641	1
Bin	(12)	0	1	502	1
Bin	(12)	1	0	653	1
Bin	(11)	0	1	493	1
Bin	(11)	1	0	647	1
Bin	(10)	0	1	635	1
Bin	(10)	1	0	787	1
Bin	(9)	0	1	759	1
Bin	(9)	1	0	907	1
Bin	(8)	0	1	419	1
Bin	(8)	1	0	572	1
Bin	(7)	0	1	907	1
Bin	(7)	1	0	1048	1
Bin	(6)	0	1	821	1
Bin	(6)	1	0	966	1
Bin	(5)	0	1	601	1
Bin	(5)	1	0	752	1
Bin	(4)	0	1	603	1
Bin	(4)	1	0	754	1
Bin	(3)	0	1	742	1
Bin	(3)	1	0	886	1
Bin	(2)	0	1	1063	1
Bin	(2)	1	0	1209	1
Bin	(1)	0	1	922	1
Bin	(1)	1	0	1071	1
Bin	(0)	0	1	708	1
Bin	(0)	1	0	852	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	89	1
Bin	1	0	254	1

Signal:

PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	25	1
Bin	(20)	1	0	694	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	718	1
Bin	(18)	0	1	2	1
Bin	(18)	1	0	717	1
Bin	(17)	0	1	9	1
Bin	(17)	1	0	710	1
Bin	(16)	0	1	11	1
Bin	(16)	1	0	708	1
Bin	(15)	0	1	13	1
Bin	(15)	1	0	706	1
Bin	(14)	0	1	16	1
Bin	(14)	1	0	703	1
Bin	(13)	0	1	9	1
Bin	(13)	1	0	710	1
Bin	(12)	0	1	11	1
Bin	(12)	1	0	708	1
Bin	(11)	0	1	37	1
Bin	(11)	1	0	682	1
Bin	(10)	0	1	40	1
Bin	(10)	1	0	679	1
Bin	(9)	0	1	26	1
Bin	(9)	1	0	693	1
Bin	(8)	0	1	32	1
Bin	(8)	1	0	687	1
Bin	(7)	0	1	36	1
Bin	(7)	1	0	683	1
Bin	(6)	0	1	71	1
Bin	(6)	1	0	648	1
Bin	(5)	0	1	113	1
Bin	(5)	1	0	606	1
Bin	(4)	0	1	144	1
Bin	(4)	1	0	575	1
Bin	(3)	0	1	324	1
Bin	(3)	1	0	395	1
Bin	(2)	0	1	401	1
Bin	(2)	1	0	318	1
Bin	(1)	0	1	244	1
Bin	(1)	1	0	475	1
Bin	(0)	0	1	218	1
Bin	(0)	1	0	501	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1213	1
Bin	1	0	1069	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	1011	1
Bin	1	0	1176	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

If statement on lines 277 to 280:

Signal assignment statement on line 277:

Signal assignment statement on line 280:

If statement on lines 283 to 285:

Signal assignment statement on line 283:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 287:

Signal assignment statement on line 289:

If statement on lines 291 to 293:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 296 to 298:

Signal assignment statement on line 296:

Signal assignment statement on line 298:

If statement on lines 300 to 302:

Signal assignment statement on line 300:

Signal assignment statement on line 302:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

"if" / "when" / "else" condition on line 283:

"if" / "when" / "else" condition on line 287:

"if" / "when" / "else" condition on line 291:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 300:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

"and" expression on lines 277 to 278:

Excluded expressions:

Covered expressions:

"and" expression on lines 277 to 278:

"=" expression on line 277:

"=" expression on line 283:

"=" expression on line 287:

"=" expression on line 291:

"=" expression on line 296:

"=" expression on line 300:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: