NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	100.0 % (30/30)	N.A.	N.A.	100.0 % (1641/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (17/17)	N.A.	N.A.	100.0 % (109/109)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST	100.0 % (18/18)	100.0 % (12/12)	100.0 % (516/516)	100.0 % (15/15)	N.A.	N.A.	100.0 % (561/561)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 1602
Threshold: 1

Signal assignment statement:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 87
Threshold: 1

Signal assignment statement:

280: '0';
Count: 1515
Threshold: 1

If statement:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 10180700
Threshold: 1

Signal assignment statement:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 10165550
Threshold: 1

Signal assignment statement:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 15150
Threshold: 1

If statement:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 96296
Threshold: 1

Signal assignment statement:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 95263
Threshold: 1

Signal assignment statement:

289: mr_tst_control_twrstb;
Count: 1033
Threshold: 1

If statement:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 683317
Threshold: 1

Signal assignment statement:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 674105
Threshold: 1

Signal assignment statement:

293: mr_tst_wdata_tst_wdata;
Count: 9212
Threshold: 1

If statement:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 85200
Threshold: 1

Signal assignment statement:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 83922
Threshold: 1

Signal assignment statement:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 1278
Threshold: 1

If statement:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 4732
Threshold: 1

Signal assignment statement:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 586
Threshold: 1

Signal assignment statement:

302: (others => '0');
Count: 4146
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	Evaluated to	Count	Threshold
Bin	True	87	1
Bin	False	1515	1

"if" / "when" / "else" condition:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	10165550	1
Bin	False	15150	1

"if" / "when" / "else" condition:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	95263	1
Bin	False	1033	1

"if" / "when" / "else" condition:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	674105	1
Bin	False	9212	1

"if" / "when" / "else" condition:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	83922	1
Bin	False	1278	1

"if" / "when" / "else" condition:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')

	Evaluated to	Count	Threshold
Bin	True	586	1
Bin	False	4146	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	327716	1
Bin	1	0	327881	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	723	1
Bin	1	0	723	1

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold
Bin	0	1	35	1
Bin	1	0	200	1

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold
Bin	0	1	240	1
Bin	1	0	405	1

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold
Bin	0	1	24019	1
Bin	1	0	24663	1

Port:

MR_TST_DEST_TST_ADDR(4)

	From	To	Count	Threshold
Bin	0	1	2083	1
Bin	1	0	2248	1

Port:

MR_TST_DEST_TST_ADDR(3)

	From	To	Count	Threshold
Bin	0	1	3365	1
Bin	1	0	3530	1

Port:

MR_TST_DEST_TST_ADDR(2)

	From	To	Count	Threshold
Bin	0	1	6817	1
Bin	1	0	6982	1

Port:

MR_TST_DEST_TST_ADDR(1)

	From	To	Count	Threshold
Bin	0	1	14296	1
Bin	1	0	14461	1

Port:

MR_TST_DEST_TST_ADDR(0)

	From	To	Count	Threshold
Bin	0	1	28591	1
Bin	1	0	28756	1

Port:

MR_TST_DEST_TST_MTGT(3)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Port:

MR_TST_DEST_TST_MTGT(2)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	298	1

Port:

MR_TST_DEST_TST_MTGT(1)

	From	To	Count	Threshold
Bin	0	1	184	1
Bin	1	0	349	1

Port:

MR_TST_DEST_TST_MTGT(0)

	From	To	Count	Threshold
Bin	0	1	350	1
Bin	1	0	515	1

Port:

MR_TST_WDATA_TST_WDATA(31)

	From	To	Count	Threshold
Bin	0	1	1168	1
Bin	1	0	1333	1

Port:

MR_TST_WDATA_TST_WDATA(30)

	From	To	Count	Threshold
Bin	0	1	1113	1
Bin	1	0	1278	1

Port:

MR_TST_WDATA_TST_WDATA(29)

	From	To	Count	Threshold
Bin	0	1	1143	1
Bin	1	0	1308	1

Port:

MR_TST_WDATA_TST_WDATA(28)

	From	To	Count	Threshold
Bin	0	1	1221	1
Bin	1	0	1386	1

Port:

MR_TST_WDATA_TST_WDATA(27)

	From	To	Count	Threshold
Bin	0	1	1247	1
Bin	1	0	1412	1

Port:

MR_TST_WDATA_TST_WDATA(26)

	From	To	Count	Threshold
Bin	0	1	1230	1
Bin	1	0	1395	1

Port:

MR_TST_WDATA_TST_WDATA(25)

	From	To	Count	Threshold
Bin	0	1	1246	1
Bin	1	0	1411	1

Port:

MR_TST_WDATA_TST_WDATA(24)

	From	To	Count	Threshold
Bin	0	1	1287	1
Bin	1	0	1452	1

Port:

MR_TST_WDATA_TST_WDATA(23)

	From	To	Count	Threshold
Bin	0	1	1175	1
Bin	1	0	1340	1

Port:

MR_TST_WDATA_TST_WDATA(22)

	From	To	Count	Threshold
Bin	0	1	1117	1
Bin	1	0	1282	1

Port:

MR_TST_WDATA_TST_WDATA(21)

	From	To	Count	Threshold
Bin	0	1	1148	1
Bin	1	0	1313	1

Port:

MR_TST_WDATA_TST_WDATA(20)

	From	To	Count	Threshold
Bin	0	1	1239	1
Bin	1	0	1404	1

Port:

MR_TST_WDATA_TST_WDATA(19)

	From	To	Count	Threshold
Bin	0	1	1248	1
Bin	1	0	1413	1

Port:

MR_TST_WDATA_TST_WDATA(18)

	From	To	Count	Threshold
Bin	0	1	1231	1
Bin	1	0	1396	1

Port:

MR_TST_WDATA_TST_WDATA(17)

	From	To	Count	Threshold
Bin	0	1	1250	1
Bin	1	0	1415	1

Port:

MR_TST_WDATA_TST_WDATA(16)

	From	To	Count	Threshold
Bin	0	1	1284	1
Bin	1	0	1449	1

Port:

MR_TST_WDATA_TST_WDATA(15)

	From	To	Count	Threshold
Bin	0	1	1176	1
Bin	1	0	1341	1

Port:

MR_TST_WDATA_TST_WDATA(14)

	From	To	Count	Threshold
Bin	0	1	1126	1
Bin	1	0	1291	1

Port:

MR_TST_WDATA_TST_WDATA(13)

	From	To	Count	Threshold
Bin	0	1	1163	1
Bin	1	0	1328	1

Port:

MR_TST_WDATA_TST_WDATA(12)

	From	To	Count	Threshold
Bin	0	1	1236	1
Bin	1	0	1401	1

Port:

MR_TST_WDATA_TST_WDATA(11)

	From	To	Count	Threshold
Bin	0	1	1236	1
Bin	1	0	1401	1

Port:

MR_TST_WDATA_TST_WDATA(10)

	From	To	Count	Threshold
Bin	0	1	1235	1
Bin	1	0	1400	1

Port:

MR_TST_WDATA_TST_WDATA(9)

	From	To	Count	Threshold
Bin	0	1	1254	1
Bin	1	0	1419	1

Port:

MR_TST_WDATA_TST_WDATA(8)

	From	To	Count	Threshold
Bin	0	1	1290	1
Bin	1	0	1455	1

Port:

MR_TST_WDATA_TST_WDATA(7)

	From	To	Count	Threshold
Bin	0	1	1188	1
Bin	1	0	1353	1

Port:

MR_TST_WDATA_TST_WDATA(6)

	From	To	Count	Threshold
Bin	0	1	1144	1
Bin	1	0	1309	1

Port:

MR_TST_WDATA_TST_WDATA(5)

	From	To	Count	Threshold
Bin	0	1	1178	1
Bin	1	0	1343	1

Port:

MR_TST_WDATA_TST_WDATA(4)

	From	To	Count	Threshold
Bin	0	1	1229	1
Bin	1	0	1394	1

Port:

MR_TST_WDATA_TST_WDATA(3)

	From	To	Count	Threshold
Bin	0	1	1251	1
Bin	1	0	1416	1

Port:

MR_TST_WDATA_TST_WDATA(2)

	From	To	Count	Threshold
Bin	0	1	1239	1
Bin	1	0	1404	1

Port:

MR_TST_WDATA_TST_WDATA(1)

	From	To	Count	Threshold
Bin	0	1	1252	1
Bin	1	0	1417	1

Port:

MR_TST_WDATA_TST_WDATA(0)

	From	To	Count	Threshold
Bin	0	1	1297	1
Bin	1	0	1462	1

Port:

MR_TST_RDATA_TST_RDATA(31)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	298	1

Port:

MR_TST_RDATA_TST_RDATA(30)

	From	To	Count	Threshold
Bin	0	1	125	1
Bin	1	0	290	1

Port:

MR_TST_RDATA_TST_RDATA(29)

	From	To	Count	Threshold
Bin	0	1	112	1
Bin	1	0	277	1

Port:

MR_TST_RDATA_TST_RDATA(28)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	305	1

Port:

MR_TST_RDATA_TST_RDATA(27)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	303	1

Port:

MR_TST_RDATA_TST_RDATA(26)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	304	1

Port:

MR_TST_RDATA_TST_RDATA(25)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	303	1

Port:

MR_TST_RDATA_TST_RDATA(24)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	293	1

Port:

MR_TST_RDATA_TST_RDATA(23)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	306	1

Port:

MR_TST_RDATA_TST_RDATA(22)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	292	1

Port:

MR_TST_RDATA_TST_RDATA(21)

	From	To	Count	Threshold
Bin	0	1	141	1
Bin	1	0	306	1

Port:

MR_TST_RDATA_TST_RDATA(20)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	303	1

Port:

MR_TST_RDATA_TST_RDATA(19)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	300	1

Port:

MR_TST_RDATA_TST_RDATA(18)

	From	To	Count	Threshold
Bin	0	1	128	1
Bin	1	0	293	1

Port:

MR_TST_RDATA_TST_RDATA(17)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	294	1

Port:

MR_TST_RDATA_TST_RDATA(16)

	From	To	Count	Threshold
Bin	0	1	121	1
Bin	1	0	286	1

Port:

MR_TST_RDATA_TST_RDATA(15)

	From	To	Count	Threshold
Bin	0	1	139	1
Bin	1	0	304	1

Port:

MR_TST_RDATA_TST_RDATA(14)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	297	1

Port:

MR_TST_RDATA_TST_RDATA(13)

	From	To	Count	Threshold
Bin	0	1	131	1
Bin	1	0	296	1

Port:

MR_TST_RDATA_TST_RDATA(12)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	300	1

Port:

MR_TST_RDATA_TST_RDATA(11)

	From	To	Count	Threshold
Bin	0	1	133	1
Bin	1	0	298	1

Port:

MR_TST_RDATA_TST_RDATA(10)

	From	To	Count	Threshold
Bin	0	1	135	1
Bin	1	0	300	1

Port:

MR_TST_RDATA_TST_RDATA(9)

	From	To	Count	Threshold
Bin	0	1	148	1
Bin	1	0	313	1

Port:

MR_TST_RDATA_TST_RDATA(8)

	From	To	Count	Threshold
Bin	0	1	137	1
Bin	1	0	302	1

Port:

MR_TST_RDATA_TST_RDATA(7)

	From	To	Count	Threshold
Bin	0	1	142	1
Bin	1	0	307	1

Port:

MR_TST_RDATA_TST_RDATA(6)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	294	1

Port:

MR_TST_RDATA_TST_RDATA(5)

	From	To	Count	Threshold
Bin	0	1	130	1
Bin	1	0	295	1

Port:

MR_TST_RDATA_TST_RDATA(4)

	From	To	Count	Threshold
Bin	0	1	134	1
Bin	1	0	299	1

Port:

MR_TST_RDATA_TST_RDATA(3)

	From	To	Count	Threshold
Bin	0	1	132	1
Bin	1	0	297	1

Port:

MR_TST_RDATA_TST_RDATA(2)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	301	1

Port:

MR_TST_RDATA_TST_RDATA(1)

	From	To	Count	Threshold
Bin	0	1	142	1
Bin	1	0	307	1

Port:

MR_TST_RDATA_TST_RDATA(0)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	294	1

Port:

TXTB_PORT_A_ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	101760	1
Bin	1	0	4959695	1

Port:

TXTB_PORT_A_ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	128188	1
Bin	1	0	4933267	1

Port:

TXTB_PORT_A_ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	109822	1
Bin	1	0	4951633	1

Port:

TXTB_PORT_A_ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	4817393	1
Bin	1	0	244062	1

Port:

TXTB_PORT_A_ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	3627605	1
Bin	1	0	1433850	1

Port:

TXTB_PORT_A_DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	16808	1
Bin	1	0	322174	1

Port:

TXTB_PORT_A_DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	18868	1
Bin	1	0	320114	1

Port:

TXTB_PORT_A_DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	16474	1
Bin	1	0	322508	1

Port:

TXTB_PORT_A_DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	25047	1
Bin	1	0	313935	1

Port:

TXTB_PORT_A_DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	19169	1
Bin	1	0	319813	1

Port:

TXTB_PORT_A_DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	21501	1
Bin	1	0	317481	1

Port:

TXTB_PORT_A_DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	26436	1
Bin	1	0	312546	1

Port:

TXTB_PORT_A_DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	21343	1
Bin	1	0	317639	1

Port:

TXTB_PORT_A_DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	20412	1
Bin	1	0	318570	1

Port:

TXTB_PORT_A_DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	23917	1
Bin	1	0	315065	1

Port:

TXTB_PORT_A_DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	22658	1
Bin	1	0	316324	1

Port:

TXTB_PORT_A_DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	20997	1
Bin	1	0	317985	1

Port:

TXTB_PORT_A_DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	35338	1
Bin	1	0	303644	1

Port:

TXTB_PORT_A_DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	43965	1
Bin	1	0	295017	1

Port:

TXTB_PORT_A_DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	41196	1
Bin	1	0	297786	1

Port:

TXTB_PORT_A_DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	84963	1
Bin	1	0	254019	1

Port:

TXTB_PORT_A_DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	18507	1
Bin	1	0	320475	1

Port:

TXTB_PORT_A_DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	21922	1
Bin	1	0	317060	1

Port:

TXTB_PORT_A_DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	19202	1
Bin	1	0	319780	1

Port:

TXTB_PORT_A_DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	22335	1
Bin	1	0	316647	1

Port:

TXTB_PORT_A_DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	40384	1
Bin	1	0	298598	1

Port:

TXTB_PORT_A_DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	41708	1
Bin	1	0	297274	1

Port:

TXTB_PORT_A_DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	49733	1
Bin	1	0	289249	1

Port:

TXTB_PORT_A_DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	50881	1
Bin	1	0	288101	1

Port:

TXTB_PORT_A_DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	44637	1
Bin	1	0	294345	1

Port:

TXTB_PORT_A_DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	42583	1
Bin	1	0	296399	1

Port:

TXTB_PORT_A_DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	44992	1
Bin	1	0	293990	1

Port:

TXTB_PORT_A_DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	49747	1
Bin	1	0	289235	1

Port:

TXTB_PORT_A_DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	53414	1
Bin	1	0	285568	1

Port:

TXTB_PORT_A_DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	56312	1
Bin	1	0	282670	1

Port:

TXTB_PORT_A_DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	97154	1
Bin	1	0	241828	1

Port:

TXTB_PORT_A_DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	84031	1
Bin	1	0	254951	1

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold
Bin	0	1	270660	1
Bin	1	0	68322	1

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	11306	1
Bin	1	0	11471	1

Port:

TXTB_PORT_A_BE(3)

	From	To	Count	Threshold
Bin	0	1	5053365	1
Bin	1	0	7925	1

Port:

TXTB_PORT_A_BE(2)

	From	To	Count	Threshold
Bin	0	1	5053445	1
Bin	1	0	7845	1

Port:

TXTB_PORT_A_BE(1)

	From	To	Count	Threshold
Bin	0	1	5039204	1
Bin	1	0	22086	1

Port:

TXTB_PORT_A_BE(0)

	From	To	Count	Threshold
Bin	0	1	5039488	1
Bin	1	0	21802	1

Port:

TXTB_PORT_B_ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	3193	1
Bin	1	0	3358	1

Port:

TXTB_PORT_B_ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	114	1
Bin	1	0	279	1

Port:

TXTB_PORT_B_ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	4926	1
Bin	1	0	5091	1

Port:

TXTB_PORT_B_ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	3696	1
Bin	1	0	3696	1

Port:

TXTB_PORT_B_ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	10610	1
Bin	1	0	10775	1

Port:

TXTB_PORT_B_DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	471	1

Port:

TXTB_PORT_B_DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	409	1

Port:

TXTB_PORT_B_DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	403	1

Port:

TXTB_PORT_B_DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	827	1
Bin	1	0	978	1

Port:

TXTB_PORT_B_DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	714	1
Bin	1	0	865	1

Port:

TXTB_PORT_B_DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	715	1
Bin	1	0	863	1

Port:

TXTB_PORT_B_DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	510	1
Bin	1	0	659	1

Port:

TXTB_PORT_B_DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	496	1
Bin	1	0	646	1

Port:

TXTB_PORT_B_DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	902	1

Port:

TXTB_PORT_B_DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	608	1
Bin	1	0	759	1

Port:

TXTB_PORT_B_DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	546	1
Bin	1	0	694	1

Port:

TXTB_PORT_B_DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	920	1

Port:

TXTB_PORT_B_DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	774	1

Port:

TXTB_PORT_B_DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	760	1
Bin	1	0	910	1

Port:

TXTB_PORT_B_DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	449	1
Bin	1	0	600	1

Port:

TXTB_PORT_B_DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	551	1

Port:

TXTB_PORT_B_DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	607	1
Bin	1	0	759	1

Port:

TXTB_PORT_B_DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	398	1
Bin	1	0	552	1

Port:

TXTB_PORT_B_DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	633	1
Bin	1	0	786	1

Port:

TXTB_PORT_B_DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	454	1
Bin	1	0	605	1

Port:

TXTB_PORT_B_DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	796	1

Port:

TXTB_PORT_B_DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	822	1

Port:

TXTB_PORT_B_DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	960	1
Bin	1	0	1109	1

Port:

TXTB_PORT_B_DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	684	1
Bin	1	0	835	1

Port:

TXTB_PORT_B_DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	1064	1
Bin	1	0	1208	1

Port:

TXTB_PORT_B_DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	825	1
Bin	1	0	974	1

Port:

TXTB_PORT_B_DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	504	1
Bin	1	0	654	1

Port:

TXTB_PORT_B_DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	600	1

Port:

TXTB_PORT_B_DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	791	1
Bin	1	0	940	1

Port:

TXTB_PORT_B_DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	946	1

Port:

TXTB_PORT_B_DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	793	1
Bin	1	0	943	1

Port:

TXTB_PORT_B_DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	567	1
Bin	1	0	710	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	500	1
Bin	1	0	665	1

Signal:

TXTB_PORT_A_ADDRESS_I(4)

	From	To	Count	Threshold
Bin	0	1	101815	1
Bin	1	0	4952814	1

Signal:

TXTB_PORT_A_ADDRESS_I(3)

	From	To	Count	Threshold
Bin	0	1	128238	1
Bin	1	0	4926381	1

Signal:

TXTB_PORT_A_ADDRESS_I(2)

	From	To	Count	Threshold
Bin	0	1	109944	1
Bin	1	0	4944819	1

Signal:

TXTB_PORT_A_ADDRESS_I(1)

	From	To	Count	Threshold
Bin	0	1	4814581	1
Bin	1	0	240470	1

Signal:

TXTB_PORT_A_ADDRESS_I(0)

	From	To	Count	Threshold
Bin	0	1	3622587	1
Bin	1	0	1433086	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11545	1
Bin	1	0	11747	1

Signal:

TXTB_PORT_A_DATA_I(31)

	From	To	Count	Threshold
Bin	0	1	16682	1
Bin	1	0	317940	1

Signal:

TXTB_PORT_A_DATA_I(30)

	From	To	Count	Threshold
Bin	0	1	18745	1
Bin	1	0	315867	1

Signal:

TXTB_PORT_A_DATA_I(29)

	From	To	Count	Threshold
Bin	0	1	16355	1
Bin	1	0	318255	1

Signal:

TXTB_PORT_A_DATA_I(28)

	From	To	Count	Threshold
Bin	0	1	24930	1
Bin	1	0	309700	1

Signal:

TXTB_PORT_A_DATA_I(27)

	From	To	Count	Threshold
Bin	0	1	19050	1
Bin	1	0	315574	1

Signal:

TXTB_PORT_A_DATA_I(26)

	From	To	Count	Threshold
Bin	0	1	21373	1
Bin	1	0	313249	1

Signal:

TXTB_PORT_A_DATA_I(25)

	From	To	Count	Threshold
Bin	0	1	26299	1
Bin	1	0	308325	1

Signal:

TXTB_PORT_A_DATA_I(24)

	From	To	Count	Threshold
Bin	0	1	21226	1
Bin	1	0	313396	1

Signal:

TXTB_PORT_A_DATA_I(23)

	From	To	Count	Threshold
Bin	0	1	20291	1
Bin	1	0	314331	1

Signal:

TXTB_PORT_A_DATA_I(22)

	From	To	Count	Threshold
Bin	0	1	23791	1
Bin	1	0	310829	1

Signal:

TXTB_PORT_A_DATA_I(21)

	From	To	Count	Threshold
Bin	0	1	22533	1
Bin	1	0	312085	1

Signal:

TXTB_PORT_A_DATA_I(20)

	From	To	Count	Threshold
Bin	0	1	20875	1
Bin	1	0	313753	1

Signal:

TXTB_PORT_A_DATA_I(19)

	From	To	Count	Threshold
Bin	0	1	33354	1
Bin	1	0	301287	1

Signal:

TXTB_PORT_A_DATA_I(18)

	From	To	Count	Threshold
Bin	0	1	43048	1
Bin	1	0	291580	1

Signal:

TXTB_PORT_A_DATA_I(17)

	From	To	Count	Threshold
Bin	0	1	40270	1
Bin	1	0	294355	1

Signal:

TXTB_PORT_A_DATA_I(16)

	From	To	Count	Threshold
Bin	0	1	83594	1
Bin	1	0	251022	1

Signal:

TXTB_PORT_A_DATA_I(15)

	From	To	Count	Threshold
Bin	0	1	18389	1
Bin	1	0	316247	1

Signal:

TXTB_PORT_A_DATA_I(14)

	From	To	Count	Threshold
Bin	0	1	21805	1
Bin	1	0	312833	1

Signal:

TXTB_PORT_A_DATA_I(13)

	From	To	Count	Threshold
Bin	0	1	19083	1
Bin	1	0	315545	1

Signal:

TXTB_PORT_A_DATA_I(12)

	From	To	Count	Threshold
Bin	0	1	22218	1
Bin	1	0	312418	1

Signal:

TXTB_PORT_A_DATA_I(11)

	From	To	Count	Threshold
Bin	0	1	40263	1
Bin	1	0	294363	1

Signal:

TXTB_PORT_A_DATA_I(10)

	From	To	Count	Threshold
Bin	0	1	41579	1
Bin	1	0	293051	1

Signal:

TXTB_PORT_A_DATA_I(9)

	From	To	Count	Threshold
Bin	0	1	49599	1
Bin	1	0	285039	1

Signal:

TXTB_PORT_A_DATA_I(8)

	From	To	Count	Threshold
Bin	0	1	50746	1
Bin	1	0	283882	1

Signal:

TXTB_PORT_A_DATA_I(7)

	From	To	Count	Threshold
Bin	0	1	44518	1
Bin	1	0	290128	1

Signal:

TXTB_PORT_A_DATA_I(6)

	From	To	Count	Threshold
Bin	0	1	42465	1
Bin	1	0	292177	1

Signal:

TXTB_PORT_A_DATA_I(5)

	From	To	Count	Threshold
Bin	0	1	44872	1
Bin	1	0	289760	1

Signal:

TXTB_PORT_A_DATA_I(4)

	From	To	Count	Threshold
Bin	0	1	48992	1
Bin	1	0	285632	1

Signal:

TXTB_PORT_A_DATA_I(3)

	From	To	Count	Threshold
Bin	0	1	52101	1
Bin	1	0	282533	1

Signal:

TXTB_PORT_A_DATA_I(2)

	From	To	Count	Threshold
Bin	0	1	54952	1
Bin	1	0	279687	1

Signal:

TXTB_PORT_A_DATA_I(1)

	From	To	Count	Threshold
Bin	0	1	94864	1
Bin	1	0	239763	1

Signal:

TXTB_PORT_A_DATA_I(0)

	From	To	Count	Threshold
Bin	0	1	81928	1
Bin	1	0	252719	1

Signal:

TXTB_PORT_B_ADDRESS_I(4)

	From	To	Count	Threshold
Bin	0	1	3248	1
Bin	1	0	3413	1

Signal:

TXTB_PORT_B_ADDRESS_I(3)

	From	To	Count	Threshold
Bin	0	1	164	1
Bin	1	0	329	1

Signal:

TXTB_PORT_B_ADDRESS_I(2)

	From	To	Count	Threshold
Bin	0	1	5048	1
Bin	1	0	5213	1

Signal:

TXTB_PORT_B_ADDRESS_I(1)

	From	To	Count	Threshold
Bin	0	1	4010	1
Bin	1	0	4010	1

Signal:

TXTB_PORT_B_ADDRESS_I(0)

	From	To	Count	Threshold
Bin	0	1	11143	1
Bin	1	0	11308	1

Signal:

TXTB_PORT_B_DATA_OUT_I(31)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	471	1

Signal:

TXTB_PORT_B_DATA_OUT_I(30)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	409	1

Signal:

TXTB_PORT_B_DATA_OUT_I(29)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	403	1

Signal:

TXTB_PORT_B_DATA_OUT_I(28)

	From	To	Count	Threshold
Bin	0	1	827	1
Bin	1	0	978	1

Signal:

TXTB_PORT_B_DATA_OUT_I(27)

	From	To	Count	Threshold
Bin	0	1	714	1
Bin	1	0	865	1

Signal:

TXTB_PORT_B_DATA_OUT_I(26)

	From	To	Count	Threshold
Bin	0	1	715	1
Bin	1	0	863	1

Signal:

TXTB_PORT_B_DATA_OUT_I(25)

	From	To	Count	Threshold
Bin	0	1	510	1
Bin	1	0	659	1

Signal:

TXTB_PORT_B_DATA_OUT_I(24)

	From	To	Count	Threshold
Bin	0	1	496	1
Bin	1	0	646	1

Signal:

TXTB_PORT_B_DATA_OUT_I(23)

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	902	1

Signal:

TXTB_PORT_B_DATA_OUT_I(22)

	From	To	Count	Threshold
Bin	0	1	608	1
Bin	1	0	759	1

Signal:

TXTB_PORT_B_DATA_OUT_I(21)

	From	To	Count	Threshold
Bin	0	1	546	1
Bin	1	0	694	1

Signal:

TXTB_PORT_B_DATA_OUT_I(20)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	920	1

Signal:

TXTB_PORT_B_DATA_OUT_I(19)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	774	1

Signal:

TXTB_PORT_B_DATA_OUT_I(18)

	From	To	Count	Threshold
Bin	0	1	760	1
Bin	1	0	910	1

Signal:

TXTB_PORT_B_DATA_OUT_I(17)

	From	To	Count	Threshold
Bin	0	1	449	1
Bin	1	0	600	1

Signal:

TXTB_PORT_B_DATA_OUT_I(16)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	551	1

Signal:

TXTB_PORT_B_DATA_OUT_I(15)

	From	To	Count	Threshold
Bin	0	1	607	1
Bin	1	0	759	1

Signal:

TXTB_PORT_B_DATA_OUT_I(14)

	From	To	Count	Threshold
Bin	0	1	398	1
Bin	1	0	552	1

Signal:

TXTB_PORT_B_DATA_OUT_I(13)

	From	To	Count	Threshold
Bin	0	1	633	1
Bin	1	0	786	1

Signal:

TXTB_PORT_B_DATA_OUT_I(12)

	From	To	Count	Threshold
Bin	0	1	454	1
Bin	1	0	605	1

Signal:

TXTB_PORT_B_DATA_OUT_I(11)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	796	1

Signal:

TXTB_PORT_B_DATA_OUT_I(10)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	822	1

Signal:

TXTB_PORT_B_DATA_OUT_I(9)

	From	To	Count	Threshold
Bin	0	1	960	1
Bin	1	0	1109	1

Signal:

TXTB_PORT_B_DATA_OUT_I(8)

	From	To	Count	Threshold
Bin	0	1	684	1
Bin	1	0	835	1

Signal:

TXTB_PORT_B_DATA_OUT_I(7)

	From	To	Count	Threshold
Bin	0	1	1064	1
Bin	1	0	1208	1

Signal:

TXTB_PORT_B_DATA_OUT_I(6)

	From	To	Count	Threshold
Bin	0	1	825	1
Bin	1	0	974	1

Signal:

TXTB_PORT_B_DATA_OUT_I(5)

	From	To	Count	Threshold
Bin	0	1	504	1
Bin	1	0	654	1

Signal:

TXTB_PORT_B_DATA_OUT_I(4)

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	600	1

Signal:

TXTB_PORT_B_DATA_OUT_I(3)

	From	To	Count	Threshold
Bin	0	1	791	1
Bin	1	0	940	1

Signal:

TXTB_PORT_B_DATA_OUT_I(2)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	946	1

Signal:

TXTB_PORT_B_DATA_OUT_I(1)

	From	To	Count	Threshold
Bin	0	1	793	1
Bin	1	0	943	1

Signal:

TXTB_PORT_B_DATA_OUT_I(0)

	From	To	Count	Threshold
Bin	0	1	567	1
Bin	1	0	710	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	87	1
Bin	1	0	252	1

Signal:

PARITY_WORD(20)

	From	To	Count	Threshold
Bin	0	1	23	1
Bin	1	0	702	1

Signal:

PARITY_WORD(19)

	From	To	Count	Threshold
Bin	0	1	4	1
Bin	1	0	721	1

Signal:

PARITY_WORD(18)

	From	To	Count	Threshold
Bin	0	1	2	1
Bin	1	0	723	1

Signal:

PARITY_WORD(17)

	From	To	Count	Threshold
Bin	0	1	13	1
Bin	1	0	712	1

Signal:

PARITY_WORD(16)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	719	1

Signal:

PARITY_WORD(15)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	715	1

Signal:

PARITY_WORD(14)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	715	1

Signal:

PARITY_WORD(13)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	715	1

Signal:

PARITY_WORD(12)

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	713	1

Signal:

PARITY_WORD(11)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	703	1

Signal:

PARITY_WORD(10)

	From	To	Count	Threshold
Bin	0	1	31	1
Bin	1	0	694	1

Signal:

PARITY_WORD(9)

	From	To	Count	Threshold
Bin	0	1	35	1
Bin	1	0	690	1

Signal:

PARITY_WORD(8)

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	661	1

Signal:

PARITY_WORD(7)

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	679	1

Signal:

PARITY_WORD(6)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	682	1

Signal:

PARITY_WORD(5)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	640	1

Signal:

PARITY_WORD(4)

	From	To	Count	Threshold
Bin	0	1	167	1
Bin	1	0	558	1

Signal:

PARITY_WORD(3)

	From	To	Count	Threshold
Bin	0	1	311	1
Bin	1	0	414	1

Signal:

PARITY_WORD(2)

	From	To	Count	Threshold
Bin	0	1	396	1
Bin	1	0	329	1

Signal:

PARITY_WORD(1)

	From	To	Count	Threshold
Bin	0	1	281	1
Bin	1	0	444	1

Signal:

PARITY_WORD(0)

	From	To	Count	Threshold
Bin	0	1	258	1
Bin	1	0	467	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1130	1
Bin	1	0	984	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	994	1
Bin	1	0	1159	1

Uncovered expressions:

Excluded expressions:

"and" expression

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

"and" expression

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	LHS	RHS	Count	Threshold
Bin	True	False	584	1
Bin	True	True	87	1

"=" expression

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	15150	1
Bin	True	10165550	1

"=" expression

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	1033	1
Bin	True	95263	1

"=" expression

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	9212	1
Bin	True	674105	1

"=" expression

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	1278	1
Bin	True	83922	1

"=" expression

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')

	Evaluated to	Count	Threshold
Bin	False	4146	1
Bin	True	586	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

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