NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DFF_ENA_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
DFF_FIXED_STUFF_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)
DFF_DESTUFFED_FLAG_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
DFF_ERR_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
DFF_PREV_VAL_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
DFF_DATA_OUT_VAL_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

DFF_ENA_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

DFF_FIXED_STUFF_REG

100.0 % (4/4)

100.0 % (6/6)

100.0 % (10/10)

100.0 % (4/4)

N.A.

100.0 % (24/24)

DFF_DESTUFFED_FLAG_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

DFF_ERR_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

DFF_PREV_VAL_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

DFF_DATA_OUT_VAL_REG

100.0 % (4/4)

100.0 % (6/6)

100.0 % (10/10)

100.0 % (4/4)

N.A.

100.0 % (24/24)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_DESTUFFING_INST	100.0 % (53/53)	100.0 % (48/48)	100.0 % (88/88)	100.0 % (107/107)	N.A.	N.A.	100.0 % (296/296)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_DESTUFFING_INST

100.0 % (53/53)

100.0 % (48/48)

100.0 % (88/88)

100.0 % (107/107)

N.A.

100.0 % (296/296)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 208 to 210:

208:    non_fix_to_fix_chng    <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0') 
209:                                  else 
210:                              '0';

Count: 58850
Threshold: 1

Signal assignment statement on line 208:

208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0')
Count: 13512
Threshold: 1

Signal assignment statement on line 210:

210: '0';
Count: 45338
Threshold: 1

If statement on lines 222 to 224:

222:    stuff_lvl_reached <= '1' when (same_bits_q = "101") 
223:                             else 
224:                         '0';

Count: 6479449
Threshold: 1

Signal assignment statement on line 222:

222: stuff_lvl_reached <= '1' when (same_bits_q = "101")
Count: 1011475
Threshold: 1

Signal assignment statement on line 224:

224: '0';
Count: 5467974
Threshold: 1

If statement on lines 231 to 233:

231:    discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') 
232:                             else 
233:                         '0';

Count: 2051421
Threshold: 1

Signal assignment statement on line 231:

231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
Count: 1024987
Threshold: 1

Signal assignment statement on line 233:

233: '0';
Count: 1026434
Threshold: 1

If statement on lines 240 to 242:

240:    fixed_prev_d <= '0'         when (enable_prev = '0') else 
241:                    fixed_stuff when (bds_trigger = '1') else 
242:                    fixed_prev_q;

Count: 45727955
Threshold: 1

Signal assignment statement on line 240:

240: fixed_prev_d <= '0' when (enable_prev = '0') else
Count: 15791082
Threshold: 1

Signal assignment statement on line 241:

241: fixed_stuff when (bds_trigger = '1') else
Count: 14937611
Threshold: 1

Signal assignment statement on line 242:

242: fixed_prev_q;
Count: 14999262
Threshold: 1

If statement on lines 250 to 253:

250:    stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and 
251:                                    destuff_enable = '1') 
252:                              else 
253:                          '0';

Count: 7745899
Threshold: 1

Signal assignment statement on line 250:

250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and
Count: 2020549
Threshold: 1

Signal assignment statement on line 253:

253: '0';
Count: 5725350
Threshold: 1

Signal assignment statement on line 276:

276: dst_ctr_add <= (dst_ctr_q + 1) mod 8;
Count: 995560
Threshold: 1

If statement on lines 284 to 289:

284:    dst_ctr_d <=       "000"  when (enable_prev = '0') 
285:                              else 
286:                 dst_ctr_add  when (bds_trigger = '1' and stuff_lvl_reached = '1' and 
287:                                    fixed_stuff = '0') 
288:                              else 
289:                  dst_ctr_q;

Count: 48725146
Threshold: 1

Signal assignment statement on line 284:

284: dst_ctr_d <= "000" when (enable_prev = '0')
Count: 15802834
Threshold: 1

Signal assignment statement on line 286:

286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and
Count: 3773520
Threshold: 1

Signal assignment statement on line 289:

289: dst_ctr_q;
Count: 29148792
Threshold: 1

If statement on lines 296 to 302:

296:        if (res_n = '0') then 
297:            dst_ctr_q <= (others => '0'); 
...
301:            end if; 
302:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 297:

297: dst_ctr_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 299 to 301:

299:            if (destuff_enable = '1') then 
300:                dst_ctr_q <= dst_ctr_d; 
301:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 300:

300: dst_ctr_q <= dst_ctr_d;
Count: 302936168
Threshold: 1

If statement on lines 311 to 315:

311:    same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else 
312:                       '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else 
313:                       '1' when (bds_trigger = '1' and data_in /= prev_val_q and 
314:                                 fixed_stuff = '0') else 
315:                       '0';

Count: 53443892
Threshold: 1

Signal assignment statement on line 311:

311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else
Count: 16179142
Threshold: 1

Signal assignment statement on line 312:

312:                       '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else

Count: 4052959
Threshold: 1

Signal assignment statement on line 313:

313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and
Count: 2092341
Threshold: 1

Signal assignment statement on line 315:

315: '0';
Count: 31119450
Threshold: 1

Signal assignment statement on line 320:

320: same_bits_add <= (same_bits_q + 1) mod 8;
Count: 6479449
Threshold: 1

If statement on lines 328 to 330:

328:    same_bits_d   <=         "001" when (same_bits_erase = '1') else 
329:                     same_bits_add when (bds_trigger = '1') else 
330:                     same_bits_q;

Count: 66373876
Threshold: 1

Signal assignment statement on line 328:

328: same_bits_d <= "001" when (same_bits_erase = '1') else
Count: 25133180
Threshold: 1

Signal assignment statement on line 329:

329: same_bits_add when (bds_trigger = '1') else
Count: 26268683
Threshold: 1

Signal assignment statement on line 330:

330: same_bits_q;
Count: 14972013
Threshold: 1

If statement on lines 337 to 341:

337:        if (res_n = '0') then 
338:            same_bits_q <= "001"; 
339:        elsif (rising_edge(clk_sys)) then 
340:            same_bits_q <= same_bits_d; 
341:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 338:

338: same_bits_q <= "001";
Count: 2424883
Threshold: 1

Signal assignment statement on line 340:

340: same_bits_q <= same_bits_d;
Count: 543791678
Threshold: 1

If statement on lines 351 to 354:

351:    destuffed_d   <= '0' when (destuff_enable = '0') else 
352:                     '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else 
353:                     '0' when (bds_trigger = '1') else 
354:                     destuffed_q;

Count: 49766216
Threshold: 1

Signal assignment statement on line 351:

351: destuffed_d <= '0' when (destuff_enable = '0') else
Count: 15812511
Threshold: 1

Signal assignment statement on line 352:

352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
Count: 4078762
Threshold: 1

Signal assignment statement on line 353:

353: '0' when (bds_trigger = '1') else
Count: 14890937
Threshold: 1

Signal assignment statement on line 354:

354: destuffed_q;
Count: 14984006
Threshold: 1

If statement on lines 377 to 378:

377:    stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else 
378:                   '0';

Count: 47128661
Threshold: 1

Signal assignment statement on line 377:

377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else
Count: 1591987
Threshold: 1

Signal assignment statement on line 378:

378: '0';
Count: 45536674
Threshold: 1

If statement on lines 401 to 403:

401:    prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else 
402:                  data_in   when (bds_trigger = '1') else 
403:                  prev_val_q;

Count: 51172864
Threshold: 1

Signal assignment statement on line 401:

401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
Count: 35276
Threshold: 1

Signal assignment statement on line 402:

402: data_in when (bds_trigger = '1') else
Count: 25537144
Threshold: 1

Signal assignment statement on line 403:

403: prev_val_q;
Count: 25600444
Threshold: 1

Signal assignment statement on line 444:

444: destuffed <= destuffed_q;
Count: 2048050
Threshold: 1

Signal assignment statement on line 445:

445: stuff_err <= stuff_err_q;
Count: 44546
Threshold: 1

Signal assignment statement on line 446:

446: dst_ctr <= std_logic_vector(dst_ctr_q);
Count: 995560
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 208:

208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0')

	Evaluated to	Count	Threshold
Bin	True	13512	1
Bin	False	45338	1

"if" / "when" / "else" condition on line 222:

222: stuff_lvl_reached <= '1' when (same_bits_q = "101")

	Evaluated to	Count	Threshold
Bin	True	1011475	1
Bin	False	5467974	1

"if" / "when" / "else" condition on line 231:

231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')

	Evaluated to	Count	Threshold
Bin	True	1024987	1
Bin	False	1026434	1

"if" / "when" / "else" condition on line 240:

240: fixed_prev_d <= '0' when (enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	15791082	1
Bin	False	29936873	1

"if" / "when" / "else" condition on line 241:

241: fixed_stuff when (bds_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	14937611	1
Bin	False	14999262	1

"if" / "when" / "else" condition on lines 250 to 251:

250:    stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and 
251:                                    destuff_enable = '1')

	Evaluated to	Count	Threshold
Bin	True	2020549	1
Bin	False	5725350	1

"if" / "when" / "else" condition on line 284:

284: dst_ctr_d <= "000" when (enable_prev = '0')

	Evaluated to	Count	Threshold
Bin	True	15802834	1
Bin	False	32922312	1

"if" / "when" / "else" condition on lines 286 to 287:

286:                 dst_ctr_add  when (bds_trigger = '1' and stuff_lvl_reached = '1' and 
287:                                    fixed_stuff = '0')

	Evaluated to	Count	Threshold
Bin	True	3773520	1
Bin	False	29148792	1

"if" / "when" / "else" condition on line 296:

296: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 298:

298: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 299:

299: if (destuff_enable = '1') then

	Evaluated to	Count	Threshold
Bin	True	302936168	1
Bin	False	240855510	1

"if" / "when" / "else" condition on line 311:

311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else

	Evaluated to	Count	Threshold
Bin	True	16179142	1
Bin	False	37264750	1

"if" / "when" / "else" condition on line 312:

312:                       '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	4052959	1
Bin	False	33211791	1

"if" / "when" / "else" condition on lines 313 to 314:

313:                       '1' when (bds_trigger = '1' and data_in /= prev_val_q and 
314:                                 fixed_stuff = '0') else

	Evaluated to	Count	Threshold
Bin	True	2092341	1
Bin	False	31119450	1

"if" / "when" / "else" condition on line 328:

328: same_bits_d <= "001" when (same_bits_erase = '1') else

	Evaluated to	Count	Threshold
Bin	True	25133180	1
Bin	False	41240696	1

"if" / "when" / "else" condition on line 329:

329: same_bits_add when (bds_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	26268683	1
Bin	False	14972013	1

"if" / "when" / "else" condition on line 337:

337: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 339:

339: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 351:

351: destuffed_d <= '0' when (destuff_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	15812511	1
Bin	False	33953705	1

"if" / "when" / "else" condition on line 352:

352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else

	Evaluated to	Count	Threshold
Bin	True	4078762	1
Bin	False	29874943	1

"if" / "when" / "else" condition on line 353:

353: '0' when (bds_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	14890937	1
Bin	False	14984006	1

"if" / "when" / "else" condition on line 377:

377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else

	Evaluated to	Count	Threshold
Bin	True	1591987	1
Bin	False	45536674	1

"if" / "when" / "else" condition on line 401:

401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else

	Evaluated to	Count	Threshold
Bin	True	35276	1
Bin	False	51137588	1

"if" / "when" / "else" condition on line 402:

402: data_in when (bds_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	25537144	1
Bin	False	25600444	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BDS_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DESTUFF_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

FIXED_STUFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

DATA_OUT

	From	To	Count	Threshold
Bin	0	1	1392677	1
Bin	1	0	1391076	1

Port:

STUFF_ERR

	From	To	Count	Threshold
Bin	0	1	20672	1
Bin	1	0	22273	1

Port:

DESTUFFED

	From	To	Count	Threshold
Bin	0	1	1022424	1
Bin	1	0	1024025	1

Port:

DST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	117682	1
Bin	(2)	1	0	119283	1
Bin	(1)	0	1	242662	1
Bin	(1)	1	0	244257	1
Bin	(0)	0	1	484884	1
Bin	(0)	1	0	486480	1

Signal:

DISCARD_STUFF_BIT

	From	To	Count	Threshold
Bin	0	1	1023232	1
Bin	1	0	1024833	1

Signal:

NON_FIX_TO_FIX_CHNG

	From	To	Count	Threshold
Bin	0	1	13512	1
Bin	1	0	15113	1

Signal:

STUFF_LVL_REACHED

	From	To	Count	Threshold
Bin	0	1	1011475	1
Bin	1	0	1013076	1

Signal:

STUFF_RULE_VIOLATE

	From	To	Count	Threshold
Bin	0	1	2020549	1
Bin	1	0	2022150	1

Signal:

ENABLE_PREV

	From	To	Count	Threshold
Bin	0	1	55762	1
Bin	1	0	57363	1

Signal:

FIXED_PREV_Q

	From	To	Count	Threshold
Bin	0	1	13512	1
Bin	1	0	15112	1

Signal:

FIXED_PREV_D

	From	To	Count	Threshold
Bin	0	1	39464	1
Bin	1	0	41065	1

Signal:

SAME_BITS_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	5811542	1
Bin	(2)	1	0	5813143	1
Bin	(1)	0	1	12261792	1
Bin	(1)	1	0	12263393	1
Bin	(0)	0	1	18696101	1
Bin	(0)	1	0	18694500	1

Signal:

SAME_BITS_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	1105373	1
Bin	(2)	1	0	1106974	1
Bin	(1)	0	1	1551443	1
Bin	(1)	1	0	1553044	1
Bin	(0)	0	1	2658417	1
Bin	(0)	1	0	2656816	1

Signal:

SAME_BITS_ADD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	1256513	1
Bin	(2)	1	0	1258114	1
Bin	(1)	0	1	1258114	1
Bin	(1)	1	0	1256513	1
Bin	(0)	0	1	2656816	1
Bin	(0)	1	0	2658417	1

Signal:

SAME_BITS_ERASE

	From	To	Count	Threshold
Bin	0	1	5205992	1
Bin	1	0	5205992	1

Signal:

DESTUFFED_Q

	From	To	Count	Threshold
Bin	0	1	1022424	1
Bin	1	0	1024025	1

Signal:

DESTUFFED_D

	From	To	Count	Threshold
Bin	0	1	5080503	1
Bin	1	0	5082104	1

Signal:

STUFF_ERR_Q

	From	To	Count	Threshold
Bin	0	1	20672	1
Bin	1	0	22273	1

Signal:

STUFF_ERR_D

	From	To	Count	Threshold
Bin	0	1	1591987	1
Bin	1	0	1593588	1

Signal:

DST_CTR_Q

	Element	From	To	Count	Threshold
Bin	(2)	0	1	117682	1
Bin	(2)	1	0	119283	1
Bin	(1)	0	1	242662	1
Bin	(1)	1	0	244257	1
Bin	(0)	0	1	484884	1
Bin	(0)	1	0	486480	1

Signal:

DST_CTR_D

	Element	From	To	Count	Threshold
Bin	(2)	0	1	548431	1
Bin	(2)	1	0	550032	1
Bin	(1)	0	1	1159604	1
Bin	(1)	1	0	1161205	1
Bin	(0)	0	1	2372856	1
Bin	(0)	1	0	2374457	1

Signal:

DST_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	126443	1
Bin	(2)	1	0	128043	1
Bin	(1)	0	1	257838	1
Bin	(1)	1	0	259430	1
Bin	(0)	0	1	486480	1
Bin	(0)	1	0	484884	1

Signal:

PREV_VAL_Q

	From	To	Count	Threshold
Bin	0	1	1391134	1
Bin	1	0	1389533	1

Signal:

PREV_VAL_D

	From	To	Count	Threshold
Bin	0	1	2546345	1
Bin	1	0	2544744	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 208:

 fixed_stuff = '1' and fixed_prev_q = '0' 
 <------LHS------>     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	15112	1
Bin	True	False	13512	1
Bin	True	True	13512	1

"=" expression on line 208:

fixed_stuff = '1'

	Evaluated to	Count	Threshold
Bin	False	31826	1
Bin	True	27024	1

"=" expression on line 208:

fixed_prev_q = '0'

	Evaluated to	Count	Threshold
Bin	False	30226	1
Bin	True	28624	1

"or" expression on line 231:

 non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1' 
 <----------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	1026434	1
Bin	False	True	1011475	1
Bin	True	False	11757	1

"=" expression on line 231:

non_fix_to_fix_chng = '1'

	Evaluated to	Count	Threshold
Bin	False	2037909	1
Bin	True	13512	1

"=" expression on line 231:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	1038191	1
Bin	True	1013230	1

"=" expression on line 240:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	29936873	1
Bin	True	15791082	1

"=" expression on line 241:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	14999262	1
Bin	True	14937611	1

"and" expression on lines 250 to 251:

 discard_stuff_bit = '1' and prev_val_q = data_in and destuff_enable = '1' 
 <---------------------LHS---------------------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	5388107	1
Bin	True	False	808	1
Bin	True	True	2020549	1

"and" expression on line 250:

 discard_stuff_bit = '1' and prev_val_q = data_in 
 <---------LHS--------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	2926620	1
Bin	True	False	1002699	1
Bin	True	True	2021357	1

"=" expression on line 250:

discard_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	4721843	1
Bin	True	3024056	1

"=" expression on line 250:

prev_val_q = data_in

	Evaluated to	Count	Threshold
Bin	False	2797922	1
Bin	True	4947977	1

"=" expression on line 251:

destuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	337243	1
Bin	True	7408656	1

"=" expression on line 284:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	32922312	1
Bin	True	15802834	1

"and" expression on lines 286 to 287:

 bds_trigger = '1' and stuff_lvl_reached = '1' and fixed_stuff = '0' 
 <--------------------LHS-------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	27565103	1
Bin	True	False	202078	1
Bin	True	True	3773520	1

"and" expression on line 286:

 bds_trigger = '1' and stuff_lvl_reached = '1' 
 <------LHS------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	2024066	1
Bin	True	False	13900991	1
Bin	True	True	3975598	1

"=" expression on line 286:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	15045723	1
Bin	True	17876589	1

"=" expression on line 286:

stuff_lvl_reached = '1'

	Evaluated to	Count	Threshold
Bin	False	26922648	1
Bin	True	5999664	1

"=" expression on line 287:

fixed_stuff = '0'

	Evaluated to	Count	Threshold
Bin	False	1583689	1
Bin	True	31338623	1

"=" expression on line 296:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 299:

destuff_enable = '1'

	Evaluated to	Count	Threshold
Bin	False	240855510	1
Bin	True	302936168	1

"or" expression on line 311:

 destuff_enable = '0' or enable_prev = '0' 
 <-------LHS-------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	37264750	1
Bin	False	True	55786	1
Bin	True	False	56918	1

"=" expression on line 311:

destuff_enable = '0'

	Evaluated to	Count	Threshold
Bin	False	37320536	1
Bin	True	16123356	1

"=" expression on line 311:

enable_prev = '0'

	Evaluated to	Count	Threshold
Bin	False	37321668	1
Bin	True	16122224	1

"and" expression on line 312:

 bds_trigger = '1' and discard_stuff_bit = '1' 
 <------LHS------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	3050837	1
Bin	True	False	15540794	1
Bin	True	True	4052959	1

"=" expression on line 312:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	17670997	1
Bin	True	19593753	1

"=" expression on line 312:

discard_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	30160954	1
Bin	True	7103796	1

"and" expression on lines 313 to 314:

 bds_trigger = '1' and data_in /= prev_val_q and fixed_stuff = '0' 
 <-------------------LHS------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	29371903	1
Bin	True	False	220490	1
Bin	True	True	2092341	1

"and" expression on line 313:

 bds_trigger = '1' and data_in /= prev_val_q 
 <------LHS------>     <--------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	3762012	1
Bin	True	False	13227963	1
Bin	True	True	2312831	1

"=" expression on line 313:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	17670997	1
Bin	True	15540794	1

"/=" expression on line 313:

data_in /= prev_val_q

	Evaluated to	Count	Threshold
Bin	False	27136948	1
Bin	True	6074843	1

"=" expression on line 314:

fixed_stuff = '0'

	Evaluated to	Count	Threshold
Bin	False	1747547	1
Bin	True	31464244	1

"=" expression on line 328:

same_bits_erase = '1'

	Evaluated to	Count	Threshold
Bin	False	41240696	1
Bin	True	25133180	1

"=" expression on line 329:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	14972013	1
Bin	True	26268683	1

"=" expression on line 337:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 351:

destuff_enable = '0'

	Evaluated to	Count	Threshold
Bin	False	33953705	1
Bin	True	15812511	1

"and" expression on line 352:

 bds_trigger = '1' and discard_stuff_bit = '1' 
 <------LHS------>     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	2045671	1
Bin	True	False	14890937	1
Bin	True	True	4078762	1

"=" expression on line 352:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	14984006	1
Bin	True	18969699	1

"=" expression on line 352:

discard_stuff_bit = '1'

	Evaluated to	Count	Threshold
Bin	False	27829272	1
Bin	True	6124433	1

"=" expression on line 353:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	14984006	1
Bin	True	14890937	1

"and" expression on line 377:

 bds_trigger = '1' and stuff_rule_violate = '1' 
 <------LHS------>     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	1598686	1
Bin	True	False	22183208	1
Bin	True	True	1591987	1

"=" expression on line 377:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	23353466	1
Bin	True	23775195	1

"=" expression on line 377:

stuff_rule_violate = '1'

	Evaluated to	Count	Threshold
Bin	False	43937988	1
Bin	True	3190673	1

"and" expression on line 401:

 bds_trigger = '1' and non_fix_to_fix_chng = '1' 
 <------LHS------>     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	40436	1
Bin	True	False	25537144	1
Bin	True	True	35276	1

"=" expression on line 401:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	25600444	1
Bin	True	25572420	1

"=" expression on line 401:

non_fix_to_fix_chng = '1'

	Evaluated to	Count	Threshold
Bin	False	51097152	1
Bin	True	75712	1

"=" expression on line 402:

bds_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	25600444	1
Bin	True	25537144	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_DESTUFFING_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 208 to 210:

Signal assignment statement on line 208:

Signal assignment statement on line 210:

If statement on lines 222 to 224:

Signal assignment statement on line 222:

Signal assignment statement on line 224:

If statement on lines 231 to 233:

Signal assignment statement on line 231:

Signal assignment statement on line 233:

If statement on lines 240 to 242:

Signal assignment statement on line 240:

Signal assignment statement on line 241:

Signal assignment statement on line 242:

If statement on lines 250 to 253:

Signal assignment statement on line 250:

Signal assignment statement on line 253:

Signal assignment statement on line 276:

If statement on lines 284 to 289:

Signal assignment statement on line 284:

Signal assignment statement on line 286:

Signal assignment statement on line 289:

If statement on lines 296 to 302:

Signal assignment statement on line 297:

If statement on lines 299 to 301:

Signal assignment statement on line 300:

If statement on lines 311 to 315:

Signal assignment statement on line 311:

Signal assignment statement on line 312:

Signal assignment statement on line 313:

Signal assignment statement on line 315:

Signal assignment statement on line 320:

If statement on lines 328 to 330:

Signal assignment statement on line 328:

Signal assignment statement on line 329:

Signal assignment statement on line 330:

If statement on lines 337 to 341:

Signal assignment statement on line 338:

Signal assignment statement on line 340:

If statement on lines 351 to 354:

Signal assignment statement on line 351:

Signal assignment statement on line 352:

Signal assignment statement on line 353:

Signal assignment statement on line 354:

If statement on lines 377 to 378:

Signal assignment statement on line 377:

Signal assignment statement on line 378:

If statement on lines 401 to 403:

Signal assignment statement on line 401:

Signal assignment statement on line 402:

Signal assignment statement on line 403:

Signal assignment statement on line 444:

Signal assignment statement on line 445:

Signal assignment statement on line 446:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 208:

"if" / "when" / "else" condition on line 222:

"if" / "when" / "else" condition on line 231:

"if" / "when" / "else" condition on line 240:

"if" / "when" / "else" condition on line 241:

"if" / "when" / "else" condition on lines 250 to 251:

"if" / "when" / "else" condition on line 284:

"if" / "when" / "else" condition on lines 286 to 287:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 298:

"if" / "when" / "else" condition on line 299:

"if" / "when" / "else" condition on line 311:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on lines 313 to 314:

"if" / "when" / "else" condition on line 328:

"if" / "when" / "else" condition on line 329: