Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_DESTUFFING_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| DFF_ENA_REG |
100.0 % (3/3) |
100.0 % (4/4) |
100.0 % (8/8) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (17/17) |
| DFF_FIXED_STUFF_REG |
100.0 % (4/4) |
100.0 % (6/6) |
100.0 % (10/10) |
100.0 % (4/4) |
N.A. |
N.A. |
100.0 % (24/24) |
| DFF_DESTUFFED_FLAG_REG |
100.0 % (3/3) |
100.0 % (4/4) |
100.0 % (8/8) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (17/17) |
| DFF_ERR_REG |
100.0 % (3/3) |
100.0 % (4/4) |
100.0 % (8/8) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (17/17) |
| DFF_PREV_VAL_REG |
100.0 % (3/3) |
100.0 % (4/4) |
100.0 % (8/8) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (17/17) |
| DFF_DATA_OUT_VAL_REG |
100.0 % (4/4) |
100.0 % (6/6) |
100.0 % (10/10) |
100.0 % (4/4) |
N.A. |
N.A. |
100.0 % (24/24) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0')
209: else
210: '0'; Count: 58663
Threshold: 1
Signal assignment statement:
208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0') Count: 13466
Threshold: 1
Signal assignment statement:
210: '0'; Count: 45197
Threshold: 1
If statement:
222: stuff_lvl_reached <= '1' when (same_bits_q = "101")
223: else
224: '0'; Count: 6457995
Threshold: 1
Signal assignment statement:
222: stuff_lvl_reached <= '1' when (same_bits_q = "101") Count: 1008541
Threshold: 1
Signal assignment statement:
224: '0'; Count: 5449454
Threshold: 1
If statement:
231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
232: else
233: '0'; Count: 2045585
Threshold: 1
Signal assignment statement:
231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') Count: 1022007
Threshold: 1
Signal assignment statement:
233: '0'; Count: 1023578
Threshold: 1
If statement:
240: fixed_prev_d <= '0' when (enable_prev = '0') else
241: fixed_stuff when (bds_trigger = '1') else
242: fixed_prev_q; Count: 44338107
Threshold: 1
Signal assignment statement:
240: fixed_prev_d <= '0' when (enable_prev = '0') else Count: 14482836
Threshold: 1
Signal assignment statement:
241: fixed_stuff when (bds_trigger = '1') else Count: 14897050
Threshold: 1
Signal assignment statement:
242: fixed_prev_q; Count: 14958221
Threshold: 1
If statement:
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and
251: destuff_enable = '1')
252: else
253: '0'; Count: 7733105
Threshold: 1
Signal assignment statement:
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and Count: 2015505
Threshold: 1
Signal assignment statement:
253: '0'; Count: 5717600
Threshold: 1
Signal assignment statement:
276: dst_ctr_add <= (dst_ctr_q + 1) mod 8; Count: 992866
Threshold: 1
If statement:
284: dst_ctr_d <= "000" when (enable_prev = '0')
285: else
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and
287: fixed_stuff = '0')
288: else
289: dst_ctr_q; Count: 47326819
Threshold: 1
Signal assignment statement:
284: dst_ctr_d <= "000" when (enable_prev = '0') Count: 14494336
Threshold: 1
Signal assignment statement:
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and Count: 3763116
Threshold: 1
Signal assignment statement:
289: dst_ctr_q; Count: 29069367
Threshold: 1
If statement:
296: if (res_n = '0') then
297: dst_ctr_q <= (others => '0');
...
301: end if;
302: end if; Count: 1055177083
Threshold: 1
Signal assignment statement:
297: dst_ctr_q <= (others => '0'); Count: 2418499
Threshold: 1
If statement:
299: if (destuff_enable = '1') then
300: dst_ctr_q <= dst_ctr_d;
301: end if; Count: 526374300
Threshold: 1
Signal assignment statement:
300: dst_ctr_q <= dst_ctr_d; Count: 304002549
Threshold: 1
If statement:
311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else
312: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and
314: fixed_stuff = '0') else
315: '0'; Count: 52041353
Threshold: 1
Signal assignment statement:
311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else Count: 14864520
Threshold: 1
Signal assignment statement:
312: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else Count: 4042631
Threshold: 1
Signal assignment statement:
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and Count: 2107163
Threshold: 1
Signal assignment statement:
315: '0'; Count: 31027039
Threshold: 1
Signal assignment statement:
320: same_bits_add <= (same_bits_q + 1) mod 8; Count: 6457995
Threshold: 1
If statement:
328: same_bits_d <= "001" when (same_bits_erase = '1') else
329: same_bits_add when (bds_trigger = '1') else
330: same_bits_q; Count: 64958379
Threshold: 1
Signal assignment statement:
328: same_bits_d <= "001" when (same_bits_erase = '1') else Count: 23837220
Threshold: 1
Signal assignment statement:
329: same_bits_add when (bds_trigger = '1') else Count: 26190097
Threshold: 1
Signal assignment statement:
330: same_bits_q; Count: 14931062
Threshold: 1
If statement:
337: if (res_n = '0') then
338: same_bits_q <= "001";
339: elsif (rising_edge(clk_sys)) then
340: same_bits_q <= same_bits_d;
341: end if; Count: 1055177083
Threshold: 1
Signal assignment statement:
338: same_bits_q <= "001"; Count: 2418499
Threshold: 1
Signal assignment statement:
340: same_bits_q <= same_bits_d; Count: 526374300
Threshold: 1
If statement:
351: destuffed_d <= '0' when (destuff_enable = '0') else
352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
353: '0' when (bds_trigger = '1') else
354: destuffed_q; Count: 48365622
Threshold: 1
Signal assignment statement:
351: destuffed_d <= '0' when (destuff_enable = '0') else Count: 14503801
Threshold: 1
Signal assignment statement:
352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else Count: 4068018
Threshold: 1
Signal assignment statement:
353: '0' when (bds_trigger = '1') else Count: 14850666
Threshold: 1
Signal assignment statement:
354: destuffed_q; Count: 14943137
Threshold: 1
If statement:
377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else
378: '0'; Count: 45739362
Threshold: 1
Signal assignment statement:
377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else Count: 1591210
Threshold: 1
Signal assignment statement:
378: '0'; Count: 44148152
Threshold: 1
If statement:
401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
402: data_in when (bds_trigger = '1') else
403: prev_val_q; Count: 49777937
Threshold: 1
Signal assignment statement:
401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else Count: 35362
Threshold: 1
Signal assignment statement:
402: data_in when (bds_trigger = '1') else Count: 24839928
Threshold: 1
Signal assignment statement:
403: prev_val_q; Count: 24902647
Threshold: 1
Signal assignment statement:
446: dst_ctr <= std_logic_vector(dst_ctr_q); Count: 992866
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 13466 | 1 |
| Bin | False | 45197 | 1 |
"if" / "when" / "else" condition:
222: stuff_lvl_reached <= '1' when (same_bits_q = "101") | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1008541 | 1 |
| Bin | False | 5449454 | 1 |
"if" / "when" / "else" condition:
231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1022007 | 1 |
| Bin | False | 1023578 | 1 |
"if" / "when" / "else" condition:
240: fixed_prev_d <= '0' when (enable_prev = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14482836 | 1 |
| Bin | False | 29855271 | 1 |
"if" / "when" / "else" condition:
241: fixed_stuff when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14897050 | 1 |
| Bin | False | 14958221 | 1 |
"if" / "when" / "else" condition:
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and
251: destuff_enable = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2015505 | 1 |
| Bin | False | 5717600 | 1 |
"if" / "when" / "else" condition:
284: dst_ctr_d <= "000" when (enable_prev = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14494336 | 1 |
| Bin | False | 32832483 | 1 |
"if" / "when" / "else" condition:
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and
287: fixed_stuff = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 3763116 | 1 |
| Bin | False | 29069367 | 1 |
"if" / "when" / "else" condition:
296: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2418499 | 1 |
| Bin | False | 1052758584 | 1 |
"if" / "when" / "else" condition:
298: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526374300 | 1 |
| Bin | False | 526384284 | 1 |
"if" / "when" / "else" condition:
299: if (destuff_enable = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 304002549 | 1 |
| Bin | False | 222371751 | 1 |
"if" / "when" / "else" condition:
311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14864520 | 1 |
| Bin | False | 37176833 | 1 |
"if" / "when" / "else" condition:
312: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 4042631 | 1 |
| Bin | False | 33134202 | 1 |
"if" / "when" / "else" condition:
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and
314: fixed_stuff = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2107163 | 1 |
| Bin | False | 31027039 | 1 |
"if" / "when" / "else" condition:
328: same_bits_d <= "001" when (same_bits_erase = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 23837220 | 1 |
| Bin | False | 41121159 | 1 |
"if" / "when" / "else" condition:
329: same_bits_add when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 26190097 | 1 |
| Bin | False | 14931062 | 1 |
"if" / "when" / "else" condition:
337: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2418499 | 1 |
| Bin | False | 1052758584 | 1 |
"if" / "when" / "else" condition:
339: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526374300 | 1 |
| Bin | False | 526384284 | 1 |
"if" / "when" / "else" condition:
351: destuffed_d <= '0' when (destuff_enable = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14503801 | 1 |
| Bin | False | 33861821 | 1 |
"if" / "when" / "else" condition:
352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 4068018 | 1 |
| Bin | False | 29793803 | 1 |
"if" / "when" / "else" condition:
353: '0' when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14850666 | 1 |
| Bin | False | 14943137 | 1 |
"if" / "when" / "else" condition:
377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1591210 | 1 |
| Bin | False | 44148152 | 1 |
"if" / "when" / "else" condition:
401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 35362 | 1 |
| Bin | False | 49742575 | 1 |
"if" / "when" / "else" condition:
402: data_in when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 24839928 | 1 |
| Bin | False | 24902647 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
DATA_IN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1401177 | 1 |
| Bin | 1 | 0 | 1399577 | 1 |
Port:
DATA_OUT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Port:
BDS_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22084127 | 1 |
| Bin | 1 | 0 | 22085727 | 1 |
Port:
DESTUFF_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55285 | 1 |
| Bin | 1 | 0 | 56885 | 1 |
Port:
FIXED_STUFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13466 | 1 |
| Bin | 1 | 0 | 15066 | 1 |
Port:
STUFF_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20489 | 1 |
| Bin | 1 | 0 | 22089 | 1 |
Port:
DESTUFFED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1019821 | 1 |
| Bin | 1 | 0 | 1021421 | 1 |
Port:
DST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116920 | 1 |
| Bin | 1 | 0 | 118520 | 1 |
Port:
DST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 241878 | 1 |
| Bin | 1 | 0 | 243473 | 1 |
Port:
DST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 483649 | 1 |
| Bin | 1 | 0 | 485246 | 1 |
Signal:
DISCARD_STUFF_BIT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1020378 | 1 |
| Bin | 1 | 0 | 1021978 | 1 |
Signal:
NON_FIX_TO_FIX_CHNG | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13466 | 1 |
| Bin | 1 | 0 | 15066 | 1 |
Signal:
STUFF_LVL_REACHED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1008541 | 1 |
| Bin | 1 | 0 | 1010141 | 1 |
Signal:
STUFF_RULE_VIOLATE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2015505 | 1 |
| Bin | 1 | 0 | 2017105 | 1 |
Signal:
ENABLE_PREV | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55285 | 1 |
| Bin | 1 | 0 | 56885 | 1 |
Signal:
FIXED_PREV_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13466 | 1 |
| Bin | 1 | 0 | 15065 | 1 |
Signal:
FIXED_PREV_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 39323 | 1 |
| Bin | 1 | 0 | 40923 | 1 |
Signal:
SAME_BITS_D(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5770953 | 1 |
| Bin | 1 | 0 | 5772553 | 1 |
Signal:
SAME_BITS_D(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12242514 | 1 |
| Bin | 1 | 0 | 12244114 | 1 |
Signal:
SAME_BITS_D(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18643681 | 1 |
| Bin | 1 | 0 | 18642081 | 1 |
Signal:
SAME_BITS_Q(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1100943 | 1 |
| Bin | 1 | 0 | 1102543 | 1 |
Signal:
SAME_BITS_Q(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1550498 | 1 |
| Bin | 1 | 0 | 1552098 | 1 |
Signal:
SAME_BITS_Q(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2653041 | 1 |
| Bin | 1 | 0 | 2651441 | 1 |
Signal:
SAME_BITS_ADD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1244315 | 1 |
| Bin | 1 | 0 | 1245915 | 1 |
Signal:
SAME_BITS_ADD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1245915 | 1 |
| Bin | 1 | 0 | 1244315 | 1 |
Signal:
SAME_BITS_ADD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2651441 | 1 |
| Bin | 1 | 0 | 2653041 | 1 |
Signal:
SAME_BITS_ERASE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5212197 | 1 |
| Bin | 1 | 0 | 5212197 | 1 |
Signal:
DESTUFFED_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1019821 | 1 |
| Bin | 1 | 0 | 1021421 | 1 |
Signal:
DESTUFFED_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5067344 | 1 |
| Bin | 1 | 0 | 5068944 | 1 |
Signal:
STUFF_ERR_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20489 | 1 |
| Bin | 1 | 0 | 22089 | 1 |
Signal:
STUFF_ERR_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1591210 | 1 |
| Bin | 1 | 0 | 1592810 | 1 |
Signal:
DST_CTR_Q(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116920 | 1 |
| Bin | 1 | 0 | 118520 | 1 |
Signal:
DST_CTR_Q(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 241878 | 1 |
| Bin | 1 | 0 | 243473 | 1 |
Signal:
DST_CTR_Q(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 483649 | 1 |
| Bin | 1 | 0 | 485246 | 1 |
Signal:
DST_CTR_D(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 546630 | 1 |
| Bin | 1 | 0 | 548230 | 1 |
Signal:
DST_CTR_D(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1155949 | 1 |
| Bin | 1 | 0 | 1157549 | 1 |
Signal:
DST_CTR_D(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2366229 | 1 |
| Bin | 1 | 0 | 2367829 | 1 |
Signal:
DST_CTR_ADD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124833 | 1 |
| Bin | 1 | 0 | 126432 | 1 |
Signal:
DST_CTR_ADD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 257863 | 1 |
| Bin | 1 | 0 | 259457 | 1 |
Signal:
DST_CTR_ADD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 485246 | 1 |
| Bin | 1 | 0 | 483649 | 1 |
Signal:
PREV_VAL_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1389745 | 1 |
| Bin | 1 | 0 | 1388145 | 1 |
Signal:
PREV_VAL_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2549188 | 1 |
| Bin | 1 | 0 | 2547588 | 1 |
Covered expressions:
"=" expression
208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 31731 | 1 |
| Bin | True | 26932 | 1 |
"=" expression
208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 30132 | 1 |
| Bin | True | 28531 | 1 |
"and" expression
208: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0')
<------LHS------> <------RHS-------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 15065 | 1 |
| Bin | True | False | 13466 | 1 |
| Bin | True | True | 13466 | 1 |
"=" expression
231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2032119 | 1 |
| Bin | True | 13466 | 1 |
"=" expression
231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1035415 | 1 |
| Bin | True | 1010170 | 1 |
"or" expression
231: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
<----------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 1023578 | 1 |
| Bin | False | True | 1008541 | 1 |
| Bin | True | False | 11837 | 1 |
"=" expression
240: fixed_prev_d <= '0' when (enable_prev = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 29855271 | 1 |
| Bin | True | 14482836 | 1 |
"=" expression
241: fixed_stuff when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14958221 | 1 |
| Bin | True | 14897050 | 1 |
"=" expression
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4716734 | 1 |
| Bin | True | 3016371 | 1 |
"=" expression
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2794674 | 1 |
| Bin | True | 4938431 | 1 |
"and" expression
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and
<---------LHS---------> <-------RHS--------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 2922369 | 1 |
| Bin | True | False | 1000309 | 1 |
| Bin | True | True | 2016062 | 1 |
"=" expression
251: destuff_enable = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 331353 | 1 |
| Bin | True | 7401752 | 1 |
"and" expression
250: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and
251: destuff_enable = '1') | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 5386247 | 1 |
| Bin | True | False | 557 | 1 |
| Bin | True | True | 2015505 | 1 |
"=" expression
284: dst_ctr_d <= "000" when (enable_prev = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 32832483 | 1 |
| Bin | True | 14494336 | 1 |
"=" expression
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 15004486 | 1 |
| Bin | True | 17827997 | 1 |
"=" expression
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 26849368 | 1 |
| Bin | True | 5983115 | 1 |
"and" expression
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and
<------LHS------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 2018324 | 1 |
| Bin | True | False | 13863206 | 1 |
| Bin | True | True | 3964791 | 1 |
"=" expression
287: fixed_stuff = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1582113 | 1 |
| Bin | True | 31250370 | 1 |
"and" expression
286: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and
287: fixed_stuff = '0') | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 27487254 | 1 |
| Bin | True | False | 201675 | 1 |
| Bin | True | True | 3763116 | 1 |
"=" expression
296: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052758584 | 1 |
| Bin | True | 2418499 | 1 |
"=" expression
299: if (destuff_enable = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 222371751 | 1 |
| Bin | True | 304002549 | 1 |
"=" expression
311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 37232142 | 1 |
| Bin | True | 14809211 | 1 |
"=" expression
311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 37233153 | 1 |
| Bin | True | 14808200 | 1 |
"or" expression
311: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else
<-------LHS--------> <------RHS------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 37176833 | 1 |
| Bin | False | True | 55309 | 1 |
| Bin | True | False | 56320 | 1 |
"=" expression
312: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 17629340 | 1 |
| Bin | True | 19547493 | 1 |
"=" expression
312: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 30091333 | 1 |
| Bin | True | 7085500 | 1 |
"and" expression
312: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
<------LHS------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 3042869 | 1 |
| Bin | True | False | 15504862 | 1 |
| Bin | True | True | 4042631 | 1 |
"=" expression
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 17629340 | 1 |
| Bin | True | 15504862 | 1 |
"/=" expression
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 27041703 | 1 |
| Bin | True | 6092499 | 1 |
"and" expression
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and
<------LHS------> <--------RHS--------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 3767535 | 1 |
| Bin | True | False | 13179898 | 1 |
| Bin | True | True | 2324964 | 1 |
"=" expression
314: fixed_stuff = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1744453 | 1 |
| Bin | True | 31389749 | 1 |
"and" expression
313: '1' when (bds_trigger = '1' and data_in /= prev_val_q and
314: fixed_stuff = '0') else | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 29282586 | 1 |
| Bin | True | False | 217801 | 1 |
| Bin | True | True | 2107163 | 1 |
"=" expression
328: same_bits_d <= "001" when (same_bits_erase = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 41121159 | 1 |
| Bin | True | 23837220 | 1 |
"=" expression
329: same_bits_add when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14931062 | 1 |
| Bin | True | 26190097 | 1 |
"=" expression
337: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052758584 | 1 |
| Bin | True | 2418499 | 1 |
"=" expression
351: destuffed_d <= '0' when (destuff_enable = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 33861821 | 1 |
| Bin | True | 14503801 | 1 |
"=" expression
352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14943137 | 1 |
| Bin | True | 18918684 | 1 |
"=" expression
352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 27753590 | 1 |
| Bin | True | 6108231 | 1 |
"and" expression
352: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
<------LHS------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 2040213 | 1 |
| Bin | True | False | 14850666 | 1 |
| Bin | True | True | 4068018 | 1 |
"=" expression
353: '0' when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14943137 | 1 |
| Bin | True | 14850666 | 1 |
"=" expression
377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 22660726 | 1 |
| Bin | True | 23078636 | 1 |
"=" expression
377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 42550687 | 1 |
| Bin | True | 3188675 | 1 |
"and" expression
377: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else
<------LHS------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 1597465 | 1 |
| Bin | True | False | 21487426 | 1 |
| Bin | True | True | 1591210 | 1 |
"=" expression
401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 24902647 | 1 |
| Bin | True | 24875290 | 1 |
"=" expression
401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 49702283 | 1 |
| Bin | True | 75654 | 1 |
"and" expression
401: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
<------LHS------> <----------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 40292 | 1 |
| Bin | True | False | 24839928 | 1 |
| Bin | True | True | 35362 | 1 |
"=" expression
402: data_in when (bds_trigger = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 24902647 | 1 |
| Bin | True | 24839928 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: