NVC code coverage report

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.TX_ARBITRATOR_FSM_INST	100.0 % (126/126)	100.0 % (136/136)	100.0 % (54/54)	100.0 % (141/141)	100.0 % (16/16)	N.A.	100.0 % (473/473)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 195 to 197:

195:    parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0') 
196:                            else 
197:                        '0';

Count: 284557
Threshold: 1

Signal assignment statement on line 195:

195: parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0')
Count: 3132
Threshold: 1

Signal assignment statement on line 197:

197: '0';
Count: 281425
Threshold: 1

Signal assignment statement on line 206:

206: next_state <= curr_state;
Count: 589326
Threshold: 1

Sequential statement on lines 208 to 313:

208:        case curr_state is 
209: 
...
312: 
313:        end case;

Count: 589326
Threshold: 1

If statement on lines 214 to 216:

214:            if (select_buf_avail = '1') then 
215:                next_state <= s_arb_sel_low_ts; 
216:            end if;

Count: 119662
Threshold: 1

Signal assignment statement on line 215:

215: next_state <= s_arb_sel_low_ts;
Count: 30653
Threshold: 1

If statement on lines 222 to 230:

222:            if (txtb_hw_cmd_lock = '1') then 
223:                next_state         <= s_arb_locked; 
...
229:                next_state         <= s_arb_sel_upp_ts; 
230:            end if;

Count: 72126
Threshold: 1

Signal assignment statement on line 223:

223: next_state <= s_arb_locked;
Count: 10
Threshold: 1

Signal assignment statement on line 225:

225: next_state <= s_arb_idle;
Count: 853
Threshold: 1

Signal assignment statement on line 227:

227: next_state <= s_arb_sel_low_ts;
Count: 17985
Threshold: 1

Signal assignment statement on line 229:

229: next_state <= s_arb_sel_upp_ts;
Count: 26809
Threshold: 1

If statement on lines 237 to 247:

237:            if (txtb_hw_cmd_lock = '1') then 
238:                next_state         <= s_arb_locked; 
...
246:                end if; 
247:            end if;

Count: 52768
Threshold: 1

Signal assignment statement on line 238:

238: next_state <= s_arb_locked;
Count: 10
Threshold: 1

Signal assignment statement on line 240:

240: next_state <= s_arb_idle;
Count: 159
Threshold: 1

Signal assignment statement on line 242:

242: next_state <= s_arb_sel_low_ts;
Count: 81
Threshold: 1

If statement on lines 244 to 246:

244:                if (timestamp_valid = '1') then 
245:                    next_state     <= s_arb_sel_ftw; 
246:                end if;

Count: 26318
Threshold: 1

Signal assignment statement on line 245:

245: next_state <= s_arb_sel_ftw;
Count: 26174
Threshold: 1

If statement on lines 253 to 263:

253:            if (txtb_hw_cmd_lock = '1') then 
254:                next_state         <= s_arb_locked; 
...
262:                next_state         <= s_arb_sel_ffw; 
263:            end if;

Count: 52771
Threshold: 1

Signal assignment statement on line 254:

254: next_state <= s_arb_locked;
Count: 2
Threshold: 1

Signal assignment statement on line 258:

258: next_state <= s_arb_idle;
Count: 94
Threshold: 1

Signal assignment statement on line 260:

260: next_state <= s_arb_sel_low_ts;
Count: 70
Threshold: 1

Signal assignment statement on line 262:

262: next_state <= s_arb_sel_ffw;
Count: 26589
Threshold: 1

If statement on lines 269 to 277:

269:             if (txtb_hw_cmd_lock = '1') then 
270:                next_state         <= s_arb_locked; 
...
276:                next_state         <= s_arb_sel_idw; 
277:            end if;

Count: 53804
Threshold: 1

Signal assignment statement on line 270:

270: next_state <= s_arb_locked;
Count: 2
Threshold: 1

Signal assignment statement on line 272:

272: next_state <= s_arb_idle;
Count: 1377
Threshold: 1

Signal assignment statement on line 274:

274: next_state <= s_arb_sel_low_ts;
Count: 75
Threshold: 1

Signal assignment statement on line 276:

276: next_state <= s_arb_sel_idw;
Count: 26446
Threshold: 1

If statement on lines 283 to 291:

283:             if (txtb_hw_cmd_lock = '1') then 
284:                next_state         <= s_arb_locked; 
...
290:                next_state         <= s_arb_validated; 
291:            end if;

Count: 52118
Threshold: 1

Signal assignment statement on line 284:

284: next_state <= s_arb_locked;
Count: 2
Threshold: 1

Signal assignment statement on line 286:

286: next_state <= s_arb_idle;
Count: 391
Threshold: 1

Signal assignment statement on line 288:

288: next_state <= s_arb_sel_low_ts;
Count: 62
Threshold: 1

Signal assignment statement on line 290:

290: next_state <= s_arb_validated;
Count: 25931
Threshold: 1

If statement on lines 297 to 303:

297:             if (txtb_hw_cmd_lock = '1') then 
298:                next_state         <= s_arb_locked; 
...
302:                next_state         <= s_arb_sel_low_ts; 
303:            end if;

Count: 51304
Threshold: 1

Signal assignment statement on line 298:

298: next_state <= s_arb_locked;
Count: 25292
Threshold: 1

Signal assignment statement on line 300:

300: next_state <= s_arb_idle;
Count: 209
Threshold: 1

Signal assignment statement on line 302:

302: next_state <= s_arb_sel_low_ts;
Count: 230
Threshold: 1

If statement on lines 309 to 311:

309:            if (txtb_hw_cmd_unlock = '1') then 
310:                next_state         <= s_arb_idle; 
311:            end if;

Count: 134773
Threshold: 1

Signal assignment statement on line 310:

310: next_state <= s_arb_idle;
Count: 25265
Threshold: 1

Signal assignment statement on line 325:

325: load_ts_lw_addr <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 326:

326: load_ts_uw_addr <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 327:

327: load_ffmt_w_addr <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 328:

328: load_ident_w_addr <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 329:

329: load_frame_test_w_addr <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 332:

332: txtb_meta_clk_en <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 334:

334: store_ts_l_w <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 335:

335: commit_dbl_bufs <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 336:

336: buffer_frame_test_w <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 338:

338: buffer_md_w <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 339:

339: tx_arb_locked <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 340:

340: frame_valid_com_set <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 341:

341: frame_valid_com_clear <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 342:

342: store_last_txtb_index <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 344:

344: fsm_wait_state_d <= '0';
Count: 589326
Threshold: 1

Signal assignment statement on line 346:

346: tx_arb_parity_check_valid <= '0';
Count: 589326
Threshold: 1

Sequential statement on lines 348 to 502:

348:        case curr_state is 
349: 
...
501: 
502:        end case;

Count: 589326
Threshold: 1

If statement on lines 354 to 357:

354:            if (select_buf_avail = '1') then 
355:                fsm_wait_state_d <= '1'; 
356:                load_ts_lw_addr  <= '1'; 
357:            end if;

Count: 119662
Threshold: 1

Signal assignment statement on line 355:

355: fsm_wait_state_d <= '1';
Count: 30653
Threshold: 1

Signal assignment statement on line 356:

356: load_ts_lw_addr <= '1';
Count: 30653
Threshold: 1

Signal assignment statement on line 363:

363: txtb_meta_clk_en <= '1';
Count: 72126
Threshold: 1

If statement on lines 365 to 380:

365:            if (txtb_hw_cmd_lock = '1') then 
366:                store_last_txtb_index <= '1'; 
...
379:                tx_arb_parity_check_valid <= '1'; 
380:            end if;

Count: 72126
Threshold: 1

Signal assignment statement on line 366:

366: store_last_txtb_index <= '1';
Count: 10
Threshold: 1

Signal assignment statement on line 369:

369: frame_valid_com_clear <= '1';
Count: 193
Threshold: 1

Signal assignment statement on line 372:

372: fsm_wait_state_d <= '1';
Count: 18164
Threshold: 1

Signal assignment statement on line 373:

373: load_ts_lw_addr <= '1';
Count: 18164
Threshold: 1

Signal assignment statement on line 376:

376: fsm_wait_state_d <= '1';
Count: 27270
Threshold: 1

Signal assignment statement on line 377:

377: load_ts_uw_addr <= '1';
Count: 27270
Threshold: 1

Signal assignment statement on line 378:

378: store_ts_l_w <= '1';
Count: 27270
Threshold: 1

Signal assignment statement on line 379:

379: tx_arb_parity_check_valid <= '1';
Count: 27270
Threshold: 1

Signal assignment statement on line 387:

387: txtb_meta_clk_en <= '1';
Count: 52768
Threshold: 1

If statement on lines 389 to 405:

389:            if (txtb_hw_cmd_lock = '1') then 
390:                store_last_txtb_index <= '1'; 
...
404:                tx_arb_parity_check_valid <= '1'; 
405:            end if;

Count: 52768
Threshold: 1

Signal assignment statement on line 390:

390: store_last_txtb_index <= '1';
Count: 10
Threshold: 1

Signal assignment statement on line 393:

393: frame_valid_com_clear <= '1';
Count: 117
Threshold: 1

Signal assignment statement on line 396:

396: fsm_wait_state_d <= '1';
Count: 81
Threshold: 1

Signal assignment statement on line 397:

397: load_ts_lw_addr <= '1';
Count: 81
Threshold: 1

If statement on lines 400 to 403:

400:                if (timestamp_valid = '1') then 
401:                    fsm_wait_state_d       <= '1'; 
402:                    load_frame_test_w_addr <= '1'; 
403:                end if;

Count: 26360
Threshold: 1

Signal assignment statement on line 401:

401: fsm_wait_state_d <= '1';
Count: 26216
Threshold: 1

Signal assignment statement on line 402:

402: load_frame_test_w_addr <= '1';
Count: 26216
Threshold: 1

Signal assignment statement on line 404:

404: tx_arb_parity_check_valid <= '1';
Count: 26360
Threshold: 1

Signal assignment statement on line 411:

411: txtb_meta_clk_en <= '1';
Count: 52771
Threshold: 1

If statement on lines 413 to 427:

413:            if (txtb_hw_cmd_lock = '1') then 
414:                store_last_txtb_index <= '1'; 
...
426:                load_ffmt_w_addr <= '1'; 
427:            end if;

Count: 52771
Threshold: 1

Signal assignment statement on line 414:

414: store_last_txtb_index <= '1';
Count: 2
Threshold: 1

Signal assignment statement on line 417:

417: frame_valid_com_clear <= '1';
Count: 94
Threshold: 1

Signal assignment statement on line 420:

420: fsm_wait_state_d <= '1';
Count: 70
Threshold: 1

Signal assignment statement on line 421:

421: load_ts_lw_addr <= '1';
Count: 70
Threshold: 1

Signal assignment statement on line 424:

424: fsm_wait_state_d <= '1';
Count: 26589
Threshold: 1

Signal assignment statement on line 425:

425: buffer_frame_test_w <= '1';
Count: 26589
Threshold: 1

Signal assignment statement on line 426:

426: load_ffmt_w_addr <= '1';
Count: 26589
Threshold: 1

Signal assignment statement on line 433:

433: txtb_meta_clk_en <= '1';
Count: 53804
Threshold: 1

If statement on lines 435 to 450:

435:            if (txtb_hw_cmd_lock = '1') then 
436:                store_last_txtb_index <= '1'; 
...
449:                tx_arb_parity_check_valid <= '1'; 
450:            end if;

Count: 53804
Threshold: 1

Signal assignment statement on line 436:

436: store_last_txtb_index <= '1';
Count: 2
Threshold: 1

Signal assignment statement on line 439:

439: frame_valid_com_clear <= '1';
Count: 94
Threshold: 1

Signal assignment statement on line 442:

442: fsm_wait_state_d <= '1';
Count: 75
Threshold: 1

Signal assignment statement on line 443:

443: load_ts_lw_addr <= '1';
Count: 75
Threshold: 1

Signal assignment statement on line 446:

446: fsm_wait_state_d <= '1';
Count: 27100
Threshold: 1

Signal assignment statement on line 447:

447: load_ident_w_addr <= '1';
Count: 27100
Threshold: 1

Signal assignment statement on line 448:

448: buffer_md_w <= '1';
Count: 27100
Threshold: 1

Signal assignment statement on line 449:

449: tx_arb_parity_check_valid <= '1';
Count: 27100
Threshold: 1

Signal assignment statement on line 456:

456: txtb_meta_clk_en <= '1';
Count: 52118
Threshold: 1

If statement on lines 458 to 475:

458:            if (txtb_hw_cmd_lock = '1') then 
459:                store_last_txtb_index <= '1'; 
...
474:                tx_arb_parity_check_valid <= '1'; 
475:            end if;

Count: 52118
Threshold: 1

Signal assignment statement on line 459:

459: store_last_txtb_index <= '1';
Count: 2
Threshold: 1

Signal assignment statement on line 462:

462: frame_valid_com_clear <= '1';
Count: 75
Threshold: 1

Signal assignment statement on line 465:

465: fsm_wait_state_d <= '1';
Count: 62
Threshold: 1

Signal assignment statement on line 466:

466: load_ts_lw_addr <= '1';
Count: 62
Threshold: 1

If statement on lines 469 to 472:

469:                if (parity_error_vld = '0') then 
470:                    commit_dbl_bufs     <= '1'; 
471:                    frame_valid_com_set <= '1'; 
472:                end if;

Count: 26247
Threshold: 1

Signal assignment statement on line 470:

470: commit_dbl_bufs <= '1';
Count: 25931
Threshold: 1

Signal assignment statement on line 471:

471: frame_valid_com_set <= '1';
Count: 25931
Threshold: 1

Signal assignment statement on line 474:

474: tx_arb_parity_check_valid <= '1';
Count: 26247
Threshold: 1

If statement on lines 481 to 490:

481:            if (txtb_hw_cmd_lock = '1') then 
482:                store_last_txtb_index <= '1'; 
...
489:                load_ts_lw_addr     <= '1'; 
490:            end if;

Count: 51304
Threshold: 1

Signal assignment statement on line 482:

482: store_last_txtb_index <= '1';
Count: 25292
Threshold: 1

Signal assignment statement on line 485:

485: frame_valid_com_clear <= '1';
Count: 209
Threshold: 1

Signal assignment statement on line 488:

488: fsm_wait_state_d <= '1';
Count: 230
Threshold: 1

Signal assignment statement on line 489:

489: load_ts_lw_addr <= '1';
Count: 230
Threshold: 1

Signal assignment statement on line 496:

496: tx_arb_locked <= '1';
Count: 134773
Threshold: 1

If statement on lines 498 to 500:

498:            if (txtb_hw_cmd_unlock = '1') then 
499:                frame_valid_com_clear <= '1'; 
500:            end if;

Count: 134773
Threshold: 1

Signal assignment statement on line 499:

499: frame_valid_com_clear <= '1';
Count: 25265
Threshold: 1

If statement on lines 511 to 517:

511:        if (res_n = '0') then 
512:            curr_state <= s_arb_idle; 
...
516:            end if; 
517:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 512:

512: curr_state <= s_arb_idle;
Count: 2424883
Threshold: 1

If statement on lines 514 to 516:

514:            if (tx_arb_fsm_ce = '1') then 
515:                curr_state <= next_state; 
516:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 515:

515: curr_state <= next_state;
Count: 207400
Threshold: 1

If statement on lines 521 to 522:

521:    tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else 
522:                     '0';

Count: 425325
Threshold: 1

Signal assignment statement on line 521:

521: tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else
Count: 213526
Threshold: 1

Signal assignment statement on line 522:

522: '0';
Count: 211799
Threshold: 1

If statement on lines 530 to 534:

530:        if (res_n = '0') then 
531:            fsm_wait_state_q <= '1'; 
532:        elsif (rising_edge(clk_sys)) then 
533:            fsm_wait_state_q <= fsm_wait_state_d; 
534:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 531:

531: fsm_wait_state_q <= '1';
Count: 2424883
Threshold: 1

Signal assignment statement on line 533:

533: fsm_wait_state_q <= fsm_wait_state_d;
Count: 543791678
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 195:

195: parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0')

	Evaluated to	Count	Threshold
Bin	True	3132	1
Bin	False	281425	1

"case" / "with" / "select" choice on line 213:

213: when s_arb_idle =>

	Choice of	Count	Threshold
Bin	`s_arb_idle`	119662	1

"if" / "when" / "else" condition on line 214:

214: if (select_buf_avail = '1') then

	Evaluated to	Count	Threshold
Bin	True	30653	1
Bin	False	89009	1

"case" / "with" / "select" choice on line 221:

221: when s_arb_sel_low_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_low_ts`	72126	1

"if" / "when" / "else" condition on line 222:

222: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	72116	1

"if" / "when" / "else" condition on line 224:

224: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	853	1
Bin	False	71263	1

"if" / "when" / "else" condition on line 226:

226: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	17985	1
Bin	False	53278	1

"if" / "when" / "else" condition on line 228:

228: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26809	1
Bin	False	26469	1

"case" / "with" / "select" choice on line 236:

236: when s_arb_sel_upp_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_upp_ts`	52768	1

"if" / "when" / "else" condition on line 237:

237: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	52758	1

"if" / "when" / "else" condition on line 239:

239: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	159	1
Bin	False	52599	1

"if" / "when" / "else" condition on line 241:

241: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	81	1
Bin	False	52518	1

"if" / "when" / "else" condition on line 243:

243: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26318	1
Bin	False	26200	1

"if" / "when" / "else" condition on line 244:

244: if (timestamp_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	26174	1
Bin	False	144	1

"case" / "with" / "select" choice on line 252:

252: when s_arb_sel_ftw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ftw`	52771	1

"if" / "when" / "else" condition on line 253:

253: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	52769	1

"if" / "when" / "else" condition on line 257:

257: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	94	1
Bin	False	52675	1

"if" / "when" / "else" condition on line 259:

259: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	70	1
Bin	False	52605	1

"if" / "when" / "else" condition on line 261:

261: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26589	1
Bin	False	26016	1

"case" / "with" / "select" choice on line 268:

268: when s_arb_sel_ffw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ffw`	53804	1

"if" / "when" / "else" condition on line 269:

269: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	53802	1

"if" / "when" / "else" condition on line 271:

271: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	1377	1
Bin	False	52425	1

"if" / "when" / "else" condition on line 273:

273: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	75	1
Bin	False	52350	1

"if" / "when" / "else" condition on line 275:

275: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26446	1
Bin	False	25904	1

"case" / "with" / "select" choice on line 282:

282: when s_arb_sel_idw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_idw`	52118	1

"if" / "when" / "else" condition on line 283:

283: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	52116	1

"if" / "when" / "else" condition on line 285:

285: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	391	1
Bin	False	51725	1

"if" / "when" / "else" condition on line 287:

287: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	62	1
Bin	False	51663	1

"if" / "when" / "else" condition on line 289:

289: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	25931	1
Bin	False	25732	1

"case" / "with" / "select" choice on line 296:

296: when s_arb_validated =>

	Choice of	Count	Threshold
Bin	`s_arb_validated`	51304	1

"if" / "when" / "else" condition on line 297:

297: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	25292	1
Bin	False	26012	1

"if" / "when" / "else" condition on line 299:

299: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	209	1
Bin	False	25803	1

"if" / "when" / "else" condition on line 301:

301: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	230	1
Bin	False	25573	1

"case" / "with" / "select" choice on line 308:

308: when s_arb_locked =>

	Choice of	Count	Threshold
Bin	`s_arb_locked`	134773	1

"if" / "when" / "else" condition on line 309:

309: if (txtb_hw_cmd_unlock = '1') then

	Evaluated to	Count	Threshold
Bin	True	25265	1
Bin	False	109508	1

"case" / "with" / "select" choice on line 353:

353: when s_arb_idle =>

	Choice of	Count	Threshold
Bin	`s_arb_idle`	119662	1

"if" / "when" / "else" condition on line 354:

354: if (select_buf_avail = '1') then

	Evaluated to	Count	Threshold
Bin	True	30653	1
Bin	False	89009	1

"case" / "with" / "select" choice on line 362:

362: when s_arb_sel_low_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_low_ts`	72126	1

"if" / "when" / "else" condition on line 365:

365: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	72116	1

"if" / "when" / "else" condition on line 368:

368: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	193	1
Bin	False	71923	1

"if" / "when" / "else" condition on line 371:

371: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	18164	1
Bin	False	53759	1

"if" / "when" / "else" condition on line 375:

375: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	27270	1
Bin	False	26489	1

"case" / "with" / "select" choice on line 386:

386: when s_arb_sel_upp_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_upp_ts`	52768	1

"if" / "when" / "else" condition on line 389:

389: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	52758	1

"if" / "when" / "else" condition on line 392:

392: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	117	1
Bin	False	52641	1

"if" / "when" / "else" condition on line 395:

395: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	81	1
Bin	False	52560	1

"if" / "when" / "else" condition on line 399:

399: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26360	1
Bin	False	26200	1

"if" / "when" / "else" condition on line 400:

400: if (timestamp_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	26216	1
Bin	False	144	1

"case" / "with" / "select" choice on line 410:

410: when s_arb_sel_ftw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ftw`	52771	1

"if" / "when" / "else" condition on line 413:

413: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	52769	1

"if" / "when" / "else" condition on line 416:

416: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	94	1
Bin	False	52675	1

"if" / "when" / "else" condition on line 419:

419: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	70	1
Bin	False	52605	1

"if" / "when" / "else" condition on line 423:

423: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26589	1
Bin	False	26016	1

"case" / "with" / "select" choice on line 432:

432: when s_arb_sel_ffw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ffw`	53804	1

"if" / "when" / "else" condition on line 435:

435: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	53802	1

"if" / "when" / "else" condition on line 438:

438: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	94	1
Bin	False	53708	1

"if" / "when" / "else" condition on line 441:

441: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	75	1
Bin	False	53633	1

"if" / "when" / "else" condition on line 445:

445: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	27100	1
Bin	False	26533	1

"case" / "with" / "select" choice on line 455:

455: when s_arb_sel_idw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_idw`	52118	1

"if" / "when" / "else" condition on line 458:

458: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	52116	1

"if" / "when" / "else" condition on line 461:

461: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	75	1
Bin	False	52041	1

"if" / "when" / "else" condition on line 464:

464: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	62	1
Bin	False	51979	1

"if" / "when" / "else" condition on line 468:

468: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26247	1
Bin	False	25732	1

"if" / "when" / "else" condition on line 469:

469: if (parity_error_vld = '0') then

	Evaluated to	Count	Threshold
Bin	True	25931	1
Bin	False	316	1

"case" / "with" / "select" choice on line 480:

480: when s_arb_validated =>

	Choice of	Count	Threshold
Bin	`s_arb_validated`	51304	1

"if" / "when" / "else" condition on line 481:

481: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	25292	1
Bin	False	26012	1

"if" / "when" / "else" condition on line 484:

484: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	209	1
Bin	False	25803	1

"if" / "when" / "else" condition on line 487:

487: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	230	1
Bin	False	25573	1

"case" / "with" / "select" choice on line 495:

495: when s_arb_locked =>

	Choice of	Count	Threshold
Bin	`s_arb_locked`	134773	1

"if" / "when" / "else" condition on line 498:

498: if (txtb_hw_cmd_unlock = '1') then

	Evaluated to	Count	Threshold
Bin	True	25265	1
Bin	False	109508	1

"if" / "when" / "else" condition on line 511:

511: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 513:

513: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 514:

514: if (tx_arb_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	207400	1
Bin	False	543584278	1

"if" / "when" / "else" condition on line 521:

521: tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else

	Evaluated to	Count	Threshold
Bin	True	213526	1
Bin	False	211799	1

"if" / "when" / "else" condition on line 530:

530: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 532:

532: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SELECT_BUF_AVAIL

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SELECT_INDEX_CHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TIMESTAMP_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_LOCK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_UNLOCK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_MISMATCH_VLD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

LOAD_TS_LW_ADDR

	From	To	Count	Threshold
Bin	0	1	28775	1
Bin	1	0	30376	1

Port:

LOAD_TS_UW_ADDR

	From	To	Count	Threshold
Bin	0	1	26350	1
Bin	1	0	27951	1

Port:

LOAD_FFMT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25960	1
Bin	1	0	27561	1

Port:

LOAD_IDENT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25847	1
Bin	1	0	27448	1

Port:

LOAD_FRAME_TEST_W_ADDR

	From	To	Count	Threshold
Bin	0	1	26174	1
Bin	1	0	27775	1

Port:

TXTB_META_CLK_EN

	From	To	Count	Threshold
Bin	0	1	26372	1
Bin	1	0	27973	1

Port:

STORE_TS_L_W

	From	To	Count	Threshold
Bin	0	1	26350	1
Bin	1	0	27951	1

Port:

COMMIT_DBL_BUFS

	From	To	Count	Threshold
Bin	0	1	25922	1
Bin	1	0	27523	1

Port:

BUFFER_FRAME_TEST_W

	From	To	Count	Threshold
Bin	0	1	25960	1
Bin	1	0	27561	1

Port:

BUFFER_MD_W

	From	To	Count	Threshold
Bin	0	1	25847	1
Bin	1	0	27448	1

Port:

TX_ARB_LOCKED

	From	To	Count	Threshold
Bin	0	1	25275	1
Bin	1	0	26876	1

Port:

STORE_LAST_TXTB_INDEX

	From	To	Count	Threshold
Bin	0	1	25275	1
Bin	1	0	26876	1

Port:

FRAME_VALID_COM_SET

	From	To	Count	Threshold
Bin	0	1	25922	1
Bin	1	0	27523	1

Port:

FRAME_VALID_COM_CLEAR

	From	To	Count	Threshold
Bin	0	1	26018	1
Bin	1	0	27619	1

Port:

TX_ARB_PARITY_CHECK_VALID

	From	To	Count	Threshold
Bin	0	1	103989	1
Bin	1	0	105590	1

Signal:

TX_ARB_FSM_CE

	From	To	Count	Threshold
Bin	0	1	210198	1
Bin	1	0	211799	1

Signal:

FSM_WAIT_STATE_D

	From	To	Count	Threshold
Bin	0	1	132786	1
Bin	1	0	134387	1

Signal:

FSM_WAIT_STATE_Q

	From	To	Count	Threshold
Bin	0	1	138411	1
Bin	1	0	138422	1

Signal:

PARITY_ERROR_VLD

	From	To	Count	Threshold
Bin	0	1	3132	1
Bin	1	0	4733	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 195:

 txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0' 
 <------------LHS------------->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	139648	1
Bin	True	False	1035	1
Bin	True	True	3132	1

"=" expression on line 195:

txtb_parity_mismatch_vld = '1'

	Evaluated to	Count	Threshold
Bin	False	280390	1
Bin	True	4167	1

"=" expression on line 195:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	141777	1
Bin	True	142780	1

"=" expression on line 214:

select_buf_avail = '1'

	Evaluated to	Count	Threshold
Bin	False	89009	1
Bin	True	30653	1

"=" expression on line 222:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	72116	1
Bin	True	10	1

"or" expression on line 224:

 select_buf_avail = '0' or parity_error_vld = '1' 
 <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	71263	1
Bin	False	True	660	1
Bin	True	False	193	1

"=" expression on line 224:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	71923	1
Bin	True	193	1

"=" expression on line 224:

parity_error_vld = '1'

	Evaluated to	Count	Threshold
Bin	False	71456	1
Bin	True	660	1

"=" expression on line 226:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	53278	1
Bin	True	17985	1

"=" expression on line 228:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26469	1
Bin	True	26809	1

"=" expression on line 237:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	52758	1
Bin	True	10	1

"or" expression on line 239:

 select_buf_avail = '0' or parity_error_vld = '1' 
 <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	52599	1
Bin	False	True	42	1
Bin	True	False	117	1

"=" expression on line 239:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	52641	1
Bin	True	117	1

"=" expression on line 239:

parity_error_vld = '1'

	Evaluated to	Count	Threshold
Bin	False	52716	1
Bin	True	42	1

"=" expression on line 241:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	52518	1
Bin	True	81	1

"=" expression on line 243:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26200	1
Bin	True	26318	1

"=" expression on line 244:

timestamp_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	144	1
Bin	True	26174	1

"=" expression on line 253:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	52769	1
Bin	True	2	1

"=" expression on line 257:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	52675	1
Bin	True	94	1

"=" expression on line 259:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	52605	1
Bin	True	70	1

"=" expression on line 261:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26016	1
Bin	True	26589	1

"=" expression on line 269:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	53802	1
Bin	True	2	1

"or" expression on line 271:

 select_buf_avail = '0' or parity_error_vld = '1' 
 <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	52425	1
Bin	False	True	1283	1
Bin	True	False	94	1

"=" expression on line 271:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	53708	1
Bin	True	94	1

"=" expression on line 271:

parity_error_vld = '1'

	Evaluated to	Count	Threshold
Bin	False	52519	1
Bin	True	1283	1

"=" expression on line 273:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	52350	1
Bin	True	75	1

"=" expression on line 275:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	25904	1
Bin	True	26446	1

"=" expression on line 283:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	52116	1
Bin	True	2	1

"or" expression on line 285:

 select_buf_avail = '0' or parity_error_vld = '1' 
 <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	51725	1
Bin	False	True	316	1
Bin	True	False	75	1

"=" expression on line 285:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	52041	1
Bin	True	75	1

"=" expression on line 285:

parity_error_vld = '1'

	Evaluated to	Count	Threshold
Bin	False	51800	1
Bin	True	316	1

"=" expression on line 287:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	51663	1
Bin	True	62	1

"=" expression on line 289:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	25732	1
Bin	True	25931	1

"=" expression on line 297:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	26012	1
Bin	True	25292	1

"=" expression on line 299:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	25803	1
Bin	True	209	1

"=" expression on line 301:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	25573	1
Bin	True	230	1

"=" expression on line 309:

txtb_hw_cmd_unlock = '1'

	Evaluated to	Count	Threshold
Bin	False	109508	1
Bin	True	25265	1

"=" expression on line 354:

select_buf_avail = '1'

	Evaluated to	Count	Threshold
Bin	False	89009	1
Bin	True	30653	1

"=" expression on line 365:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	72116	1
Bin	True	10	1

"=" expression on line 368:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	71923	1
Bin	True	193	1

"=" expression on line 371:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	53759	1
Bin	True	18164	1

"=" expression on line 375:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26489	1
Bin	True	27270	1

"=" expression on line 389:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	52758	1
Bin	True	10	1

"=" expression on line 392:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	52641	1
Bin	True	117	1

"=" expression on line 395:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	52560	1
Bin	True	81	1

"=" expression on line 399:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26200	1
Bin	True	26360	1

"=" expression on line 400:

timestamp_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	144	1
Bin	True	26216	1

"=" expression on line 413:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	52769	1
Bin	True	2	1

"=" expression on line 416:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	52675	1
Bin	True	94	1

"=" expression on line 419:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	52605	1
Bin	True	70	1

"=" expression on line 423:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26016	1
Bin	True	26589	1

"=" expression on line 435:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	53802	1
Bin	True	2	1

"=" expression on line 438:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	53708	1
Bin	True	94	1

"=" expression on line 441:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	53633	1
Bin	True	75	1

"=" expression on line 445:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	26533	1
Bin	True	27100	1

"=" expression on line 458:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	52116	1
Bin	True	2	1

"=" expression on line 461:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	52041	1
Bin	True	75	1

"=" expression on line 464:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	51979	1
Bin	True	62	1

"=" expression on line 468:

fsm_wait_state_q = '0'

	Evaluated to	Count	Threshold
Bin	False	25732	1
Bin	True	26247	1

"=" expression on line 469:

parity_error_vld = '0'

	Evaluated to	Count	Threshold
Bin	False	316	1
Bin	True	25931	1

"=" expression on line 481:

txtb_hw_cmd_lock = '1'

	Evaluated to	Count	Threshold
Bin	False	26012	1
Bin	True	25292	1

"=" expression on line 484:

select_buf_avail = '0'

	Evaluated to	Count	Threshold
Bin	False	25803	1
Bin	True	209	1

"=" expression on line 487:

select_index_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	25573	1
Bin	True	230	1

"=" expression on line 498:

txtb_hw_cmd_unlock = '1'

	Evaluated to	Count	Threshold
Bin	False	109508	1
Bin	True	25265	1

"=" expression on line 511:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 514:

tx_arb_fsm_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543584278	1
Bin	True	207400	1

"/=" expression on line 521:

curr_state /= next_state

	Evaluated to	Count	Threshold
Bin	False	211799	1
Bin	True	213526	1

"=" expression on line 530:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

"T_TX_ARB_STATE" FSM on line 182:

182: signal curr_state : t_tx_arb_state;

	State	Count	Threshold
Bin	S_ARB_IDLE	27882	1
Bin	S_ARB_SEL_LOW_TS	26459	1
Bin	S_ARB_SEL_UPP_TS	26200	1
Bin	S_ARB_SEL_FFW	25904	1
Bin	S_ARB_SEL_IDW	25732	1
Bin	S_ARB_SEL_FTW	26016	1
Bin	S_ARB_VALIDATED	25568	1
Bin	S_ARB_LOCKED	25275	1

"T_TX_ARB_STATE" FSM on line 183:

183: signal next_state : t_tx_arb_state;

	State	Count	Threshold
Bin	S_ARB_IDLE	31778	1
Bin	S_ARB_SEL_LOW_TS	28897	1
Bin	S_ARB_SEL_UPP_TS	26804	1
Bin	S_ARB_SEL_FFW	26589	1
Bin	S_ARB_SEL_IDW	26446	1
Bin	S_ARB_SEL_FTW	26174	1
Bin	S_ARB_VALIDATED	25927	1
Bin	S_ARB_LOCKED	25275	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.TX_ARBITRATOR_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

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