NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.TX_ARBITRATOR_FSM_INST	100.0 % (126/126)	100.0 % (136/136)	100.0 % (54/54)	100.0 % (141/141)	100.0 % (16/16)	N.A.	100.0 % (473/473)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

195:    parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0') 
196:                            else 
197:                        '0';

Count: 279971
Threshold: 1

Signal assignment statement:

195: parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0')
Count: 3104
Threshold: 1

Signal assignment statement:

197: '0';
Count: 276867
Threshold: 1

Signal assignment statement:

206: next_state <= curr_state;
Count: 579438
Threshold: 1

Sequential statement:

208:        case curr_state is 
209: 
...
312: 
313:        end case;

Count: 579438
Threshold: 1

If statement:

214:            if (select_buf_avail = '1') then 
215:                next_state <= s_arb_sel_low_ts; 
216:            end if;

Count: 118299
Threshold: 1

Signal assignment statement:

215: next_state <= s_arb_sel_low_ts;
Count: 30098
Threshold: 1

If statement:

222:            if (txtb_hw_cmd_lock = '1') then 
223:                next_state         <= s_arb_locked; 
...
229:                next_state         <= s_arb_sel_upp_ts; 
230:            end if;

Count: 70790
Threshold: 1

Signal assignment statement:

223: next_state <= s_arb_locked;
Count: 10
Threshold: 1

Signal assignment statement:

225: next_state <= s_arb_idle;
Count: 857
Threshold: 1

Signal assignment statement:

227: next_state <= s_arb_sel_low_ts;
Count: 17570
Threshold: 1

Signal assignment statement:

229: next_state <= s_arb_sel_upp_ts;
Count: 26340
Threshold: 1

If statement:

237:            if (txtb_hw_cmd_lock = '1') then 
238:                next_state         <= s_arb_locked; 
...
246:                end if; 
247:            end if;

Count: 51833
Threshold: 1

Signal assignment statement:

238: next_state <= s_arb_locked;
Count: 10
Threshold: 1

Signal assignment statement:

240: next_state <= s_arb_idle;
Count: 150
Threshold: 1

Signal assignment statement:

242: next_state <= s_arb_sel_low_ts;
Count: 81
Threshold: 1

If statement:

244:                if (timestamp_valid = '1') then 
245:                    next_state     <= s_arb_sel_ftw; 
246:                end if;

Count: 25855
Threshold: 1

Signal assignment statement:

245: next_state <= s_arb_sel_ftw;
Count: 25721
Threshold: 1

If statement:

253:            if (txtb_hw_cmd_lock = '1') then 
254:                next_state         <= s_arb_locked; 
...
262:                next_state         <= s_arb_sel_ffw; 
263:            end if;

Count: 51853
Threshold: 1

Signal assignment statement:

254: next_state <= s_arb_locked;
Count: 2
Threshold: 1

Signal assignment statement:

258: next_state <= s_arb_idle;
Count: 94
Threshold: 1

Signal assignment statement:

260: next_state <= s_arb_sel_low_ts;
Count: 71
Threshold: 1

Signal assignment statement:

262: next_state <= s_arb_sel_ffw;
Count: 26124
Threshold: 1

If statement:

269:             if (txtb_hw_cmd_lock = '1') then 
270:                next_state         <= s_arb_locked; 
...
276:                next_state         <= s_arb_sel_idw; 
277:            end if;

Count: 52868
Threshold: 1

Signal assignment statement:

270: next_state <= s_arb_locked;
Count: 2
Threshold: 1

Signal assignment statement:

272: next_state <= s_arb_idle;
Count: 1354
Threshold: 1

Signal assignment statement:

274: next_state <= s_arb_sel_low_ts;
Count: 73
Threshold: 1

Signal assignment statement:

276: next_state <= s_arb_sel_idw;
Count: 25990
Threshold: 1

If statement:

283:             if (txtb_hw_cmd_lock = '1') then 
284:                next_state         <= s_arb_locked; 
...
290:                next_state         <= s_arb_validated; 
291:            end if;

Count: 51251
Threshold: 1

Signal assignment statement:

284: next_state <= s_arb_locked;
Count: 2
Threshold: 1

Signal assignment statement:

286: next_state <= s_arb_idle;
Count: 408
Threshold: 1

Signal assignment statement:

288: next_state <= s_arb_sel_low_ts;
Count: 66
Threshold: 1

Signal assignment statement:

290: next_state <= s_arb_validated;
Count: 25485
Threshold: 1

If statement:

297:             if (txtb_hw_cmd_lock = '1') then 
298:                next_state         <= s_arb_locked; 
...
302:                next_state         <= s_arb_sel_low_ts; 
303:            end if;

Count: 50385
Threshold: 1

Signal assignment statement:

298: next_state <= s_arb_locked;
Count: 24831
Threshold: 1

Signal assignment statement:

300: next_state <= s_arb_idle;
Count: 207
Threshold: 1

Signal assignment statement:

302: next_state <= s_arb_sel_low_ts;
Count: 233
Threshold: 1

If statement:

309:            if (txtb_hw_cmd_unlock = '1') then 
310:                next_state         <= s_arb_idle; 
311:            end if;

Count: 132159
Threshold: 1

Signal assignment statement:

310: next_state <= s_arb_idle;
Count: 24805
Threshold: 1

Signal assignment statement:

325: load_ts_lw_addr <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

326: load_ts_uw_addr <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

327: load_ffmt_w_addr <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

328: load_ident_w_addr <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

329: load_frame_test_w_addr <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

332: txtb_meta_clk_en <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

334: store_ts_l_w <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

335: commit_dbl_bufs <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

336: buffer_frame_test_w <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

338: buffer_md_w <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

339: tx_arb_locked <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

340: frame_valid_com_set <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

341: frame_valid_com_clear <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

342: store_last_txtb_index <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

344: fsm_wait_state_d <= '0';
Count: 579438
Threshold: 1

Signal assignment statement:

346: tx_arb_parity_check_valid <= '0';
Count: 579438
Threshold: 1

Sequential statement:

348:        case curr_state is 
349: 
...
501: 
502:        end case;

Count: 579438
Threshold: 1

If statement:

354:            if (select_buf_avail = '1') then 
355:                fsm_wait_state_d <= '1'; 
356:                load_ts_lw_addr  <= '1'; 
357:            end if;

Count: 118299
Threshold: 1

Signal assignment statement:

355: fsm_wait_state_d <= '1';
Count: 30098
Threshold: 1

Signal assignment statement:

356: load_ts_lw_addr <= '1';
Count: 30098
Threshold: 1

Signal assignment statement:

363: txtb_meta_clk_en <= '1';
Count: 70790
Threshold: 1

If statement:

365:            if (txtb_hw_cmd_lock = '1') then 
366:                store_last_txtb_index <= '1'; 
...
379:                tx_arb_parity_check_valid <= '1'; 
380:            end if;

Count: 70790
Threshold: 1

Signal assignment statement:

366: store_last_txtb_index <= '1';
Count: 10
Threshold: 1

Signal assignment statement:

369: frame_valid_com_clear <= '1';
Count: 193
Threshold: 1

Signal assignment statement:

372: fsm_wait_state_d <= '1';
Count: 17751
Threshold: 1

Signal assignment statement:

373: load_ts_lw_addr <= '1';
Count: 17751
Threshold: 1

Signal assignment statement:

376: fsm_wait_state_d <= '1';
Count: 26806
Threshold: 1

Signal assignment statement:

377: load_ts_uw_addr <= '1';
Count: 26806
Threshold: 1

Signal assignment statement:

378: store_ts_l_w <= '1';
Count: 26806
Threshold: 1

Signal assignment statement:

379: tx_arb_parity_check_valid <= '1';
Count: 26806
Threshold: 1

Signal assignment statement:

387: txtb_meta_clk_en <= '1';
Count: 51833
Threshold: 1

If statement:

389:            if (txtb_hw_cmd_lock = '1') then 
390:                store_last_txtb_index <= '1'; 
...
404:                tx_arb_parity_check_valid <= '1'; 
405:            end if;

Count: 51833
Threshold: 1

Signal assignment statement:

390: store_last_txtb_index <= '1';
Count: 10
Threshold: 1

Signal assignment statement:

393: frame_valid_com_clear <= '1';
Count: 117
Threshold: 1

Signal assignment statement:

396: fsm_wait_state_d <= '1';
Count: 81
Threshold: 1

Signal assignment statement:

397: load_ts_lw_addr <= '1';
Count: 81
Threshold: 1

If statement:

400:                if (timestamp_valid = '1') then 
401:                    fsm_wait_state_d       <= '1'; 
402:                    load_frame_test_w_addr <= '1'; 
403:                end if;

Count: 25888
Threshold: 1

Signal assignment statement:

401: fsm_wait_state_d <= '1';
Count: 25754
Threshold: 1

Signal assignment statement:

402: load_frame_test_w_addr <= '1';
Count: 25754
Threshold: 1

Signal assignment statement:

404: tx_arb_parity_check_valid <= '1';
Count: 25888
Threshold: 1

Signal assignment statement:

411: txtb_meta_clk_en <= '1';
Count: 51853
Threshold: 1

If statement:

413:            if (txtb_hw_cmd_lock = '1') then 
414:                store_last_txtb_index <= '1'; 
...
426:                load_ffmt_w_addr <= '1'; 
427:            end if;

Count: 51853
Threshold: 1

Signal assignment statement:

414: store_last_txtb_index <= '1';
Count: 2
Threshold: 1

Signal assignment statement:

417: frame_valid_com_clear <= '1';
Count: 94
Threshold: 1

Signal assignment statement:

420: fsm_wait_state_d <= '1';
Count: 71
Threshold: 1

Signal assignment statement:

421: load_ts_lw_addr <= '1';
Count: 71
Threshold: 1

Signal assignment statement:

424: fsm_wait_state_d <= '1';
Count: 26124
Threshold: 1

Signal assignment statement:

425: buffer_frame_test_w <= '1';
Count: 26124
Threshold: 1

Signal assignment statement:

426: load_ffmt_w_addr <= '1';
Count: 26124
Threshold: 1

Signal assignment statement:

433: txtb_meta_clk_en <= '1';
Count: 52868
Threshold: 1

If statement:

435:            if (txtb_hw_cmd_lock = '1') then 
436:                store_last_txtb_index <= '1'; 
...
449:                tx_arb_parity_check_valid <= '1'; 
450:            end if;

Count: 52868
Threshold: 1

Signal assignment statement:

436: store_last_txtb_index <= '1';
Count: 2
Threshold: 1

Signal assignment statement:

439: frame_valid_com_clear <= '1';
Count: 94
Threshold: 1

Signal assignment statement:

442: fsm_wait_state_d <= '1';
Count: 73
Threshold: 1

Signal assignment statement:

443: load_ts_lw_addr <= '1';
Count: 73
Threshold: 1

Signal assignment statement:

446: fsm_wait_state_d <= '1';
Count: 26631
Threshold: 1

Signal assignment statement:

447: load_ident_w_addr <= '1';
Count: 26631
Threshold: 1

Signal assignment statement:

448: buffer_md_w <= '1';
Count: 26631
Threshold: 1

Signal assignment statement:

449: tx_arb_parity_check_valid <= '1';
Count: 26631
Threshold: 1

Signal assignment statement:

456: txtb_meta_clk_en <= '1';
Count: 51251
Threshold: 1

If statement:

458:            if (txtb_hw_cmd_lock = '1') then 
459:                store_last_txtb_index <= '1'; 
...
474:                tx_arb_parity_check_valid <= '1'; 
475:            end if;

Count: 51251
Threshold: 1

Signal assignment statement:

459: store_last_txtb_index <= '1';
Count: 2
Threshold: 1

Signal assignment statement:

462: frame_valid_com_clear <= '1';
Count: 82
Threshold: 1

Signal assignment statement:

465: fsm_wait_state_d <= '1';
Count: 66
Threshold: 1

Signal assignment statement:

466: load_ts_lw_addr <= '1';
Count: 66
Threshold: 1

If statement:

469:                if (parity_error_vld = '0') then 
470:                    commit_dbl_bufs     <= '1'; 
471:                    frame_valid_com_set <= '1'; 
472:                end if;

Count: 25811
Threshold: 1

Signal assignment statement:

470: commit_dbl_bufs <= '1';
Count: 25485
Threshold: 1

Signal assignment statement:

471: frame_valid_com_set <= '1';
Count: 25485
Threshold: 1

Signal assignment statement:

474: tx_arb_parity_check_valid <= '1';
Count: 25811
Threshold: 1

If statement:

481:            if (txtb_hw_cmd_lock = '1') then 
482:                store_last_txtb_index <= '1'; 
...
489:                load_ts_lw_addr     <= '1'; 
490:            end if;

Count: 50385
Threshold: 1

Signal assignment statement:

482: store_last_txtb_index <= '1';
Count: 24831
Threshold: 1

Signal assignment statement:

485: frame_valid_com_clear <= '1';
Count: 207
Threshold: 1

Signal assignment statement:

488: fsm_wait_state_d <= '1';
Count: 233
Threshold: 1

Signal assignment statement:

489: load_ts_lw_addr <= '1';
Count: 233
Threshold: 1

Signal assignment statement:

496: tx_arb_locked <= '1';
Count: 132159
Threshold: 1

If statement:

498:            if (txtb_hw_cmd_unlock = '1') then 
499:                frame_valid_com_clear <= '1'; 
500:            end if;

Count: 132159
Threshold: 1

Signal assignment statement:

499: frame_valid_com_clear <= '1';
Count: 24805
Threshold: 1

If statement:

511:        if (res_n = '0') then 
512:            curr_state <= s_arb_idle; 
...
516:            end if; 
517:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

512: curr_state <= s_arb_idle;
Count: 2418499
Threshold: 1

If statement:

514:            if (tx_arb_fsm_ce = '1') then 
515:                curr_state <= next_state; 
516:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

515: curr_state <= next_state;
Count: 203746
Threshold: 1

If statement:

521:    tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else 
522:                     '0';

Count: 418009
Threshold: 1

Signal assignment statement:

521: tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else
Count: 209870
Threshold: 1

Signal assignment statement:

522: '0';
Count: 208139
Threshold: 1

If statement:

530:        if (res_n = '0') then 
531:            fsm_wait_state_q <= '1'; 
532:        elsif (rising_edge(clk_sys)) then 
533:            fsm_wait_state_q <= fsm_wait_state_d; 
534:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

531: fsm_wait_state_q <= '1';
Count: 2418499
Threshold: 1

Signal assignment statement:

533: fsm_wait_state_q <= fsm_wait_state_d;
Count: 526374300
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

195: parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0')

	Evaluated to	Count	Threshold
Bin	True	3104	1
Bin	False	276867	1

"case" / "with" / "select" choice:

213: when s_arb_idle =>

	Choice of	Count	Threshold
Bin	`s_arb_idle`	118299	1

"if" / "when" / "else" condition:

214: if (select_buf_avail = '1') then

	Evaluated to	Count	Threshold
Bin	True	30098	1
Bin	False	88201	1

"case" / "with" / "select" choice:

221: when s_arb_sel_low_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_low_ts`	70790	1

"if" / "when" / "else" condition:

222: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	70780	1

"if" / "when" / "else" condition:

224: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	857	1
Bin	False	69923	1

"if" / "when" / "else" condition:

226: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	17570	1
Bin	False	52353	1

"if" / "when" / "else" condition:

228: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26340	1
Bin	False	26013	1

"case" / "with" / "select" choice:

236: when s_arb_sel_upp_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_upp_ts`	51833	1

"if" / "when" / "else" condition:

237: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	51823	1

"if" / "when" / "else" condition:

239: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	150	1
Bin	False	51673	1

"if" / "when" / "else" condition:

241: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	81	1
Bin	False	51592	1

"if" / "when" / "else" condition:

243: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	25855	1
Bin	False	25737	1

"if" / "when" / "else" condition:

244: if (timestamp_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	25721	1
Bin	False	134	1

"case" / "with" / "select" choice:

252: when s_arb_sel_ftw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ftw`	51853	1

"if" / "when" / "else" condition:

253: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	51851	1

"if" / "when" / "else" condition:

257: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	94	1
Bin	False	51757	1

"if" / "when" / "else" condition:

259: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	71	1
Bin	False	51686	1

"if" / "when" / "else" condition:

261: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26124	1
Bin	False	25562	1

"case" / "with" / "select" choice:

268: when s_arb_sel_ffw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ffw`	52868	1

"if" / "when" / "else" condition:

269: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	52866	1

"if" / "when" / "else" condition:

271: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	1354	1
Bin	False	51512	1

"if" / "when" / "else" condition:

273: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	73	1
Bin	False	51439	1

"if" / "when" / "else" condition:

275: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	25990	1
Bin	False	25449	1

"case" / "with" / "select" choice:

282: when s_arb_sel_idw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_idw`	51251	1

"if" / "when" / "else" condition:

283: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	51249	1

"if" / "when" / "else" condition:

285: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	True	408	1
Bin	False	50841	1

"if" / "when" / "else" condition:

287: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	66	1
Bin	False	50775	1

"if" / "when" / "else" condition:

289: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	25485	1
Bin	False	25290	1

"case" / "with" / "select" choice:

296: when s_arb_validated =>

	Choice of	Count	Threshold
Bin	`s_arb_validated`	50385	1

"if" / "when" / "else" condition:

297: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	24831	1
Bin	False	25554	1

"if" / "when" / "else" condition:

299: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	207	1
Bin	False	25347	1

"if" / "when" / "else" condition:

301: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	233	1
Bin	False	25114	1

"case" / "with" / "select" choice:

308: when s_arb_locked =>

	Choice of	Count	Threshold
Bin	`s_arb_locked`	132159	1

"if" / "when" / "else" condition:

309: if (txtb_hw_cmd_unlock = '1') then

	Evaluated to	Count	Threshold
Bin	True	24805	1
Bin	False	107354	1

"case" / "with" / "select" choice:

353: when s_arb_idle =>

	Choice of	Count	Threshold
Bin	`s_arb_idle`	118299	1

"if" / "when" / "else" condition:

354: if (select_buf_avail = '1') then

	Evaluated to	Count	Threshold
Bin	True	30098	1
Bin	False	88201	1

"case" / "with" / "select" choice:

362: when s_arb_sel_low_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_low_ts`	70790	1

"if" / "when" / "else" condition:

365: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	70780	1

"if" / "when" / "else" condition:

368: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	193	1
Bin	False	70587	1

"if" / "when" / "else" condition:

371: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	17751	1
Bin	False	52836	1

"if" / "when" / "else" condition:

375: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26806	1
Bin	False	26030	1

"case" / "with" / "select" choice:

386: when s_arb_sel_upp_ts =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_upp_ts`	51833	1

"if" / "when" / "else" condition:

389: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	51823	1

"if" / "when" / "else" condition:

392: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	117	1
Bin	False	51706	1

"if" / "when" / "else" condition:

395: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	81	1
Bin	False	51625	1

"if" / "when" / "else" condition:

399: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	25888	1
Bin	False	25737	1

"if" / "when" / "else" condition:

400: if (timestamp_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	25754	1
Bin	False	134	1

"case" / "with" / "select" choice:

410: when s_arb_sel_ftw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ftw`	51853	1

"if" / "when" / "else" condition:

413: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	51851	1

"if" / "when" / "else" condition:

416: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	94	1
Bin	False	51757	1

"if" / "when" / "else" condition:

419: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	71	1
Bin	False	51686	1

"if" / "when" / "else" condition:

423: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26124	1
Bin	False	25562	1

"case" / "with" / "select" choice:

432: when s_arb_sel_ffw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_ffw`	52868	1

"if" / "when" / "else" condition:

435: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	52866	1

"if" / "when" / "else" condition:

438: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	94	1
Bin	False	52772	1

"if" / "when" / "else" condition:

441: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	73	1
Bin	False	52699	1

"if" / "when" / "else" condition:

445: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	26631	1
Bin	False	26068	1

"case" / "with" / "select" choice:

455: when s_arb_sel_idw =>

	Choice of	Count	Threshold
Bin	`s_arb_sel_idw`	51251	1

"if" / "when" / "else" condition:

458: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	2	1
Bin	False	51249	1

"if" / "when" / "else" condition:

461: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	82	1
Bin	False	51167	1

"if" / "when" / "else" condition:

464: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	66	1
Bin	False	51101	1

"if" / "when" / "else" condition:

468: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	True	25811	1
Bin	False	25290	1

"if" / "when" / "else" condition:

469: if (parity_error_vld = '0') then

	Evaluated to	Count	Threshold
Bin	True	25485	1
Bin	False	326	1

"case" / "with" / "select" choice:

480: when s_arb_validated =>

	Choice of	Count	Threshold
Bin	`s_arb_validated`	50385	1

"if" / "when" / "else" condition:

481: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	24831	1
Bin	False	25554	1

"if" / "when" / "else" condition:

484: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	True	207	1
Bin	False	25347	1

"if" / "when" / "else" condition:

487: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	True	233	1
Bin	False	25114	1

"case" / "with" / "select" choice:

495: when s_arb_locked =>

	Choice of	Count	Threshold
Bin	`s_arb_locked`	132159	1

"if" / "when" / "else" condition:

498: if (txtb_hw_cmd_unlock = '1') then

	Evaluated to	Count	Threshold
Bin	True	24805	1
Bin	False	107354	1

"if" / "when" / "else" condition:

511: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

513: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

514: if (tx_arb_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	203746	1
Bin	False	526170554	1

"if" / "when" / "else" condition:

521: tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else

	Evaluated to	Count	Threshold
Bin	True	209870	1
Bin	False	208139	1

"if" / "when" / "else" condition:

530: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

532: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SELECT_BUF_AVAIL

	From	To	Count	Threshold
Bin	0	1	26539	1
Bin	1	0	28139	1

Port:

SELECT_INDEX_CHANGED

	From	To	Count	Threshold
Bin	0	1	45237	1
Bin	1	0	45246	1

Port:

TIMESTAMP_VALID

	From	To	Count	Threshold
Bin	0	1	1791	1
Bin	1	0	191	1

Port:

TXTB_HW_CMD_LOCK

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Port:

TXTB_HW_CMD_UNLOCK

	From	To	Count	Threshold
Bin	0	1	24805	1
Bin	1	0	26405	1

Port:

TXTB_PARITY_MISMATCH_VLD

	From	To	Count	Threshold
Bin	0	1	2251	1
Bin	1	0	3851	1

Port:

LOAD_TS_LW_ADDR

	From	To	Count	Threshold
Bin	0	1	28315	1
Bin	1	0	29915	1

Port:

LOAD_TS_UW_ADDR

	From	To	Count	Threshold
Bin	0	1	25893	1
Bin	1	0	27493	1

Port:

LOAD_FFMT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25505	1
Bin	1	0	27105	1

Port:

LOAD_IDENT_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25393	1
Bin	1	0	26993	1

Port:

LOAD_FRAME_TEST_W_ADDR

	From	To	Count	Threshold
Bin	0	1	25721	1
Bin	1	0	27321	1

Port:

TXTB_META_CLK_EN

	From	To	Count	Threshold
Bin	0	1	25912	1
Bin	1	0	27512	1

Port:

STORE_TS_L_W

	From	To	Count	Threshold
Bin	0	1	25893	1
Bin	1	0	27493	1

Port:

COMMIT_DBL_BUFS

	From	To	Count	Threshold
Bin	0	1	25479	1
Bin	1	0	27079	1

Port:

BUFFER_FRAME_TEST_W

	From	To	Count	Threshold
Bin	0	1	25505	1
Bin	1	0	27105	1

Port:

BUFFER_MD_W

	From	To	Count	Threshold
Bin	0	1	25393	1
Bin	1	0	26993	1

Port:

TX_ARB_LOCKED

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Port:

STORE_LAST_TXTB_INDEX

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Port:

FRAME_VALID_COM_SET

	From	To	Count	Threshold
Bin	0	1	25479	1
Bin	1	0	27079	1

Port:

FRAME_VALID_COM_CLEAR

	From	To	Count	Threshold
Bin	0	1	25563	1
Bin	1	0	27163	1

Port:

TX_ARB_PARITY_CHECK_VALID

	From	To	Count	Threshold
Bin	0	1	102172	1
Bin	1	0	103772	1

Signal:

TX_ARB_FSM_CE

	From	To	Count	Threshold
Bin	0	1	206539	1
Bin	1	0	208139	1

Signal:

FSM_WAIT_STATE_D

	From	To	Count	Threshold
Bin	0	1	130522	1
Bin	1	0	132122	1

Signal:

FSM_WAIT_STATE_Q

	From	To	Count	Threshold
Bin	0	1	136130	1
Bin	1	0	136139	1

Signal:

PARITY_ERROR_VLD

	From	To	Count	Threshold
Bin	0	1	3104	1
Bin	1	0	4704	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

195: parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0')

	Evaluated to	Count	Threshold
Bin	False	275867	1
Bin	True	4104	1

"=" expression

195: parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0')

	Evaluated to	Count	Threshold
Bin	False	139477	1
Bin	True	140494	1

"and" expression

195:    parity_error_vld <= '1' when (txtb_parity_mismatch_vld = '1' and fsm_wait_state_q = '0') 
                                      <------------LHS------------->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	137390	1
Bin	True	False	1000	1
Bin	True	True	3104	1

"=" expression

214: if (select_buf_avail = '1') then

	Evaluated to	Count	Threshold
Bin	False	88201	1
Bin	True	30098	1

"=" expression

222: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	70780	1
Bin	True	10	1

"=" expression

224: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	70587	1
Bin	True	193	1

"=" expression

224: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	70116	1
Bin	True	664	1

"or" expression

224:            elsif (select_buf_avail = '0' or parity_error_vld = '1') then 
                       <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	69923	1
Bin	False	True	664	1
Bin	True	False	193	1

"=" expression

226: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	52353	1
Bin	True	17570	1

"=" expression

228: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	26013	1
Bin	True	26340	1

"=" expression

237: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	51823	1
Bin	True	10	1

"=" expression

239: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	51706	1
Bin	True	117	1

"=" expression

239: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	51790	1
Bin	True	33	1

"or" expression

239:            elsif (select_buf_avail = '0' or parity_error_vld = '1') then 
                       <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	51673	1
Bin	False	True	33	1
Bin	True	False	117	1

"=" expression

241: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	51592	1
Bin	True	81	1

"=" expression

243: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25737	1
Bin	True	25855	1

"=" expression

244: if (timestamp_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	134	1
Bin	True	25721	1

"=" expression

253: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	51851	1
Bin	True	2	1

"=" expression

257: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	51757	1
Bin	True	94	1

"=" expression

259: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	51686	1
Bin	True	71	1

"=" expression

261: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25562	1
Bin	True	26124	1

"=" expression

269: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	52866	1
Bin	True	2	1

"=" expression

271: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	52772	1
Bin	True	94	1

"=" expression

271: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	51606	1
Bin	True	1260	1

"or" expression

271:            elsif (select_buf_avail = '0' or parity_error_vld = '1') then 
                       <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	51512	1
Bin	False	True	1260	1
Bin	True	False	94	1

"=" expression

273: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	51439	1
Bin	True	73	1

"=" expression

275: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25449	1
Bin	True	25990	1

"=" expression

283: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	51249	1
Bin	True	2	1

"=" expression

285: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	51167	1
Bin	True	82	1

"=" expression

285: elsif (select_buf_avail = '0' or parity_error_vld = '1') then

	Evaluated to	Count	Threshold
Bin	False	50923	1
Bin	True	326	1

"or" expression

285:            elsif (select_buf_avail = '0' or parity_error_vld = '1') then 
                       <--------LHS--------->    <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	50841	1
Bin	False	True	326	1
Bin	True	False	82	1

"=" expression

287: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	50775	1
Bin	True	66	1

"=" expression

289: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25290	1
Bin	True	25485	1

"=" expression

297: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	25554	1
Bin	True	24831	1

"=" expression

299: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	25347	1
Bin	True	207	1

"=" expression

301: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	25114	1
Bin	True	233	1

"=" expression

309: if (txtb_hw_cmd_unlock = '1') then

	Evaluated to	Count	Threshold
Bin	False	107354	1
Bin	True	24805	1

"=" expression

354: if (select_buf_avail = '1') then

	Evaluated to	Count	Threshold
Bin	False	88201	1
Bin	True	30098	1

"=" expression

365: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	70780	1
Bin	True	10	1

"=" expression

368: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	70587	1
Bin	True	193	1

"=" expression

371: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	52836	1
Bin	True	17751	1

"=" expression

375: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	26030	1
Bin	True	26806	1

"=" expression

389: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	51823	1
Bin	True	10	1

"=" expression

392: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	51706	1
Bin	True	117	1

"=" expression

395: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	51625	1
Bin	True	81	1

"=" expression

399: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25737	1
Bin	True	25888	1

"=" expression

400: if (timestamp_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	134	1
Bin	True	25754	1

"=" expression

413: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	51851	1
Bin	True	2	1

"=" expression

416: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	51757	1
Bin	True	94	1

"=" expression

419: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	51686	1
Bin	True	71	1

"=" expression

423: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25562	1
Bin	True	26124	1

"=" expression

435: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	52866	1
Bin	True	2	1

"=" expression

438: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	52772	1
Bin	True	94	1

"=" expression

441: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	52699	1
Bin	True	73	1

"=" expression

445: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	26068	1
Bin	True	26631	1

"=" expression

458: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	51249	1
Bin	True	2	1

"=" expression

461: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	51167	1
Bin	True	82	1

"=" expression

464: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	51101	1
Bin	True	66	1

"=" expression

468: elsif (fsm_wait_state_q = '0') then

	Evaluated to	Count	Threshold
Bin	False	25290	1
Bin	True	25811	1

"=" expression

469: if (parity_error_vld = '0') then

	Evaluated to	Count	Threshold
Bin	False	326	1
Bin	True	25485	1

"=" expression

481: if (txtb_hw_cmd_lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	25554	1
Bin	True	24831	1

"=" expression

484: elsif (select_buf_avail = '0') then

	Evaluated to	Count	Threshold
Bin	False	25347	1
Bin	True	207	1

"=" expression

487: elsif (select_index_changed = '1') then

	Evaluated to	Count	Threshold
Bin	False	25114	1
Bin	True	233	1

"=" expression

498: if (txtb_hw_cmd_unlock = '1') then

	Evaluated to	Count	Threshold
Bin	False	107354	1
Bin	True	24805	1

"=" expression

511: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

514: if (tx_arb_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526170554	1
Bin	True	203746	1

"/=" expression

521: tx_arb_fsm_ce <= '1' when (curr_state /= next_state) else

	Evaluated to	Count	Threshold
Bin	False	208139	1
Bin	True	209870	1

"=" expression

530: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

"T_TX_ARB_STATE" FSM

182: signal curr_state : t_tx_arb_state;

	State	Count	Threshold
Bin	S_ARB_IDLE	27420	1
Bin	S_ARB_SEL_LOW_TS	25999	1
Bin	S_ARB_SEL_UPP_TS	25737	1
Bin	S_ARB_SEL_FFW	25449	1
Bin	S_ARB_SEL_IDW	25290	1
Bin	S_ARB_SEL_FTW	25562	1
Bin	S_ARB_VALIDATED	25109	1
Bin	S_ARB_LOCKED	24816	1

"T_TX_ARB_STATE" FSM

183: signal next_state : t_tx_arb_state;

	State	Count	Threshold
Bin	S_ARB_IDLE	31297	1
Bin	S_ARB_SEL_LOW_TS	28436	1
Bin	S_ARB_SEL_UPP_TS	26359	1
Bin	S_ARB_SEL_FFW	26124	1
Bin	S_ARB_SEL_IDW	25990	1
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Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.TX_ARBITRATOR_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator_fsm.vhd

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