NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP.ADDR_DEC_REG_FALSE_GEN

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP.ADDR_DEC_REG_FALSE_GEN	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement	Branch	Toggle	Expression	FSM state	Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 174:

174: addr_dec <= addr_dec_enabled_i;
Count: 38434194
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: