NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.FEATURE_TEST_AGENT_GEN.FEATURE_TEST_AGENT_INST.TEST_NODE_INST.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TXT_BUF_TEST_DATA_PADDING_GEN(5).TXT_BUF_PADDING_INDEX_GEN_FALSE

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.FEATURE_TEST_AGENT_GEN.FEATURE_TEST_AGENT_INST.TEST_NODE_INST.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TXT_BUF_TEST_DATA_PADDING_GEN(5).TXT_BUF_PADDING_INDEX_GEN_FALSE	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement	Branch	Toggle	Expression	FSM state	Functional

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: