NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TX_DATA_CACHE_INST	100.0 % (15/15)	100.0 % (18/18)	100.0 % (60/60)	100.0 % (12/12)	N.A.	N.A.	100.0 % (105/105)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TX_DATA_CACHE_INST

100.0 % (15/15)

100.0 % (18/18)

100.0 % (60/60)

100.0 % (12/12)

N.A.

100.0 % (105/105)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 146:

146: write_pointer_d <= write_pointer_q + 1;
Count: 164551
Threshold: 1

Signal assignment statement on line 147:

147: read_pointer_d <= read_pointer_q + 1;
Count: 163063
Threshold: 1

If statement on lines 155 to 161:

155:        if (res_n = '0') then 
156:            write_pointer_q        <= (others => '0'); 
...
160:            end if; 
161:        end if;

Count: 1090084515
Threshold: 1

Signal assignment statement on line 156:

156: write_pointer_q <= (others => '0');
Count: 6492788
Threshold: 1

If statement on lines 158 to 160:

158:            if (write = '1') then 
159:                write_pointer_q    <= write_pointer_d; 
160:            end if;

Count: 541774303
Threshold: 1

Signal assignment statement on line 159:

159: write_pointer_q <= write_pointer_d;
Count: 159398
Threshold: 1

If statement on lines 167 to 173:

167:        if (res_n = '0') then 
168:            read_pointer_q         <= (others => '0'); 
...
172:            end if; 
173:        end if;

Count: 1090084515
Threshold: 1

Signal assignment statement on line 168:

168: read_pointer_q <= (others => '0');
Count: 6492788
Threshold: 1

If statement on lines 170 to 172:

170:            if (read = '1') then 
171:                read_pointer_q     <= read_pointer_d; 
172:            end if;

Count: 541774303
Threshold: 1

Signal assignment statement on line 171:

171: read_pointer_q <= read_pointer_d;
Count: 158188
Threshold: 1

If statement on lines 182 to 188:

182:        if (res_n = '0') then 
183:            tx_cache_mem <= (others => G_TX_CACHE_RST_VAL); 
...
187:            end if; 
188:        end if;

Count: 1090084515
Threshold: 1

Signal assignment statement on line 183:

183: tx_cache_mem <= (others => G_TX_CACHE_RST_VAL);
Count: 6492788
Threshold: 1

If statement on lines 185 to 187:

185:            if (write = '1') then 
186:                tx_cache_mem(to_integer(write_pointer_q(2 downto 0))) <= data_in; 
187:            end if;

Count: 541774303
Threshold: 1

Signal assignment statement on line 186:

186: tx_cache_mem(to_integer(write_pointer_q(2 downto 0))) <= data_in;
Count: 159398
Threshold: 1

Signal assignment statement on line 196:

196: data_out <= tx_cache_mem(to_integer(read_pointer_q(2 downto 0)));
Count: 239242
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

155: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	6492788	1
Bin	False	1083591727	1

"if" / "when" / "else" condition on line 157:

157: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	541774303	1
Bin	False	541817424	1

"if" / "when" / "else" condition on line 158:

158: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	True	159398	1
Bin	False	541614905	1

"if" / "when" / "else" condition on line 167:

167: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	6492788	1
Bin	False	1083591727	1

"if" / "when" / "else" condition on line 169:

169: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	541774303	1
Bin	False	541817424	1

"if" / "when" / "else" condition on line 170:

170: if (read = '1') then

	Evaluated to	Count	Threshold
Bin	True	158188	1
Bin	False	541616115	1

"if" / "when" / "else" condition on line 182:

182: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	6492788	1
Bin	False	1083591727	1

"if" / "when" / "else" condition on line 184:

184: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	541774303	1
Bin	False	541817424	1

"if" / "when" / "else" condition on line 185:

185: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	True	159398	1
Bin	False	541614905	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

DATA_OUT

	From	To	Count	Threshold
Bin	0	1	81893	1
Bin	1	0	80292	1

Signal:

TX_CACHE_MEM

	Element	From	To	Count	Threshold
Bin	(7)	0	1	44999	1
Bin	(7)	1	0	34454	1
Bin	(6)	0	1	44003	1
Bin	(6)	1	0	35450	1
Bin	(5)	0	1	45229	1
Bin	(5)	1	0	34224	1
Bin	(4)	0	1	43503	1
Bin	(4)	1	0	35950	1
Bin	(3)	0	1	42427	1
Bin	(3)	1	0	37026	1
Bin	(2)	0	1	43463	1
Bin	(2)	1	0	35990	1
Bin	(1)	0	1	40873	1
Bin	(1)	1	0	38580	1
Bin	(0)	0	1	36513	1
Bin	(0)	1	0	42940	1

Signal:

WRITE_POINTER_Q

	Element	From	To	Count	Threshold
Bin	(3)	0	1	10015	1
Bin	(3)	1	0	11616	1
Bin	(2)	0	1	19874	1
Bin	(2)	1	0	21475	1
Bin	(1)	0	1	39953	1
Bin	(1)	1	0	41554	1
Bin	(0)	0	1	80319	1
Bin	(0)	1	0	81920	1

Signal:

WRITE_POINTER_D

	Element	From	To	Count	Threshold
Bin	(3)	0	1	10080	1
Bin	(3)	1	0	11681	1
Bin	(2)	0	1	20139	1
Bin	(2)	1	0	21740	1
Bin	(1)	0	1	40780	1
Bin	(1)	1	0	42381	1
Bin	(0)	0	1	81920	1
Bin	(0)	1	0	80319	1

Signal:

READ_POINTER_Q

	Element	From	To	Count	Threshold
Bin	(3)	0	1	76284	1
Bin	(3)	1	0	85178	1
Bin	(2)	0	1	19764	1
Bin	(2)	1	0	21585	1
Bin	(1)	0	1	39701	1
Bin	(1)	1	0	41522	1
Bin	(0)	0	1	79530	1
Bin	(0)	1	0	81351	1

Signal:

READ_POINTER_D

	Element	From	To	Count	Threshold
Bin	(3)	0	1	10047	1
Bin	(3)	1	0	11648	1
Bin	(2)	0	1	20021	1
Bin	(2)	1	0	21622	1
Bin	(1)	0	1	40213	1
Bin	(1)	1	0	41814	1
Bin	(0)	0	1	81131	1
Bin	(0)	1	0	79530	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 155:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1083591727	1
Bin	True	6492788	1

"=" expression on line 158:

write = '1'

	Evaluated to	Count	Threshold
Bin	False	541614905	1
Bin	True	159398	1

"=" expression on line 167:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1083591727	1
Bin	True	6492788	1

"=" expression on line 170:

read = '1'

	Evaluated to	Count	Threshold
Bin	False	541616115	1
Bin	True	158188	1

"=" expression on line 182:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1083591727	1
Bin	True	6492788	1

"=" expression on line 185:

write = '1'

	Evaluated to	Count	Threshold
Bin	False	541614905	1
Bin	True	159398	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TX_DATA_CACHE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 146:

Signal assignment statement on line 147:

If statement on lines 155 to 161:

Signal assignment statement on line 156:

If statement on lines 158 to 160:

Signal assignment statement on line 159:

If statement on lines 167 to 173:

Signal assignment statement on line 168:

If statement on lines 170 to 172:

Signal assignment statement on line 171:

If statement on lines 182 to 188:

Signal assignment statement on line 183:

If statement on lines 185 to 187:

Signal assignment statement on line 186:

Signal assignment statement on line 196:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 158:

"if" / "when" / "else" condition on line 167:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 170:

"if" / "when" / "else" condition on line 182:

"if" / "when" / "else" condition on line 184:

"if" / "when" / "else" condition on line 185:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 155:

"=" expression on line 158:

"=" expression on line 167:

"=" expression on line 170:

"=" expression on line 182:

"=" expression on line 185:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: