NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TX_DATA_CACHE_INST	100.0 % (15/15)	100.0 % (18/18)	100.0 % (60/60)	100.0 % (12/12)	N.A.	N.A.	100.0 % (105/105)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

146: write_pointer_d <= write_pointer_q + 1;
Count: 195026
Threshold: 1

Signal assignment statement:

147: read_pointer_d <= read_pointer_q + 1;
Count: 193031
Threshold: 1

If statement:

155:        if (res_n = '0') then 
156:            write_pointer_q        <= (others => '0'); 
...
160:            end if; 
161:        end if;

Count: 1055246640
Threshold: 1

Signal assignment statement:

156: write_pointer_q <= (others => '0');
Count: 6477454
Threshold: 1

If statement:

158:            if (write = '1') then 
159:                write_pointer_q    <= write_pointer_d; 
160:            end if;

Count: 524362212
Threshold: 1

Signal assignment statement:

159: write_pointer_q <= write_pointer_d;
Count: 189570
Threshold: 1

If statement:

167:        if (res_n = '0') then 
168:            read_pointer_q         <= (others => '0'); 
...
172:            end if; 
173:        end if;

Count: 1055246640
Threshold: 1

Signal assignment statement:

168: read_pointer_q <= (others => '0');
Count: 6477454
Threshold: 1

If statement:

170:            if (read = '1') then 
171:                read_pointer_q     <= read_pointer_d; 
172:            end if;

Count: 524362212
Threshold: 1

Signal assignment statement:

171: read_pointer_q <= read_pointer_d;
Count: 188011
Threshold: 1

If statement:

182:        if (res_n = '0') then 
183:            tx_cache_mem <= (others => G_TX_CACHE_RST_VAL); 
...
187:            end if; 
188:        end if;

Count: 1055246640
Threshold: 1

Signal assignment statement:

183: tx_cache_mem <= (others => G_TX_CACHE_RST_VAL);
Count: 6477454
Threshold: 1

If statement:

185:            if (write = '1') then 
186:                tx_cache_mem(to_integer(write_pointer_q(2 downto 0))) <= data_in; 
187:            end if;

Count: 524362212
Threshold: 1

Signal assignment statement:

186: tx_cache_mem(to_integer(write_pointer_q(2 downto 0))) <= data_in;
Count: 189570
Threshold: 1

Signal assignment statement:

196: data_out <= tx_cache_mem(to_integer(read_pointer_q(2 downto 0)));
Count: 284053
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

155: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	6477454	1
Bin	False	1048769186	1

"if" / "when" / "else" condition:

157: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	524362212	1
Bin	False	524406974	1

"if" / "when" / "else" condition:

158: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	True	189570	1
Bin	False	524172642	1

"if" / "when" / "else" condition:

167: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	6477454	1
Bin	False	1048769186	1

"if" / "when" / "else" condition:

169: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	524362212	1
Bin	False	524406974	1

"if" / "when" / "else" condition:

170: if (read = '1') then

	Evaluated to	Count	Threshold
Bin	True	188011	1
Bin	False	524174201	1

"if" / "when" / "else" condition:

182: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	6477454	1
Bin	False	1048769186	1

"if" / "when" / "else" condition:

184: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	524362212	1
Bin	False	524406974	1

"if" / "when" / "else" condition:

185: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	True	189570	1
Bin	False	524172642	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	42860	1
Bin	1	0	42851	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	189570	1
Bin	1	0	191170	1

Port:

READ

	From	To	Count	Threshold
Bin	0	1	190334	1
Bin	1	0	191934	1

Port:

DATA_IN

	From	To	Count	Threshold
Bin	0	1	635336	1
Bin	1	0	633738	1

Port:

DATA_OUT

	From	To	Count	Threshold
Bin	0	1	97563	1
Bin	1	0	95963	1

Signal:

TX_CACHE_MEM(7)

	From	To	Count	Threshold
Bin	0	1	51928	1
Bin	1	0	42514	1

Signal:

TX_CACHE_MEM(6)

	From	To	Count	Threshold
Bin	0	1	51274	1
Bin	1	0	43168	1

Signal:

TX_CACHE_MEM(5)

	From	To	Count	Threshold
Bin	0	1	53080	1
Bin	1	0	41362	1

Signal:

TX_CACHE_MEM(4)

	From	To	Count	Threshold
Bin	0	1	50739	1
Bin	1	0	43703	1

Signal:

TX_CACHE_MEM(3)

	From	To	Count	Threshold
Bin	0	1	49738	1
Bin	1	0	44704	1

Signal:

TX_CACHE_MEM(2)

	From	To	Count	Threshold
Bin	0	1	47852	1
Bin	1	0	46590	1

Signal:

TX_CACHE_MEM(1)

	From	To	Count	Threshold
Bin	0	1	48309	1
Bin	1	0	46133	1

Signal:

TX_CACHE_MEM(0)

	From	To	Count	Threshold
Bin	0	1	44114	1
Bin	1	0	50328	1

Signal:

WRITE_POINTER_Q(3)

	From	To	Count	Threshold
Bin	0	1	11904	1
Bin	1	0	13504	1

Signal:

WRITE_POINTER_Q(2)

	From	To	Count	Threshold
Bin	0	1	23694	1
Bin	1	0	25294	1

Signal:

WRITE_POINTER_Q(1)

	From	To	Count	Threshold
Bin	0	1	47371	1
Bin	1	0	48971	1

Signal:

WRITE_POINTER_Q(0)

	From	To	Count	Threshold
Bin	0	1	95516	1
Bin	1	0	97116	1

Signal:

WRITE_POINTER_D(3)

	From	To	Count	Threshold
Bin	0	1	11962	1
Bin	1	0	13562	1

Signal:

WRITE_POINTER_D(2)

	From	To	Count	Threshold
Bin	0	1	23914	1
Bin	1	0	25514	1

Signal:

WRITE_POINTER_D(1)

	From	To	Count	Threshold
Bin	0	1	48530	1
Bin	1	0	50130	1

Signal:

WRITE_POINTER_D(0)

	From	To	Count	Threshold
Bin	0	1	97116	1
Bin	1	0	95516	1

Signal:

READ_POINTER_Q(3)

	From	To	Count	Threshold
Bin	0	1	90851	1
Bin	1	0	100580	1

Signal:

READ_POINTER_Q(2)

	From	To	Count	Threshold
Bin	0	1	23507	1
Bin	1	0	25379	1

Signal:

READ_POINTER_Q(1)

	From	To	Count	Threshold
Bin	0	1	47111	1
Bin	1	0	48983	1

Signal:

READ_POINTER_Q(0)

	From	To	Count	Threshold
Bin	0	1	94489	1
Bin	1	0	96361	1

Signal:

READ_POINTER_D(3)

	From	To	Count	Threshold
Bin	0	1	11928	1
Bin	1	0	13528	1

Signal:

READ_POINTER_D(2)

	From	To	Count	Threshold
Bin	0	1	23782	1
Bin	1	0	25382	1

Signal:

READ_POINTER_D(1)

	From	To	Count	Threshold
Bin	0	1	47685	1
Bin	1	0	49285	1

Signal:

READ_POINTER_D(0)

	From	To	Count	Threshold
Bin	0	1	96089	1
Bin	1	0	94489	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

155: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1048769186	1
Bin	True	6477454	1

"=" expression

158: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	False	524172642	1
Bin	True	189570	1

"=" expression

167: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1048769186	1
Bin	True	6477454	1

"=" expression

170: if (read = '1') then

	Evaluated to	Count	Threshold
Bin	False	524174201	1
Bin	True	188011	1

"=" expression

182: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1048769186	1
Bin	True	6477454	1

"=" expression

185: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	False	524172642	1
Bin	True	189570	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.TX_DATA_CACHE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/tx_data_cache.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"=" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states: