NVC code coverage report

Signal assignment statement on line 881:

881:    pc_rx_data_nbs <= bds_data_out; 
Count: 2785354
Threshold: 1

---

Signal assignment statement on line 882:

882:    bst_data_in <= pc_tx_data_nbs; 
Count: 1290280
Threshold: 1

---

Signal assignment statement on line 889:

889:    crc_data_tx_nbs <= pc_tx_data_nbs; 
Count: 1290280
Threshold: 1

---

Signal assignment statement on line 890:

890:    crc_data_rx_nbs <= bds_data_out; 
Count: 2785354
Threshold: 1

---

Signal assignment statement on line 897:

897:    crc_data_tx_wbs <= bst_data_out; 
Count: 1267628
Threshold: 1

---

Signal assignment statement on line 899:

899:    lpb_dominant <= rx_data_wbs and bst_data_out; 
Count: 4065379
Threshold: 1

---

If statement on lines 909 to 911:

909:    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else 
910:                   lpb_dominant when (mr_mode_bmm = '1') else 
911:                    rx_data_wbs; 
Count: 6898747
Threshold: 1

---

Signal assignment statement on line 909:

909:    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else 
Count: 274892
Threshold: 1

---

Signal assignment statement on line 910:

910:                   lpb_dominant when (mr_mode_bmm = '1') else 
Count: 1766
Threshold: 1

---

Signal assignment statement on line 911:

911:                    rx_data_wbs; 
Count: 6622089
Threshold: 1

---

If statement on lines 917 to 919:

917:    tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else 
918:                     RECESSIVE when (mr_mode_bmm = '1') else 
919:                     bst_data_out; 
Count: 1282203
Threshold: 1

---

Signal assignment statement on line 917:

917:    tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else 
Count: 8081
Threshold: 1

---

Signal assignment statement on line 918:

918:                     RECESSIVE when (mr_mode_bmm = '1') else 
Count: 50
Threshold: 1

---

Signal assignment statement on line 919:

919:                     bst_data_out; 
Count: 1274072
Threshold: 1

---

If statement on lines 925 to 926:

925:    no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else 
926:                     '0'; 
Count: 1267598
Threshold: 1

---

Signal assignment statement on line 925:

925:    no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else 
Count: 632200
Threshold: 1

---

Signal assignment statement on line 926:

926:                     '0'; 
Count: 635398
Threshold: 1

---

Signal assignment statement on line 931:

931:    cc_stat.is_err_active   <= is_err_active; 
Count: 18442
Threshold: 1

---

Signal assignment statement on line 932:

932:    cc_stat.is_err_passive  <= is_err_passive; 
Count: 4724
Threshold: 1

---

Signal assignment statement on line 933:

933:    cc_stat.is_bus_off      <= is_bus_off_i; 
Count: 18066
Threshold: 1

---

Signal assignment statement on line 934:

934:    cc_stat.is_transmitter  <= is_transmitter; 
Count: 43835
Threshold: 1

---

Signal assignment statement on line 935:

935:    cc_stat.is_receiver     <= is_receiver; 
Count: 65011
Threshold: 1

---

Signal assignment statement on line 936:

936:    cc_stat.is_idle         <= is_idle; 
Count: 114983
Threshold: 1

---

Signal assignment statement on line 937:

937:    cc_stat.tx_err_ctr      <= tx_err_ctr; 
Count: 33426
Threshold: 1

---

Signal assignment statement on line 938:

938:    cc_stat.rx_err_ctr      <= rx_err_ctr; 
Count: 27286
Threshold: 1

---

Signal assignment statement on line 939:

939:    cc_stat.status_pexs     <= mr_status_pexs; 
Count: 3352
Threshold: 1

---

Signal assignment statement on line 940:

940:    cc_stat.norm_err_ctr    <= norm_err_ctr; 
Count: 27160
Threshold: 1

---

Signal assignment statement on line 941:

941:    cc_stat.data_err_ctr    <= data_err_ctr; 
Count: 14587
Threshold: 1

---

Signal assignment statement on line 942:

942:    cc_stat.err_type        <= err_capt_err_type; 
Count: 7328
Threshold: 1

---

Signal assignment statement on line 943:

943:    cc_stat.err_erp         <= err_capt_err_erp; 
Count: 3782
Threshold: 1

---

Signal assignment statement on line 944:

944:    cc_stat.err_pos         <= err_capt_err_pos; 
Count: 12038
Threshold: 1

---

Signal assignment statement on line 945:

945:    cc_stat.retr_ctr        <= retr_ctr; 
Count: 4515
Threshold: 1

---

Signal assignment statement on line 946:

946:    cc_stat.alc_bit         <= alc_alc_bit; 
Count: 3819
Threshold: 1

---

Signal assignment statement on line 947:

947:    cc_stat.alc_id_field    <= alc_alc_id_field; 
Count: 3470
Threshold: 1

---

Signal assignment statement on line 948:

948:    cc_stat.rx_frame_ctr    <= rx_frame_ctr; 
Count: 15421
Threshold: 1

---

Signal assignment statement on line 949:

949:    cc_stat.tx_frame_ctr    <= tx_frame_ctr; 
Count: 8142
Threshold: 1

---

Signal assignment statement on line 950:

950:    cc_stat.bst_ctr         <= bst_ctr; 
Count: 296187
Threshold: 1

---

Signal assignment statement on line 951:

951:    cc_stat.dst_ctr         <= dst_ctr; 
Count: 995560
Threshold: 1

---

Signal assignment statement on line 952:

952:    cc_stat.status_ewl      <= mr_status_ewl; 
Count: 4757
Threshold: 1

---

Signal assignment statement on line 957:

957:    rec_valid               <= rec_valid_i; 
Count: 33558
Threshold: 1

---

Signal assignment statement on line 958:

958:    arbitration_lost        <= arbitration_lost_i; 
Count: 5544
Threshold: 1

---

Signal assignment statement on line 959:

959:    tran_valid              <= tran_valid_i; 
Count: 25426
Threshold: 1

---

Signal assignment statement on line 960:

960:    err_detected            <= err_detected_i; 
Count: 252142
Threshold: 1

---

Signal assignment statement on line 961:

961:    tx_data_wbs             <= tx_data_wbs_i; 
Count: 1267598
Threshold: 1

---

Signal assignment statement on line 962:

962:    sp_control              <= sp_control_i; 
Count: 59768
Threshold: 1

---

Signal assignment statement on line 965:

965:    pc_rx_trigger           <= pc_rx_trigger_i; 
Count: 20722828
Threshold: 1

"if" / "when" / "else" condition on line 909:

909:    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else 

	Evaluated to	Count	Threshold
Bin	True	274892	1
Bin	False	6623855	1

---

"if" / "when" / "else" condition on line 910:

910:                   lpb_dominant when (mr_mode_bmm = '1') else 

	Evaluated to	Count	Threshold
Bin	True	1766	1
Bin	False	6622089	1

---

"if" / "when" / "else" condition on line 917:

917:    tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else 

	Evaluated to	Count	Threshold
Bin	True	8081	1
Bin	False	1274122	1

---

"if" / "when" / "else" condition on line 918:

918:                     RECESSIVE when (mr_mode_bmm = '1') else 

	Evaluated to	Count	Threshold
Bin	True	50	1
Bin	False	1274072	1

---

"if" / "when" / "else" condition on line 925:

925:    no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else 

	Evaluated to	Count	Threshold
Bin	True	632200	1
Bin	False	635398	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_ACF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_STM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_FDE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_TSTM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_MODE_SAM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_NISOFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_RTRTH

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_RTRLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_ILBP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PEX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_ERCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_RXFCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_TXFCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_COMMAND_CPEXS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SSP_CFG_SSP_SRC

	Element	From	To	Count	Threshold	Excluded due to
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_EWL_EW_LIMIT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_ERP_ERP_LIMIT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_CTPV

	Element	From	To	Count	Threshold	Excluded due to
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_PTX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_PRX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_ENORM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_CTR_PRES_EFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_WORD

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TRAN_DLC

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TRAN_IS_RTR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_IDENT_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_FRAME_TYPE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_BRS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_IDENTIFIER

	Element	From	To	Count	Threshold	Excluded due to
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TRAN_FRAME_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TRAN_FRAME_PARITY_ERROR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_CHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RX_TRIGGERS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RX_DATA_WBS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 BIT_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SYNC_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

 CC_STAT

	Element	From	To	Count	Threshold
Bin	IS_ERR_ACTIVE	0	1	8426	1
Bin	IS_ERR_ACTIVE	1	0	8415	1
Bin	IS_ERR_PASSIVE	0	1	761	1
Bin	IS_ERR_PASSIVE	1	0	2362	1
Bin	IS_BUS_OFF	0	1	8227	1
Bin	IS_BUS_OFF	1	0	8238	1
Bin	IS_TRANSMITTER	0	1	20317	1
Bin	IS_TRANSMITTER	1	0	21917	1
Bin	IS_RECEIVER	0	1	30908	1
Bin	IS_RECEIVER	1	0	32502	1
Bin	IS_IDLE	0	1	55892	1
Bin	IS_IDLE	1	0	57490	1
Bin	TX_ERR_CTR(8)	0	1	246	1
Bin	TX_ERR_CTR(8)	1	0	1847	1
Bin	TX_ERR_CTR(7)	0	1	506	1
Bin	TX_ERR_CTR(7)	1	0	2107	1
Bin	TX_ERR_CTR(6)	0	1	504	1
Bin	TX_ERR_CTR(6)	1	0	2105	1
Bin	TX_ERR_CTR(5)	0	1	787	1
Bin	TX_ERR_CTR(5)	1	0	2388	1
Bin	TX_ERR_CTR(4)	0	1	1957	1
Bin	TX_ERR_CTR(4)	1	0	3557	1
Bin	TX_ERR_CTR(3)	0	1	12521	1
Bin	TX_ERR_CTR(3)	1	0	14122	1
Bin	TX_ERR_CTR(2)	0	1	2978	1
Bin	TX_ERR_CTR(2)	1	0	4579	1
Bin	TX_ERR_CTR(1)	0	1	3314	1
Bin	TX_ERR_CTR(1)	1	0	4915	1
Bin	TX_ERR_CTR(0)	0	1	3548	1
Bin	TX_ERR_CTR(0)	1	0	5149	1
Bin	RX_ERR_CTR(8)	0	1	126	1
Bin	RX_ERR_CTR(8)	1	0	1727	1
Bin	RX_ERR_CTR(7)	0	1	344	1
Bin	RX_ERR_CTR(7)	1	0	1945	1
Bin	RX_ERR_CTR(6)	0	1	262	1
Bin	RX_ERR_CTR(6)	1	0	1860	1
Bin	RX_ERR_CTR(5)	0	1	343	1
Bin	RX_ERR_CTR(5)	1	0	1943	1
Bin	RX_ERR_CTR(4)	0	1	501	1
Bin	RX_ERR_CTR(4)	1	0	2101	1
Bin	RX_ERR_CTR(3)	0	1	680	1
Bin	RX_ERR_CTR(3)	1	0	2280	1
Bin	RX_ERR_CTR(2)	0	1	639	1
Bin	RX_ERR_CTR(2)	1	0	2240	1
Bin	RX_ERR_CTR(1)	0	1	1198	1
Bin	RX_ERR_CTR(1)	1	0	2799	1
Bin	RX_ERR_CTR(0)	0	1	11242	1
Bin	RX_ERR_CTR(0)	1	0	12836	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	NORM_ERR_CTR(15)	0	1	67	1
Bin	NORM_ERR_CTR(15)	1	0	1665	1
Bin	NORM_ERR_CTR(14)	0	1	65	1
Bin	NORM_ERR_CTR(14)	1	0	1663	1
Bin	NORM_ERR_CTR(13)	0	1	66	1
Bin	NORM_ERR_CTR(13)	1	0	1662	1
Bin	NORM_ERR_CTR(12)	0	1	61	1
Bin	NORM_ERR_CTR(12)	1	0	1659	1
Bin	NORM_ERR_CTR(11)	0	1	71	1
Bin	NORM_ERR_CTR(11)	1	0	1670	1
Bin	NORM_ERR_CTR(10)	0	1	67	1
Bin	NORM_ERR_CTR(10)	1	0	1665	1
Bin	NORM_ERR_CTR(9)	0	1	54	1
Bin	NORM_ERR_CTR(9)	1	0	1654	1
Bin	NORM_ERR_CTR(8)	0	1	71	1
Bin	NORM_ERR_CTR(8)	1	0	1668	1
Bin	NORM_ERR_CTR(7)	0	1	83	1
Bin	NORM_ERR_CTR(7)	1	0	1682	1
Bin	NORM_ERR_CTR(6)	0	1	97	1
Bin	NORM_ERR_CTR(6)	1	0	1695	1
Bin	NORM_ERR_CTR(5)	0	1	150	1
Bin	NORM_ERR_CTR(5)	1	0	1747	1
Bin	NORM_ERR_CTR(4)	0	1	271	1
Bin	NORM_ERR_CTR(4)	1	0	1869	1
Bin	NORM_ERR_CTR(3)	0	1	605	1
Bin	NORM_ERR_CTR(3)	1	0	2200	1
Bin	NORM_ERR_CTR(2)	0	1	1369	1
Bin	NORM_ERR_CTR(2)	1	0	2967	1
Bin	NORM_ERR_CTR(1)	0	1	3083	1
Bin	NORM_ERR_CTR(1)	1	0	4677	1
Bin	NORM_ERR_CTR(0)	0	1	11506	1
Bin	NORM_ERR_CTR(0)	1	0	13100	1
Bin	DATA_ERR_CTR(15)	0	1	59	1
Bin	DATA_ERR_CTR(15)	1	0	1657	1
Bin	DATA_ERR_CTR(14)	0	1	68	1
Bin	DATA_ERR_CTR(14)	1	0	1666	1
Bin	DATA_ERR_CTR(13)	0	1	70	1
Bin	DATA_ERR_CTR(13)	1	0	1669	1
Bin	DATA_ERR_CTR(12)	0	1	66	1
Bin	DATA_ERR_CTR(12)	1	0	1665	1
Bin	DATA_ERR_CTR(11)	0	1	63	1
Bin	DATA_ERR_CTR(11)	1	0	1663	1
Bin	DATA_ERR_CTR(10)	0	1	68	1
Bin	DATA_ERR_CTR(10)	1	0	1666	1
Bin	DATA_ERR_CTR(9)	0	1	77	1
Bin	DATA_ERR_CTR(9)	1	0	1674	1
Bin	DATA_ERR_CTR(8)	0	1	90	1
Bin	DATA_ERR_CTR(8)	1	0	1688	1
Bin	DATA_ERR_CTR(7)	0	1	99	1
Bin	DATA_ERR_CTR(7)	1	0	1698	1
Bin	DATA_ERR_CTR(6)	0	1	126	1
Bin	DATA_ERR_CTR(6)	1	0	1723	1
Bin	DATA_ERR_CTR(5)	0	1	212	1
Bin	DATA_ERR_CTR(5)	1	0	1809	1
Bin	DATA_ERR_CTR(4)	0	1	363	1
Bin	DATA_ERR_CTR(4)	1	0	1962	1
Bin	DATA_ERR_CTR(3)	0	1	679	1
Bin	DATA_ERR_CTR(3)	1	0	2278	1
Bin	DATA_ERR_CTR(2)	0	1	1288	1
Bin	DATA_ERR_CTR(2)	1	0	2888	1
Bin	DATA_ERR_CTR(1)	0	1	2512	1
Bin	DATA_ERR_CTR(1)	1	0	4112	1
Bin	DATA_ERR_CTR(0)	0	1	5598	1
Bin	DATA_ERR_CTR(0)	1	0	7196	1
Bin	ERR_TYPE(2)	0	1	964	1
Bin	ERR_TYPE(2)	1	0	2564	1
Bin	ERR_TYPE(1)	0	1	1234	1
Bin	ERR_TYPE(1)	1	0	2833	1
Bin	ERR_TYPE(0)	0	1	336	1
Bin	ERR_TYPE(0)	1	0	1936	1
Bin	ERR_ERP	0	1	290	1
Bin	ERR_ERP	1	0	1891	1
Bin	ERR_POS(3)	0	1	4188	1
Bin	ERR_POS(3)	1	0	2595	1
Bin	ERR_POS(2)	0	1	4421	1
Bin	ERR_POS(2)	1	0	2821	1
Bin	ERR_POS(1)	0	1	3743	1
Bin	ERR_POS(1)	1	0	2146	1
Bin	ERR_POS(0)	0	1	2941	1
Bin	ERR_POS(0)	1	0	1341	1
Bin	RETR_CTR(3)	0	1	54	1
Bin	RETR_CTR(3)	1	0	1655	1
Bin	RETR_CTR(2)	0	1	140	1
Bin	RETR_CTR(2)	1	0	1741	1
Bin	RETR_CTR(1)	0	1	257	1
Bin	RETR_CTR(1)	1	0	1858	1
Bin	RETR_CTR(0)	0	1	642	1
Bin	RETR_CTR(0)	1	0	2242	1
Bin	ALC_BIT(4)	0	1	68	1
Bin	ALC_BIT(4)	1	0	1667	1
Bin	ALC_BIT(3)	0	1	89	1
Bin	ALC_BIT(3)	1	0	1688	1
Bin	ALC_BIT(2)	0	1	102	1
Bin	ALC_BIT(2)	1	0	1701	1
Bin	ALC_BIT(1)	0	1	170	1
Bin	ALC_BIT(1)	1	0	1769	1
Bin	ALC_BIT(0)	0	1	297	1
Bin	ALC_BIT(0)	1	0	1896	1
Bin	ALC_ID_FIELD(2)	0	1	35	1
Bin	ALC_ID_FIELD(2)	1	0	1636	1
Bin	ALC_ID_FIELD(1)	0	1	41	1
Bin	ALC_ID_FIELD(1)	1	0	1640	1
Bin	ALC_ID_FIELD(0)	0	1	92	1
Bin	ALC_ID_FIELD(0)	1	0	1693	1
Bin	RX_FRAME_CTR(31)	0	1	53	1
Bin	RX_FRAME_CTR(31)	1	0	1652	1
Bin	RX_FRAME_CTR(30)	0	1	56	1
Bin	RX_FRAME_CTR(30)	1	0	1656	1
Bin	RX_FRAME_CTR(29)	0	1	51	1
Bin	RX_FRAME_CTR(29)	1	0	1650	1
Bin	RX_FRAME_CTR(28)	0	1	50	1
Bin	RX_FRAME_CTR(28)	1	0	1648	1
Bin	RX_FRAME_CTR(27)	0	1	53	1
Bin	RX_FRAME_CTR(27)	1	0	1652	1
Bin	RX_FRAME_CTR(26)	0	1	49	1
Bin	RX_FRAME_CTR(26)	1	0	1650	1
Bin	RX_FRAME_CTR(25)	0	1	49	1
Bin	RX_FRAME_CTR(25)	1	0	1647	1
Bin	RX_FRAME_CTR(24)	0	1	57	1
Bin	RX_FRAME_CTR(24)	1	0	1656	1
Bin	RX_FRAME_CTR(23)	0	1	49	1
Bin	RX_FRAME_CTR(23)	1	0	1650	1
Bin	RX_FRAME_CTR(22)	0	1	49	1
Bin	RX_FRAME_CTR(22)	1	0	1650	1
Bin	RX_FRAME_CTR(21)	0	1	54	1
Bin	RX_FRAME_CTR(21)	1	0	1653	1
Bin	RX_FRAME_CTR(20)	0	1	57	1
Bin	RX_FRAME_CTR(20)	1	0	1656	1
Bin	RX_FRAME_CTR(19)	0	1	53	1
Bin	RX_FRAME_CTR(19)	1	0	1651	1
Bin	RX_FRAME_CTR(18)	0	1	53	1
Bin	RX_FRAME_CTR(18)	1	0	1652	1
Bin	RX_FRAME_CTR(17)	0	1	55	1
Bin	RX_FRAME_CTR(17)	1	0	1654	1
Bin	RX_FRAME_CTR(16)	0	1	54	1
Bin	RX_FRAME_CTR(16)	1	0	1653	1
Bin	RX_FRAME_CTR(15)	0	1	54	1
Bin	RX_FRAME_CTR(15)	1	0	1651	1
Bin	RX_FRAME_CTR(14)	0	1	47	1
Bin	RX_FRAME_CTR(14)	1	0	1647	1
Bin	RX_FRAME_CTR(13)	0	1	57	1
Bin	RX_FRAME_CTR(13)	1	0	1656	1
Bin	RX_FRAME_CTR(12)	0	1	61	1
Bin	RX_FRAME_CTR(12)	1	0	1660	1
Bin	RX_FRAME_CTR(11)	0	1	50	1
Bin	RX_FRAME_CTR(11)	1	0	1648	1
Bin	RX_FRAME_CTR(10)	0	1	54	1
Bin	RX_FRAME_CTR(10)	1	0	1652	1
Bin	RX_FRAME_CTR(9)	0	1	53	1
Bin	RX_FRAME_CTR(9)	1	0	1651	1
Bin	RX_FRAME_CTR(8)	0	1	66	1
Bin	RX_FRAME_CTR(8)	1	0	1665	1
Bin	RX_FRAME_CTR(7)	0	1	87	1
Bin	RX_FRAME_CTR(7)	1	0	1686	1
Bin	RX_FRAME_CTR(6)	0	1	113	1
Bin	RX_FRAME_CTR(6)	1	0	1712	1
Bin	RX_FRAME_CTR(5)	0	1	215	1
Bin	RX_FRAME_CTR(5)	1	0	1814	1
Bin	RX_FRAME_CTR(4)	0	1	353	1
Bin	RX_FRAME_CTR(4)	1	0	1953	1
Bin	RX_FRAME_CTR(3)	0	1	747	1
Bin	RX_FRAME_CTR(3)	1	0	2345	1
Bin	RX_FRAME_CTR(2)	0	1	1493	1
Bin	RX_FRAME_CTR(2)	1	0	3092	1
Bin	RX_FRAME_CTR(1)	0	1	2963	1
Bin	RX_FRAME_CTR(1)	1	0	4561	1
Bin	RX_FRAME_CTR(0)	0	1	5921	1
Bin	RX_FRAME_CTR(0)	1	0	7521	1
Bin	TX_FRAME_CTR(31)	0	1	101	1
Bin	TX_FRAME_CTR(31)	1	0	1702	1
Bin	TX_FRAME_CTR(30)	0	1	106	1
Bin	TX_FRAME_CTR(30)	1	0	1707	1
Bin	TX_FRAME_CTR(29)	0	1	110	1
Bin	TX_FRAME_CTR(29)	1	0	1711	1
Bin	TX_FRAME_CTR(28)	0	1	98	1
Bin	TX_FRAME_CTR(28)	1	0	1699	1
Bin	TX_FRAME_CTR(27)	0	1	105	1
Bin	TX_FRAME_CTR(27)	1	0	1706	1
Bin	TX_FRAME_CTR(26)	0	1	101	1
Bin	TX_FRAME_CTR(26)	1	0	1702	1
Bin	TX_FRAME_CTR(25)	0	1	99	1
Bin	TX_FRAME_CTR(25)	1	0	1700	1
Bin	TX_FRAME_CTR(24)	0	1	97	1
Bin	TX_FRAME_CTR(24)	1	0	1698	1
Bin	TX_FRAME_CTR(23)	0	1	102	1
Bin	TX_FRAME_CTR(23)	1	0	1703	1
Bin	TX_FRAME_CTR(22)	0	1	100	1
Bin	TX_FRAME_CTR(22)	1	0	1701	1
Bin	TX_FRAME_CTR(21)	0	1	105	1
Bin	TX_FRAME_CTR(21)	1	0	1706	1
Bin	TX_FRAME_CTR(20)	0	1	108	1
Bin	TX_FRAME_CTR(20)	1	0	1709	1
Bin	TX_FRAME_CTR(19)	0	1	97	1
Bin	TX_FRAME_CTR(19)	1	0	1698	1
Bin	TX_FRAME_CTR(18)	0	1	98	1
Bin	TX_FRAME_CTR(18)	1	0	1699	1
Bin	TX_FRAME_CTR(17)	0	1	105	1
Bin	TX_FRAME_CTR(17)	1	0	1706	1
Bin	TX_FRAME_CTR(16)	0	1	111	1
Bin	TX_FRAME_CTR(16)	1	0	1712	1
Bin	TX_FRAME_CTR(15)	0	1	102	1
Bin	TX_FRAME_CTR(15)	1	0	1703	1
Bin	TX_FRAME_CTR(14)	0	1	105	1
Bin	TX_FRAME_CTR(14)	1	0	1706	1
Bin	TX_FRAME_CTR(13)	0	1	91	1
Bin	TX_FRAME_CTR(13)	1	0	1692	1
Bin	TX_FRAME_CTR(12)	0	1	99	1
Bin	TX_FRAME_CTR(12)	1	0	1700	1
Bin	TX_FRAME_CTR(11)	0	1	98	1
Bin	TX_FRAME_CTR(11)	1	0	1699	1
Bin	TX_FRAME_CTR(10)	0	1	96	1
Bin	TX_FRAME_CTR(10)	1	0	1697	1
Bin	TX_FRAME_CTR(9)	0	1	106	1
Bin	TX_FRAME_CTR(9)	1	0	1707	1
Bin	TX_FRAME_CTR(8)	0	1	104	1
Bin	TX_FRAME_CTR(8)	1	0	1705	1
Bin	TX_FRAME_CTR(7)	0	1	103	1
Bin	TX_FRAME_CTR(7)	1	0	1704	1
Bin	TX_FRAME_CTR(6)	0	1	108	1
Bin	TX_FRAME_CTR(6)	1	0	1709	1
Bin	TX_FRAME_CTR(5)	0	1	109	1
Bin	TX_FRAME_CTR(5)	1	0	1710	1
Bin	TX_FRAME_CTR(4)	0	1	152	1
Bin	TX_FRAME_CTR(4)	1	0	1753	1
Bin	TX_FRAME_CTR(3)	0	1	258	1
Bin	TX_FRAME_CTR(3)	1	0	1859	1
Bin	TX_FRAME_CTR(2)	0	1	619	1
Bin	TX_FRAME_CTR(2)	1	0	2220	1
Bin	TX_FRAME_CTR(1)	0	1	1052	1
Bin	TX_FRAME_CTR(1)	1	0	2653	1
Bin	TX_FRAME_CTR(0)	0	1	2203	1
Bin	TX_FRAME_CTR(0)	1	0	3804	1
Bin	BST_CTR(2)	0	1	33452	1
Bin	BST_CTR(2)	1	0	35053	1
Bin	BST_CTR(1)	0	1	70940	1
Bin	BST_CTR(1)	1	0	72538	1
Bin	BST_CTR(0)	0	1	141315	1
Bin	BST_CTR(0)	1	0	142914	1
Bin	DST_CTR(2)	0	1	117682	1
Bin	DST_CTR(2)	1	0	119283	1
Bin	DST_CTR(1)	0	1	242662	1
Bin	DST_CTR(1)	1	0	244257	1
Bin	DST_CTR(0)	0	1	484884	1
Bin	DST_CTR(0)	1	0	486480	1
Bin	STATUS_EWL	0	1	778	1
Bin	STATUS_EWL	1	0	2378	1

---

Port:

 PC_DBG

	Element	From	To	Count	Threshold
Bin	IS_SOF	0	1	24924	1
Bin	IS_SOF	1	0	26525	1
Bin	IS_ARBITRATION	0	1	55723	1
Bin	IS_ARBITRATION	1	0	57324	1
Bin	IS_CONTROL	0	1	50970	1
Bin	IS_CONTROL	1	0	52571	1
Bin	IS_DATA	0	1	36820	1
Bin	IS_DATA	1	0	38421	1
Bin	IS_STUFF_COUNT	0	1	13502	1
Bin	IS_STUFF_COUNT	1	0	15103	1
Bin	IS_CRC	0	1	31213	1
Bin	IS_CRC	1	0	32814	1
Bin	IS_CRC_DELIM	0	1	29735	1
Bin	IS_CRC_DELIM	1	0	31336	1
Bin	IS_ACK	0	1	29588	1
Bin	IS_ACK	1	0	31189	1
Bin	IS_ACK_DELIM	0	1	28165	1
Bin	IS_ACK_DELIM	1	0	29766	1
Bin	IS_EOF	0	1	27273	1
Bin	IS_EOF	1	0	28874	1
Bin	IS_OVERLOAD	0	1	529	1
Bin	IS_OVERLOAD	1	0	2130	1
Bin	IS_ERR	0	1	27135	1
Bin	IS_ERR	1	0	28729	1
Bin	IS_INTERMISSION	0	1	51716	1
Bin	IS_INTERMISSION	1	0	53316	1
Bin	IS_SUSPEND	0	1	2779	1
Bin	IS_SUSPEND	1	0	4380	1

---

Port:

 TRAN_FRAME_TEST

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	74	1
Bin	TPRM(4)	1	0	3283	1
Bin	TPRM(3)	0	1	169	1
Bin	TPRM(3)	1	0	1814	1
Bin	TPRM(2)	0	1	246	1
Bin	TPRM(2)	1	0	1891	1
Bin	TPRM(1)	0	1	458	1
Bin	TPRM(1)	1	0	2103	1
Bin	TPRM(0)	0	1	645	1
Bin	TPRM(0)	1	0	2290	1

---

Port:

 TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25275	1
Bin	LOCK	1	0	26876	1
Bin	VALID	0	1	11112	1
Bin	VALID	1	0	12713	1
Bin	ERR	0	1	4262	1
Bin	ERR	1	0	5863	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9436	1
Bin	FAILED	1	0	11037	1

---

Port:

 TXTB_CLK_EN

	From	To	Count	Threshold
Bin	0	1	79820	1
Bin	1	0	81421	1

---

Port:

 REC_IDENT

	Element	From	To	Count	Threshold
Bin	(28)	0	1	37958	1
Bin	(28)	1	0	31904	1
Bin	(27)	0	1	23451	1
Bin	(27)	1	0	18485	1
Bin	(26)	0	1	35197	1
Bin	(26)	1	0	30734	1
Bin	(25)	0	1	23455	1
Bin	(25)	1	0	18907	1
Bin	(24)	0	1	35024	1
Bin	(24)	1	0	30140	1
Bin	(23)	0	1	28038	1
Bin	(23)	1	0	22073	1
Bin	(22)	0	1	38177	1
Bin	(22)	1	0	32473	1
Bin	(21)	0	1	26666	1
Bin	(21)	1	0	21346	1
Bin	(20)	0	1	34372	1
Bin	(20)	1	0	29680	1
Bin	(19)	0	1	26814	1
Bin	(19)	1	0	21432	1
Bin	(18)	0	1	36475	1
Bin	(18)	1	0	31537	1
Bin	(17)	0	1	6354	1
Bin	(17)	1	0	73134	1
Bin	(16)	0	1	7666	1
Bin	(16)	1	0	76181	1
Bin	(15)	0	1	8076	1
Bin	(15)	1	0	76311	1
Bin	(14)	0	1	8012	1
Bin	(14)	1	0	76870	1
Bin	(13)	0	1	6090	1
Bin	(13)	1	0	73160	1
Bin	(12)	0	1	6063	1
Bin	(12)	1	0	72708	1
Bin	(11)	0	1	6784	1
Bin	(11)	1	0	74963	1
Bin	(10)	0	1	7457	1
Bin	(10)	1	0	75754	1
Bin	(9)	0	1	6222	1
Bin	(9)	1	0	72961	1
Bin	(8)	0	1	7533	1
Bin	(8)	1	0	75953	1
Bin	(7)	0	1	8151	1
Bin	(7)	1	0	77151	1
Bin	(6)	0	1	6815	1
Bin	(6)	1	0	74206	1
Bin	(5)	0	1	6928	1
Bin	(5)	1	0	74300	1
Bin	(4)	0	1	7556	1
Bin	(4)	1	0	76575	1
Bin	(3)	0	1	7327	1
Bin	(3)	1	0	75514	1
Bin	(2)	0	1	8887	1
Bin	(2)	1	0	78980	1
Bin	(1)	0	1	7701	1
Bin	(1)	1	0	76297	1
Bin	(0)	0	1	6473	1
Bin	(0)	1	0	73851	1

---

Port:

 REC_DLC

	Element	From	To	Count	Threshold
Bin	(3)	0	1	21342	1
Bin	(3)	1	0	59508	1
Bin	(2)	0	1	22108	1
Bin	(2)	1	0	28071	1
Bin	(1)	0	1	21797	1
Bin	(1)	1	0	27434	1
Bin	(0)	0	1	28542	1
Bin	(0)	1	0	34415	1

---

Port:

 REC_IDENT_TYPE

	From	To	Count	Threshold
Bin	0	1	17628	1
Bin	1	0	19226	1

---

Port:

 REC_FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	28884	1
Bin	1	0	30480	1

---

Port:

 REC_LBPF

	From	To	Count	Threshold
Bin	0	1	180	1
Bin	1	0	1781	1

---

Port:

 REC_IS_RTR

	From	To	Count	Threshold
Bin	0	1	21837	1
Bin	1	0	23436	1

---

Port:

 REC_BRS

	From	To	Count	Threshold
Bin	0	1	20399	1
Bin	1	0	21995	1

---

Port:

 REC_ESI

	From	To	Count	Threshold
Bin	0	1	2524	1
Bin	1	0	4123	1

---

Port:

 REC_IVLD

	From	To	Count	Threshold
Bin	0	1	50926	1
Bin	1	0	52518	1

---

Port:

 REC_VALID

	From	To	Count	Threshold
Bin	0	1	15178	1
Bin	1	0	16779	1

---

Port:

 STORE_METADATA

	From	To	Count	Threshold
Bin	0	1	28539	1
Bin	1	0	30140	1

---

Port:

 STORE_DATA

	From	To	Count	Threshold
Bin	0	1	88436	1
Bin	1	0	90037	1

---

Port:

 STORE_DATA_WORD

	Element	From	To	Count	Threshold
Bin	(31)	0	1	240582	1
Bin	(31)	1	0	242180	1
Bin	(30)	0	1	247304	1
Bin	(30)	1	0	248901	1
Bin	(29)	0	1	258514	1
Bin	(29)	1	0	260108	1
Bin	(28)	0	1	265752	1
Bin	(28)	1	0	267351	1
Bin	(27)	0	1	276396	1
Bin	(27)	1	0	277993	1
Bin	(26)	0	1	284428	1
Bin	(26)	1	0	286025	1
Bin	(25)	0	1	292258	1
Bin	(25)	1	0	293853	1
Bin	(24)	0	1	300482	1
Bin	(24)	1	0	302081	1
Bin	(23)	0	1	288578	1
Bin	(23)	1	0	290176	1
Bin	(22)	0	1	295744	1
Bin	(22)	1	0	297345	1
Bin	(21)	0	1	304275	1
Bin	(21)	1	0	305870	1
Bin	(20)	0	1	311864	1
Bin	(20)	1	0	313464	1
Bin	(19)	0	1	322864	1
Bin	(19)	1	0	324460	1
Bin	(18)	0	1	331611	1
Bin	(18)	1	0	333207	1
Bin	(17)	0	1	337780	1
Bin	(17)	1	0	339379	1
Bin	(16)	0	1	344233	1
Bin	(16)	1	0	345833	1
Bin	(15)	0	1	385458	1
Bin	(15)	1	0	387057	1
Bin	(14)	0	1	399109	1
Bin	(14)	1	0	400706	1
Bin	(13)	0	1	408432	1
Bin	(13)	1	0	410028	1
Bin	(12)	0	1	419557	1
Bin	(12)	1	0	421153	1
Bin	(11)	0	1	431918	1
Bin	(11)	1	0	433513	1
Bin	(10)	0	1	443737	1
Bin	(10)	1	0	445331	1
Bin	(9)	0	1	453415	1
Bin	(9)	1	0	455012	1
Bin	(8)	0	1	465347	1
Bin	(8)	1	0	466943	1
Bin	(7)	0	1	511984	1
Bin	(7)	1	0	513578	1
Bin	(6)	0	1	523026	1
Bin	(6)	1	0	524619	1
Bin	(5)	0	1	534226	1
Bin	(5)	1	0	535822	1
Bin	(4)	0	1	544724	1
Bin	(4)	1	0	546318	1
Bin	(3)	0	1	554817	1
Bin	(3)	1	0	556410	1
Bin	(2)	0	1	566357	1
Bin	(2)	1	0	567950	1
Bin	(1)	0	1	577627	1
Bin	(1)	1	0	579219	1
Bin	(0)	0	1	586771	1
Bin	(0)	1	0	588363	1

---

Port:

 REC_ABORT

	From	To	Count	Threshold
Bin	0	1	31302	1
Bin	1	0	32903	1

---

Port:

 SOF_PULSE

	From	To	Count	Threshold
Bin	0	1	80686	1
Bin	1	0	82287	1

---

Port:

 ARBITRATION_LOST

	From	To	Count	Threshold
Bin	0	1	1171	1
Bin	1	0	2772	1

---

Port:

 TRAN_VALID

	From	To	Count	Threshold
Bin	0	1	11112	1
Bin	1	0	12713	1

---

Port:

 BR_SHIFTED

	From	To	Count	Threshold
Bin	0	1	47648	1
Bin	1	0	49249	1

---

Port:

 ERR_DETECTED

	From	To	Count	Threshold
Bin	0	1	124470	1
Bin	1	0	126071	1

---

Port:

 FCS_CHANGED

	From	To	Count	Threshold
Bin	0	1	15983	1
Bin	1	0	17584	1

---

Port:

 ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold
Bin	0	1	3156	1
Bin	1	0	4757	1

---

Port:

 SYNC_CONTROL

	Element	From	To	Count	Threshold
Bin	(1)	0	1	100230	1
Bin	(1)	1	0	100223	1
Bin	(0)	0	1	92680	1
Bin	(0)	1	0	92687	1

---

Port:

 NO_POS_RESYNC

	From	To	Count	Threshold
Bin	0	1	632200	1
Bin	1	0	633797	1

---

Port:

 SP_CONTROL

	Element	From	To	Count	Threshold
Bin	(1)	0	1	3434	1
Bin	(1)	1	0	5035	1
Bin	(0)	0	1	25858	1
Bin	(0)	1	0	27459	1

---

Port:

 NBT_CTRS_EN

	From	To	Count	Threshold
Bin	0	1	6483	1
Bin	1	0	8072	1

---

Port:

 DBT_CTRS_EN

	From	To	Count	Threshold
Bin	0	1	67597	1
Bin	1	0	69198	1

---

Port:

 TX_DATA_WBS

	From	To	Count	Threshold
Bin	0	1	633797	1
Bin	1	0	632200	1

---

Port:

 SSP_RESET

	From	To	Count	Threshold
Bin	0	1	33156	1
Bin	1	0	34757	1

---

Port:

 TRAN_DELAY_MEAS

	From	To	Count	Threshold
Bin	0	1	37191	1
Bin	1	0	38792	1

---

Port:

 BTMC_RESET

	From	To	Count	Threshold
Bin	0	1	28575	1
Bin	1	0	30176	1

---

Port:

 DBT_MEASURE_START

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

---

Port:

 GEN_FIRST_SSP

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

---

Port:

 BIT_ERR_ENABLE

	From	To	Count	Threshold
Bin	0	1	67374	1
Bin	1	0	65781	1

---

Port:

 PC_RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10359813	1
Bin	1	0	10361414	1

---

Signal:

 ALC_ALC_BIT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	68	1
Bin	(4)	1	0	1667	1
Bin	(3)	0	1	89	1
Bin	(3)	1	0	1688	1
Bin	(2)	0	1	102	1
Bin	(2)	1	0	1701	1
Bin	(1)	0	1	170	1
Bin	(1)	1	0	1769	1
Bin	(0)	0	1	297	1
Bin	(0)	1	0	1896	1

---

Signal:

 ALC_ALC_ID_FIELD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	35	1
Bin	(2)	1	0	1636	1
Bin	(1)	0	1	41	1
Bin	(1)	1	0	1640	1
Bin	(0)	0	1	92	1
Bin	(0)	1	0	1693	1

---

Signal:

 ERR_CAPT_ERR_TYPE

	Element	From	To	Count	Threshold
Bin	(2)	0	1	964	1
Bin	(2)	1	0	2564	1
Bin	(1)	0	1	1234	1
Bin	(1)	1	0	2833	1
Bin	(0)	0	1	336	1
Bin	(0)	1	0	1936	1

---

Signal:

 ERR_CAPT_ERR_POS

	Element	From	To	Count	Threshold
Bin	(3)	0	1	4188	1
Bin	(3)	1	0	2595	1
Bin	(2)	0	1	4421	1
Bin	(2)	1	0	2821	1
Bin	(1)	0	1	3743	1
Bin	(1)	1	0	2146	1
Bin	(0)	0	1	2941	1
Bin	(0)	1	0	1341	1

---

Signal:

 ERR_CAPT_ERR_ERP

	From	To	Count	Threshold
Bin	0	1	290	1
Bin	1	0	1891	1

---

Signal:

 IS_TRANSMITTER

	From	To	Count	Threshold
Bin	0	1	20317	1
Bin	1	0	21917	1

---

Signal:

 IS_RECEIVER

	From	To	Count	Threshold
Bin	0	1	30908	1
Bin	1	0	32502	1

---

Signal:

 IS_IDLE

	From	To	Count	Threshold
Bin	0	1	55892	1
Bin	1	0	57490	1

---

Signal:

 ARBITRATION_LOST_I

	From	To	Count	Threshold
Bin	0	1	1171	1
Bin	1	0	2772	1

---

Signal:

 SET_TRANSMITTER

	From	To	Count	Threshold
Bin	0	1	40289	1
Bin	1	0	41890	1

---

Signal:

 SET_RECEIVER

	From	To	Count	Threshold
Bin	0	1	30487	1
Bin	1	0	32088	1

---

Signal:

 SET_IDLE

	From	To	Count	Threshold
Bin	0	1	96579	1
Bin	1	0	98180	1

---

Signal:

 IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8426	1
Bin	1	0	8415	1

---

Signal:

 IS_ERR_PASSIVE

	From	To	Count	Threshold
Bin	0	1	761	1
Bin	1	0	2362	1

---

Signal:

 IS_BUS_OFF_I

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8238	1

---

Signal:

 ERR_DETECTED_I

	From	To	Count	Threshold
Bin	0	1	124470	1
Bin	1	0	126071	1

---

Signal:

 PRIMARY_ERR

	From	To	Count	Threshold
Bin	0	1	22770	1
Bin	1	0	24371	1

---

Signal:

 ACT_ERR_OVR_FLAG

	From	To	Count	Threshold
Bin	0	1	19592	1
Bin	1	0	21189	1

---

Signal:

 ERR_DELIM_LATE

	From	To	Count	Threshold
Bin	0	1	390	1
Bin	1	0	1991	1

---

Signal:

 SET_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6637	1
Bin	1	0	8238	1

---

Signal:

 ERR_CTRS_UNCHANGED

	From	To	Count	Threshold
Bin	0	1	795	1
Bin	1	0	2396	1

---

Signal:

 STUFF_ENABLE

	From	To	Count	Threshold
Bin	0	1	25275	1
Bin	1	0	26876	1

---

Signal:

 DESTUFF_ENABLE

	From	To	Count	Threshold
Bin	0	1	55762	1
Bin	1	0	57363	1

---

Signal:

 FIXED_STUFF

	From	To	Count	Threshold
Bin	0	1	13512	1
Bin	1	0	15113	1

---

Signal:

 TX_FRAME_NO_SOF

	From	To	Count	Threshold
Bin	0	1	351	1
Bin	1	0	1952	1

---

Signal:

 DST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	117682	1
Bin	(2)	1	0	119283	1
Bin	(1)	0	1	242662	1
Bin	(1)	1	0	244257	1
Bin	(0)	0	1	484884	1
Bin	(0)	1	0	486480	1

---

Signal:

 BST_CTR

	Element	From	To	Count	Threshold
Bin	(2)	0	1	33452	1
Bin	(2)	1	0	35053	1
Bin	(1)	0	1	70940	1
Bin	(1)	1	0	72538	1
Bin	(0)	0	1	141315	1
Bin	(0)	1	0	142914	1

---

Signal:

 STUFF_ERR

	From	To	Count	Threshold
Bin	0	1	20672	1
Bin	1	0	22273	1

---

Signal:

 CRC_ENABLE

	From	To	Count	Threshold
Bin	0	1	55762	1
Bin	1	0	57363	1

---

Signal:

 CRC_SPEC_ENABLE

	From	To	Count	Threshold
Bin	0	1	113491	1
Bin	1	0	115088	1

---

Signal:

 CRC_CALC_FROM_RX

	From	To	Count	Threshold
Bin	0	1	84440	1
Bin	1	0	86031	1

---

Signal:

 CRC_15

	Element	From	To	Count	Threshold
Bin	(14)	0	1	1456224	1
Bin	(14)	1	0	1457824	1
Bin	(13)	0	1	1412724	1
Bin	(13)	1	0	1414324	1
Bin	(12)	0	1	1427215	1
Bin	(12)	1	0	1428815	1
Bin	(11)	0	1	1440985	1
Bin	(11)	1	0	1442580	1
Bin	(10)	0	1	1455761	1
Bin	(10)	1	0	1457360	1
Bin	(9)	0	1	1446457	1
Bin	(9)	1	0	1448054	1
Bin	(8)	0	1	1461592	1
Bin	(8)	1	0	1463189	1
Bin	(7)	0	1	1492415	1
Bin	(7)	1	0	1494015	1
Bin	(6)	0	1	1426024	1
Bin	(6)	1	0	1427621	1
Bin	(5)	0	1	1440703	1
Bin	(5)	1	0	1442299	1
Bin	(4)	0	1	1453240	1
Bin	(4)	1	0	1454838	1
Bin	(3)	0	1	1455932	1
Bin	(3)	1	0	1457530	1
Bin	(2)	0	1	1446410	1
Bin	(2)	1	0	1448008	1
Bin	(1)	0	1	1462137	1
Bin	(1)	1	0	1463734	1
Bin	(0)	0	1	1474486	1
Bin	(0)	1	0	1476084	1

---

Signal:

 CRC_17

	Element	From	To	Count	Threshold
Bin	(16)	0	1	1743319	1
Bin	(16)	1	0	1744913	1
Bin	(15)	0	1	1753557	1
Bin	(15)	1	0	1755155	1
Bin	(14)	0	1	1766867	1
Bin	(14)	1	0	1768465	1
Bin	(13)	0	1	1762999	1
Bin	(13)	1	0	1764595	1
Bin	(12)	0	1	1700069	1
Bin	(12)	1	0	1701667	1
Bin	(11)	0	1	1716955	1
Bin	(11)	1	0	1718553	1
Bin	(10)	0	1	1661649	1
Bin	(10)	1	0	1663248	1
Bin	(9)	0	1	1675901	1
Bin	(9)	1	0	1677499	1
Bin	(8)	0	1	1688782	1
Bin	(8)	1	0	1690380	1
Bin	(7)	0	1	1702291	1
Bin	(7)	1	0	1703889	1
Bin	(6)	0	1	1717785	1
Bin	(6)	1	0	1719384	1
Bin	(5)	0	1	1718205	1
Bin	(5)	1	0	1719801	1
Bin	(4)	0	1	1732556	1
Bin	(4)	1	0	1734153	1
Bin	(3)	0	1	1752646	1
Bin	(3)	1	0	1754243	1
Bin	(2)	0	1	1715867	1
Bin	(2)	1	0	1717464	1
Bin	(1)	0	1	1730969	1
Bin	(1)	1	0	1732566	1
Bin	(0)	0	1	1768915	1
Bin	(0)	1	0	1770512	1

---

Signal:

 CRC_21

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1747719	1
Bin	(20)	1	0	1749311	1
Bin	(19)	0	1	1699622	1
Bin	(19)	1	0	1701219	1
Bin	(18)	0	1	1716066	1
Bin	(18)	1	0	1717663	1
Bin	(17)	0	1	1729728	1
Bin	(17)	1	0	1731328	1
Bin	(16)	0	1	1743409	1
Bin	(16)	1	0	1745008	1
Bin	(15)	0	1	1756358	1
Bin	(15)	1	0	1757957	1
Bin	(14)	0	1	1768901	1
Bin	(14)	1	0	1770498	1
Bin	(13)	0	1	1783918	1
Bin	(13)	1	0	1785513	1
Bin	(12)	0	1	1732017	1
Bin	(12)	1	0	1733614	1
Bin	(11)	0	1	1745487	1
Bin	(11)	1	0	1747087	1
Bin	(10)	0	1	1733386	1
Bin	(10)	1	0	1734982	1
Bin	(9)	0	1	1746619	1
Bin	(9)	1	0	1748216	1
Bin	(8)	0	1	1761088	1
Bin	(8)	1	0	1762684	1
Bin	(7)	0	1	1776191	1
Bin	(7)	1	0	1777791	1
Bin	(6)	0	1	1709060	1
Bin	(6)	1	0	1710658	1
Bin	(5)	0	1	1723265	1
Bin	(5)	1	0	1724863	1
Bin	(4)	0	1	1736710	1
Bin	(4)	1	0	1738310	1
Bin	(3)	0	1	1762520	1
Bin	(3)	1	0	1764117	1
Bin	(2)	0	1	1758156	1
Bin	(2)	1	0	1759752	1
Bin	(1)	0	1	1770759	1
Bin	(1)	1	0	1772359	1
Bin	(0)	0	1	1784893	1
Bin	(0)	1	0	1786489	1

---

Signal:

 SP_CONTROL_I

	Element	From	To	Count	Threshold
Bin	(1)	0	1	3434	1
Bin	(1)	1	0	5035	1
Bin	(0)	0	1	25858	1
Bin	(0)	1	0	27459	1

---

Signal:

 SP_CONTROL_Q

	Element	From	To	Count	Threshold
Bin	(1)	0	1	2018	1
Bin	(1)	1	0	3619	1
Bin	(0)	0	1	18381	1
Bin	(0)	1	0	19982	1

---

Signal:

 TRAN_VALID_I

	From	To	Count	Threshold
Bin	0	1	11112	1
Bin	1	0	12713	1

---

Signal:

 REC_VALID_I

	From	To	Count	Threshold
Bin	0	1	15178	1
Bin	1	0	16779	1

---

Signal:

 TX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	246	1
Bin	(8)	1	0	1847	1
Bin	(7)	0	1	506	1
Bin	(7)	1	0	2107	1
Bin	(6)	0	1	504	1
Bin	(6)	1	0	2105	1
Bin	(5)	0	1	787	1
Bin	(5)	1	0	2388	1
Bin	(4)	0	1	1957	1
Bin	(4)	1	0	3557	1
Bin	(3)	0	1	12521	1
Bin	(3)	1	0	14122	1
Bin	(2)	0	1	2978	1
Bin	(2)	1	0	4579	1
Bin	(1)	0	1	3314	1
Bin	(1)	1	0	4915	1
Bin	(0)	0	1	3548	1
Bin	(0)	1	0	5149	1

---

Signal:

 RX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	126	1
Bin	(8)	1	0	1727	1
Bin	(7)	0	1	344	1
Bin	(7)	1	0	1945	1
Bin	(6)	0	1	262	1
Bin	(6)	1	0	1860	1
Bin	(5)	0	1	343	1
Bin	(5)	1	0	1943	1
Bin	(4)	0	1	501	1
Bin	(4)	1	0	2101	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2280	1
Bin	(2)	0	1	639	1
Bin	(2)	1	0	2240	1
Bin	(1)	0	1	1198	1
Bin	(1)	1	0	2799	1
Bin	(0)	0	1	11242	1
Bin	(0)	1	0	12836	1

---

Signal:

 NORM_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	1665	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	1663	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	1662	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	1670	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	1665	1
Bin	(9)	0	1	54	1
Bin	(9)	1	0	1654	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1668	1
Bin	(7)	0	1	83	1
Bin	(7)	1	0	1682	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1695	1
Bin	(5)	0	1	150	1
Bin	(5)	1	0	1747	1
Bin	(4)	0	1	271	1
Bin	(4)	1	0	1869	1
Bin	(3)	0	1	605	1
Bin	(3)	1	0	2200	1
Bin	(2)	0	1	1369	1
Bin	(2)	1	0	2967	1
Bin	(1)	0	1	3083	1
Bin	(1)	1	0	4677	1
Bin	(0)	0	1	11506	1
Bin	(0)	1	0	13100	1

---

Signal:

 DATA_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	59	1
Bin	(15)	1	0	1657	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1666	1
Bin	(13)	0	1	70	1
Bin	(13)	1	0	1669	1
Bin	(12)	0	1	66	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	63	1
Bin	(11)	1	0	1663	1
Bin	(10)	0	1	68	1
Bin	(10)	1	0	1666	1
Bin	(9)	0	1	77	1
Bin	(9)	1	0	1674	1
Bin	(8)	0	1	90	1
Bin	(8)	1	0	1688	1
Bin	(7)	0	1	99	1
Bin	(7)	1	0	1698	1
Bin	(6)	0	1	126	1
Bin	(6)	1	0	1723	1
Bin	(5)	0	1	212	1
Bin	(5)	1	0	1809	1
Bin	(4)	0	1	363	1
Bin	(4)	1	0	1962	1
Bin	(3)	0	1	679	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1288	1
Bin	(2)	1	0	2888	1
Bin	(1)	0	1	2512	1
Bin	(1)	1	0	4112	1
Bin	(0)	0	1	5598	1
Bin	(0)	1	0	7196	1

---

Signal:

 PC_TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11391077	1
Bin	1	0	11392677	1

---

Signal:

 PC_RX_TRIGGER_I

	From	To	Count	Threshold
Bin	0	1	10359813	1
Bin	1	0	10361414	1

---

Signal:

 PC_TX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	645138	1
Bin	1	0	643541	1

---

Signal:

 PC_RX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	1392677	1
Bin	1	0	1391076	1

---

Signal:

 CRC_DATA_TX_WBS

	From	To	Count	Threshold
Bin	0	1	633812	1
Bin	1	0	632215	1

---

Signal:

 CRC_DATA_TX_NBS

	From	To	Count	Threshold
Bin	0	1	645138	1
Bin	1	0	643541	1

---

Signal:

 CRC_DATA_RX_WBS

	From	To	Count	Threshold
Bin	0	1	1397496	1
Bin	1	0	1399086	1

---

Signal:

 CRC_DATA_RX_NBS

	From	To	Count	Threshold
Bin	0	1	1392677	1
Bin	1	0	1391076	1

---

Signal:

 CRC_TRIG_TX_WBS

	From	To	Count	Threshold
Bin	0	1	11423999	1
Bin	1	0	11425599	1

---

Signal:

 CRC_TRIG_TX_NBS

	From	To	Count	Threshold
Bin	0	1	11391077	1
Bin	1	0	11392677	1

---

Signal:

 CRC_TRIG_RX_WBS

	From	To	Count	Threshold
Bin	0	1	11302587	1
Bin	1	0	11304188	1

---

Signal:

 CRC_TRIG_RX_NBS

	From	To	Count	Threshold
Bin	0	1	10359813	1
Bin	1	0	10361414	1

---

Signal:

 BST_DATA_IN

	From	To	Count	Threshold
Bin	0	1	645138	1
Bin	1	0	643541	1

---

Signal:

 BST_DATA_OUT

	From	To	Count	Threshold
Bin	0	1	633812	1
Bin	1	0	632215	1

---

Signal:

 BST_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11391077	1
Bin	1	0	11392677	1

---

Signal:

 DATA_HALT

	From	To	Count	Threshold
Bin	0	1	939896	1
Bin	1	0	941497	1

---

Signal:

 BDS_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1402856	1
Bin	1	0	1401256	1

---

Signal:

 BDS_DATA_OUT

	From	To	Count	Threshold
Bin	0	1	1392677	1
Bin	1	0	1391076	1

---

Signal:

 BDS_TRIGGER

	From	To	Count	Threshold
Bin	0	1	22778488	1
Bin	1	0	22780089	1

---

Signal:

 DESTUFFED

	From	To	Count	Threshold
Bin	0	1	1022424	1
Bin	1	0	1024025	1

---

Signal:

 TX_FRAME_CTR

	Element	From	To	Count	Threshold
Bin	(31)	0	1	101	1
Bin	(31)	1	0	1702	1
Bin	(30)	0	1	106	1
Bin	(30)	1	0	1707	1
Bin	(29)	0	1	110	1
Bin	(29)	1	0	1711	1
Bin	(28)	0	1	98	1
Bin	(28)	1	0	1699	1
Bin	(27)	0	1	105	1
Bin	(27)	1	0	1706	1
Bin	(26)	0	1	101	1
Bin	(26)	1	0	1702	1
Bin	(25)	0	1	99	1
Bin	(25)	1	0	1700	1
Bin	(24)	0	1	97	1
Bin	(24)	1	0	1698	1
Bin	(23)	0	1	102	1
Bin	(23)	1	0	1703	1
Bin	(22)	0	1	100	1
Bin	(22)	1	0	1701	1
Bin	(21)	0	1	105	1
Bin	(21)	1	0	1706	1
Bin	(20)	0	1	108	1
Bin	(20)	1	0	1709	1
Bin	(19)	0	1	97	1
Bin	(19)	1	0	1698	1
Bin	(18)	0	1	98	1
Bin	(18)	1	0	1699	1
Bin	(17)	0	1	105	1
Bin	(17)	1	0	1706	1
Bin	(16)	0	1	111	1
Bin	(16)	1	0	1712	1
Bin	(15)	0	1	102	1
Bin	(15)	1	0	1703	1
Bin	(14)	0	1	105	1
Bin	(14)	1	0	1706	1
Bin	(13)	0	1	91	1
Bin	(13)	1	0	1692	1
Bin	(12)	0	1	99	1
Bin	(12)	1	0	1700	1
Bin	(11)	0	1	98	1
Bin	(11)	1	0	1699	1
Bin	(10)	0	1	96	1
Bin	(10)	1	0	1697	1
Bin	(9)	0	1	106	1
Bin	(9)	1	0	1707	1
Bin	(8)	0	1	104	1
Bin	(8)	1	0	1705	1
Bin	(7)	0	1	103	1
Bin	(7)	1	0	1704	1
Bin	(6)	0	1	108	1
Bin	(6)	1	0	1709	1
Bin	(5)	0	1	109	1
Bin	(5)	1	0	1710	1
Bin	(4)	0	1	152	1
Bin	(4)	1	0	1753	1
Bin	(3)	0	1	258	1
Bin	(3)	1	0	1859	1
Bin	(2)	0	1	619	1
Bin	(2)	1	0	2220	1
Bin	(1)	0	1	1052	1
Bin	(1)	1	0	2653	1
Bin	(0)	0	1	2203	1
Bin	(0)	1	0	3804	1

---

Signal:

 RX_FRAME_CTR

	Element	From	To	Count	Threshold
Bin	(31)	0	1	53	1
Bin	(31)	1	0	1652	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	1656	1
Bin	(29)	0	1	51	1
Bin	(29)	1	0	1650	1
Bin	(28)	0	1	50	1
Bin	(28)	1	0	1648	1
Bin	(27)	0	1	53	1
Bin	(27)	1	0	1652	1
Bin	(26)	0	1	49	1
Bin	(26)	1	0	1650	1
Bin	(25)	0	1	49	1
Bin	(25)	1	0	1647	1
Bin	(24)	0	1	57	1
Bin	(24)	1	0	1656	1
Bin	(23)	0	1	49	1
Bin	(23)	1	0	1650	1
Bin	(22)	0	1	49	1
Bin	(22)	1	0	1650	1
Bin	(21)	0	1	54	1
Bin	(21)	1	0	1653	1
Bin	(20)	0	1	57	1
Bin	(20)	1	0	1656	1
Bin	(19)	0	1	53	1
Bin	(19)	1	0	1651	1
Bin	(18)	0	1	53	1
Bin	(18)	1	0	1652	1
Bin	(17)	0	1	55	1
Bin	(17)	1	0	1654	1
Bin	(16)	0	1	54	1
Bin	(16)	1	0	1653	1
Bin	(15)	0	1	54	1
Bin	(15)	1	0	1651	1
Bin	(14)	0	1	47	1
Bin	(14)	1	0	1647	1
Bin	(13)	0	1	57	1
Bin	(13)	1	0	1656	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1660	1
Bin	(11)	0	1	50	1
Bin	(11)	1	0	1648	1
Bin	(10)	0	1	54	1
Bin	(10)	1	0	1652	1
Bin	(9)	0	1	53	1
Bin	(9)	1	0	1651	1
Bin	(8)	0	1	66	1
Bin	(8)	1	0	1665	1
Bin	(7)	0	1	87	1
Bin	(7)	1	0	1686	1
Bin	(6)	0	1	113	1
Bin	(6)	1	0	1712	1
Bin	(5)	0	1	215	1
Bin	(5)	1	0	1814	1
Bin	(4)	0	1	353	1
Bin	(4)	1	0	1953	1
Bin	(3)	0	1	747	1
Bin	(3)	1	0	2345	1
Bin	(2)	0	1	1493	1
Bin	(2)	1	0	3092	1
Bin	(1)	0	1	2963	1
Bin	(1)	1	0	4561	1
Bin	(0)	0	1	5921	1
Bin	(0)	1	0	7521	1

---

Signal:

 TX_DATA_WBS_I

	From	To	Count	Threshold
Bin	0	1	633797	1
Bin	1	0	632200	1

---

Signal:

 LPB_DOMINANT

	From	To	Count	Threshold
Bin	0	1	1396543	1
Bin	1	0	1394946	1

---

Signal:

 FORM_ERR

	From	To	Count	Threshold
Bin	0	1	87476	1
Bin	1	0	89077	1

---

Signal:

 ACK_ERR

	From	To	Count	Threshold
Bin	0	1	8377	1
Bin	1	0	9978	1

---

Signal:

 CRC_ERR

	From	To	Count	Threshold
Bin	0	1	1616	1
Bin	1	0	3217	1

---

Signal:

 LOAD_INIT_VECT

	From	To	Count	Threshold
Bin	0	1	113459	1
Bin	1	0	115060	1

---

Signal:

 RETR_CTR

	Element	From	To	Count	Threshold
Bin	(3)	0	1	54	1
Bin	(3)	1	0	1655	1
Bin	(2)	0	1	140	1
Bin	(2)	1	0	1741	1
Bin	(1)	0	1	257	1
Bin	(1)	1	0	1858	1
Bin	(0)	0	1	642	1
Bin	(0)	1	0	2242	1

---

Signal:

 DECREMENT_REC

	From	To	Count	Threshold
Bin	0	1	14981	1
Bin	1	0	16582	1

---

Signal:

 BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold
Bin	0	1	8	1
Bin	1	0	1609	1

---

Signal:

 MR_STATUS_PEXS

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1676	1

---

Signal:

 MR_STATUS_EWL

	From	To	Count	Threshold
Bin	0	1	778	1
Bin	1	0	2378	1