Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| PROTOCOL_CONTROL_INST |
100.0 % (1465/1465) |
100.0 % (1078/1078) |
100.0 % (3934/3934) |
100.0 % (1595/1595) |
100.0 % (76/76) |
100.0 % (13/13) |
100.0 % (8161/8161) |
| OPERATION_CONTROL_INST |
100.0 % (28/28) |
100.0 % (32/32) |
100.0 % (24/24) |
100.0 % (32/32) |
100.0 % (8/8) |
N.A. |
100.0 % (124/124) |
| FAULT_CONFINEMENT_INST |
100.0 % (153/153) |
100.0 % (130/130) |
100.0 % (916/916) |
100.0 % (215/215) |
100.0 % (6/6) |
N.A. |
100.0 % (1420/1420) |
| CAN_CRC_INST |
100.0 % (68/68) |
100.0 % (62/62) |
100.0 % (524/524) |
100.0 % (93/93) |
N.A. |
N.A. |
100.0 % (747/747) |
| BIT_STUFFING_INST |
100.0 % (76/76) |
100.0 % (76/76) |
100.0 % (128/128) |
100.0 % (127/127) |
N.A. |
N.A. |
100.0 % (407/407) |
| BIT_DESTUFFING_INST |
100.0 % (71/71) |
100.0 % (76/76) |
100.0 % (140/140) |
100.0 % (123/123) |
N.A. |
N.A. |
100.0 % (410/410) |
| BUS_TRAFFIC_CTRS_GEN |
100.0 % (35/35) |
100.0 % (34/34) |
100.0 % (466/466) |
100.0 % (20/20) |
N.A. |
N.A. |
100.0 % (555/555) |
| TRIGGER_MUX_INST |
100.0 % (27/27) |
100.0 % (26/26) |
100.0 % (56/56) |
100.0 % (52/52) |
N.A. |
N.A. |
100.0 % (161/161) |
| NO_BUS_TRAFFIC_CTRS_GEN |
100.0 % (2/2) |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (2/2) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
Signal assignment statement:
899: lpb_dominant <= rx_data_wbs and bst_data_out; Count: 4065224
Threshold: 1
If statement:
909: bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else
910: lpb_dominant when (mr_mode_bmm = '1') else
911: rx_data_wbs; Count: 6895323
Threshold: 1
Signal assignment statement:
909: bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else Count: 329867
Threshold: 1
Signal assignment statement:
910: lpb_dominant when (mr_mode_bmm = '1') else Count: 1881
Threshold: 1
Signal assignment statement:
911: rx_data_wbs; Count: 6563575
Threshold: 1
If statement:
917: tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else
918: RECESSIVE when (mr_mode_bmm = '1') else
919: bst_data_out; Count: 1285278
Threshold: 1
Signal assignment statement:
917: tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else Count: 8080
Threshold: 1
Signal assignment statement:
918: RECESSIVE when (mr_mode_bmm = '1') else Count: 50
Threshold: 1
Signal assignment statement:
919: bst_data_out; Count: 1277148
Threshold: 1
If statement:
925: no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else
926: '0'; Count: 1270674
Threshold: 1
Signal assignment statement:
925: no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else Count: 633738
Threshold: 1
Signal assignment statement:
926: '0'; Count: 636936
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
909: bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 329867 | 1 |
| Bin | False | 6565456 | 1 |
"if" / "when" / "else" condition:
910: lpb_dominant when (mr_mode_bmm = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1881 | 1 |
| Bin | False | 6563575 | 1 |
"if" / "when" / "else" condition:
917: tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 8080 | 1 |
| Bin | False | 1277198 | 1 |
"if" / "when" / "else" condition:
918: RECESSIVE when (mr_mode_bmm = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 50 | 1 |
| Bin | False | 1277148 | 1 |
"if" / "when" / "else" condition:
925: no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 633738 | 1 |
| Bin | False | 636936 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
Port:
MR_MODE_ACF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
Port:
MR_MODE_STM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1760 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_MODE_FDE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1800 | 1 |
| Bin | 1 | 0 | 200 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
MR_MODE_TSTM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 2626 | 1 |
Port:
MR_MODE_SAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Port:
MR_SETTINGS_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
MR_SETTINGS_NISOFD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
Port:
MR_SETTINGS_RTRTH(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
Port:
MR_SETTINGS_RTRTH(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Port:
MR_SETTINGS_RTRTH(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
Port:
MR_SETTINGS_RTRTH(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Port:
MR_SETTINGS_RTRLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2454 | 1 |
| Bin | 1 | 0 | 4054 | 1 |
Port:
MR_SETTINGS_ILBP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
Port:
MR_SETTINGS_PEX | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1672 | 1 |
Port:
MR_COMMAND_ERCRST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
Port:
MR_COMMAND_RXFCRST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
Port:
MR_COMMAND_TXFCRST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
Port:
MR_COMMAND_CPEXS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
Port:
MR_SSP_CFG_SSP_SRC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
Port:
MR_SSP_CFG_SSP_SRC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 817 | 1 |
| Bin | 1 | 0 | 2407 | 1 |
Port:
MR_EWL_EW_LIMIT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78 | 1 |
| Bin | 1 | 0 | 1678 | 1 |
Port:
MR_EWL_EW_LIMIT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1686 | 1 |
| Bin | 1 | 0 | 86 | 1 |
Port:
MR_EWL_EW_LIMIT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 70 | 1 |
Port:
MR_EWL_EW_LIMIT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
Port:
MR_EWL_EW_LIMIT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
Port:
MR_EWL_EW_LIMIT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
Port:
MR_EWL_EW_LIMIT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
Port:
MR_EWL_EW_LIMIT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
Port:
MR_ERP_ERP_LIMIT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1736 | 1 |
| Bin | 1 | 0 | 136 | 1 |
Port:
MR_ERP_ERP_LIMIT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
Port:
MR_ERP_ERP_LIMIT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
Port:
MR_ERP_ERP_LIMIT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
Port:
MR_ERP_ERP_LIMIT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1626 | 1 |
Port:
MR_ERP_ERP_LIMIT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
Port:
MR_ERP_ERP_LIMIT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
Port:
MR_ERP_ERP_LIMIT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
Port:
MR_CTR_PRES_CTPV(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 264 | 1 |
| Bin | 1 | 0 | 1864 | 1 |
Port:
MR_CTR_PRES_CTPV(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2166 | 1 |
| Bin | 1 | 0 | 3766 | 1 |
Port:
MR_CTR_PRES_CTPV(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 683 | 1 |
| Bin | 1 | 0 | 2283 | 1 |
Port:
MR_CTR_PRES_CTPV(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2181 | 1 |
| Bin | 1 | 0 | 3781 | 1 |
Port:
MR_CTR_PRES_CTPV(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2332 | 1 |
| Bin | 1 | 0 | 3932 | 1 |
Port:
MR_CTR_PRES_CTPV(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 919 | 1 |
| Bin | 1 | 0 | 2519 | 1 |
Port:
MR_CTR_PRES_CTPV(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2414 | 1 |
| Bin | 1 | 0 | 4014 | 1 |
Port:
MR_CTR_PRES_CTPV(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1008 | 1 |
| Bin | 1 | 0 | 2608 | 1 |
Port:
MR_CTR_PRES_CTPV(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
Port:
MR_CTR_PRES_PTX | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18698 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
Port:
MR_CTR_PRES_PRX | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19085 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
Port:
MR_CTR_PRES_ENORM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5942 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
Port:
MR_CTR_PRES_EFD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5942 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
Port:
CC_STAT.IS_ERR_ACTIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8424 | 1 |
| Bin | 1 | 0 | 8415 | 1 |
Port:
CC_STAT.IS_ERR_PASSIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
Port:
CC_STAT.IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8227 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Port:
CC_STAT.IS_TRANSMITTER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19892 | 1 |
| Bin | 1 | 0 | 21492 | 1 |
Port:
CC_STAT.IS_RECEIVER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30888 | 1 |
| Bin | 1 | 0 | 32482 | 1 |
Port:
CC_STAT.IS_IDLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55452 | 1 |
| Bin | 1 | 0 | 57049 | 1 |
Port:
CC_STAT.TX_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 249 | 1 |
| Bin | 1 | 0 | 1849 | 1 |
Port:
CC_STAT.TX_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 521 | 1 |
| Bin | 1 | 0 | 2121 | 1 |
Port:
CC_STAT.TX_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 488 | 1 |
| Bin | 1 | 0 | 2088 | 1 |
Port:
CC_STAT.TX_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 811 | 1 |
| Bin | 1 | 0 | 2411 | 1 |
Port:
CC_STAT.TX_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1931 | 1 |
| Bin | 1 | 0 | 3531 | 1 |
Port:
CC_STAT.TX_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12094 | 1 |
| Bin | 1 | 0 | 13694 | 1 |
Port:
CC_STAT.TX_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2980 | 1 |
| Bin | 1 | 0 | 4580 | 1 |
Port:
CC_STAT.TX_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3318 | 1 |
| Bin | 1 | 0 | 4918 | 1 |
Port:
CC_STAT.TX_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3517 | 1 |
| Bin | 1 | 0 | 5117 | 1 |
Port:
CC_STAT.RX_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 1736 | 1 |
Port:
CC_STAT.RX_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 360 | 1 |
| Bin | 1 | 0 | 1960 | 1 |
Port:
CC_STAT.RX_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 1864 | 1 |
Port:
CC_STAT.RX_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 332 | 1 |
| Bin | 1 | 0 | 1931 | 1 |
Port:
CC_STAT.RX_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 519 | 1 |
| Bin | 1 | 0 | 2119 | 1 |
Port:
CC_STAT.RX_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 686 | 1 |
| Bin | 1 | 0 | 2285 | 1 |
Port:
CC_STAT.RX_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 627 | 1 |
| Bin | 1 | 0 | 2227 | 1 |
Port:
CC_STAT.RX_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1208 | 1 |
| Bin | 1 | 0 | 2808 | 1 |
Port:
CC_STAT.RX_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11221 | 1 |
| Bin | 1 | 0 | 12815 | 1 |
Port:
CC_STAT.STATUS_PEXS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 69 | 1 |
| Bin | 1 | 0 | 1668 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1759 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 1878 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 600 | 1 |
| Bin | 1 | 0 | 2194 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1361 | 1 |
| Bin | 1 | 0 | 2956 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3048 | 1 |
| Bin | 1 | 0 | 4645 | 1 |
Port:
CC_STAT.NORM_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11189 | 1 |
| Bin | 1 | 0 | 12783 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 85 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1701 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 138 | 1 |
| Bin | 1 | 0 | 1735 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 359 | 1 |
| Bin | 1 | 0 | 1956 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 679 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1295 | 1 |
| Bin | 1 | 0 | 2892 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2524 | 1 |
| Bin | 1 | 0 | 4120 | 1 |
Port:
CC_STAT.DATA_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5478 | 1 |
| Bin | 1 | 0 | 7073 | 1 |
Port:
CC_STAT.ERR_TYPE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 793 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
Port:
CC_STAT.ERR_TYPE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1252 | 1 |
| Bin | 1 | 0 | 2850 | 1 |
Port:
CC_STAT.ERR_TYPE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 336 | 1 |
| Bin | 1 | 0 | 1935 | 1 |
Port:
CC_STAT.ERR_ERP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 290 | 1 |
| Bin | 1 | 0 | 1890 | 1 |
Port:
CC_STAT.ERR_POS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4185 | 1 |
| Bin | 1 | 0 | 2591 | 1 |
Port:
CC_STAT.ERR_POS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4402 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
Port:
CC_STAT.ERR_POS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3666 | 1 |
| Bin | 1 | 0 | 2070 | 1 |
Port:
CC_STAT.ERR_POS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2960 | 1 |
| Bin | 1 | 0 | 1361 | 1 |
Port:
CC_STAT.RETR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Port:
CC_STAT.RETR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 132 | 1 |
| Bin | 1 | 0 | 1732 | 1 |
Port:
CC_STAT.RETR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 255 | 1 |
| Bin | 1 | 0 | 1855 | 1 |
Port:
CC_STAT.RETR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Port:
CC_STAT.ALC_BIT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
Port:
CC_STAT.ALC_BIT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1686 | 1 |
Port:
CC_STAT.ALC_BIT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
Port:
CC_STAT.ALC_BIT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 171 | 1 |
| Bin | 1 | 0 | 1769 | 1 |
Port:
CC_STAT.ALC_BIT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 1894 | 1 |
Port:
CC_STAT.ALC_ID_FIELD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
Port:
CC_STAT.ALC_ID_FIELD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1638 | 1 |
Port:
CC_STAT.ALC_ID_FIELD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1648 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 222 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 355 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 746 | 1 |
| Bin | 1 | 0 | 2344 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1495 | 1 |
| Bin | 1 | 0 | 3093 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2959 | 1 |
| Bin | 1 | 0 | 4557 | 1 |
Port:
CC_STAT.RX_FRAME_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5919 | 1 |
| Bin | 1 | 0 | 7518 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108 | 1 |
| Bin | 1 | 0 | 1708 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 1691 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 1729 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 1752 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 1863 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 593 | 1 |
| Bin | 1 | 0 | 2193 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1072 | 1 |
| Bin | 1 | 0 | 2672 | 1 |
Port:
CC_STAT.TX_FRAME_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2211 | 1 |
| Bin | 1 | 0 | 3811 | 1 |
Port:
CC_STAT.BST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33334 | 1 |
| Bin | 1 | 0 | 34934 | 1 |
Port:
CC_STAT.BST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70225 | 1 |
| Bin | 1 | 0 | 71823 | 1 |
Port:
CC_STAT.BST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 140700 | 1 |
| Bin | 1 | 0 | 142298 | 1 |
Port:
CC_STAT.DST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116920 | 1 |
| Bin | 1 | 0 | 118520 | 1 |
Port:
CC_STAT.DST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 241878 | 1 |
| Bin | 1 | 0 | 243473 | 1 |
Port:
CC_STAT.DST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 483649 | 1 |
| Bin | 1 | 0 | 485246 | 1 |
Port:
CC_STAT.STATUS_EWL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 2391 | 1 |
Port:
PC_DBG.IS_SOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24462 | 1 |
| Bin | 1 | 0 | 26062 | 1 |
Port:
PC_DBG.IS_ARBITRATION | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55248 | 1 |
| Bin | 1 | 0 | 56848 | 1 |
Port:
PC_DBG.IS_CONTROL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50561 | 1 |
| Bin | 1 | 0 | 52161 | 1 |
Port:
PC_DBG.IS_DATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
PC_DBG.IS_STUFF_COUNT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13456 | 1 |
| Bin | 1 | 0 | 15056 | 1 |
Port:
PC_DBG.IS_CRC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31170 | 1 |
| Bin | 1 | 0 | 32770 | 1 |
Port:
PC_DBG.IS_CRC_DELIM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29717 | 1 |
| Bin | 1 | 0 | 31317 | 1 |
Port:
PC_DBG.IS_ACK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 29563 | 1 |
| Bin | 1 | 0 | 31163 | 1 |
Port:
PC_DBG.IS_ACK_DELIM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28146 | 1 |
| Bin | 1 | 0 | 29746 | 1 |
Port:
PC_DBG.IS_EOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27259 | 1 |
| Bin | 1 | 0 | 28859 | 1 |
Port:
PC_DBG.IS_OVERLOAD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 529 | 1 |
| Bin | 1 | 0 | 2129 | 1 |
Port:
PC_DBG.IS_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26658 | 1 |
| Bin | 1 | 0 | 28253 | 1 |
Port:
PC_DBG.IS_INTERMISSION | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51238 | 1 |
| Bin | 1 | 0 | 52837 | 1 |
Port:
PC_DBG.IS_SUSPEND | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2324 | 1 |
| Bin | 1 | 0 | 3924 | 1 |
Port:
TRAN_WORD(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8251 | 1 |
| Bin | 1 | 0 | 9851 | 1 |
Port:
TRAN_WORD(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8670 | 1 |
| Bin | 1 | 0 | 10270 | 1 |
Port:
TRAN_WORD(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8250 | 1 |
| Bin | 1 | 0 | 9850 | 1 |
Port:
TRAN_WORD(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26016 | 1 |
| Bin | 1 | 0 | 27616 | 1 |
Port:
TRAN_WORD(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20559 | 1 |
| Bin | 1 | 0 | 22159 | 1 |
Port:
TRAN_WORD(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26228 | 1 |
| Bin | 1 | 0 | 27828 | 1 |
Port:
TRAN_WORD(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21530 | 1 |
| Bin | 1 | 0 | 23130 | 1 |
Port:
TRAN_WORD(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25986 | 1 |
| Bin | 1 | 0 | 27586 | 1 |
Port:
TRAN_WORD(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22777 | 1 |
| Bin | 1 | 0 | 24377 | 1 |
Port:
TRAN_WORD(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25704 | 1 |
| Bin | 1 | 0 | 27304 | 1 |
Port:
TRAN_WORD(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22032 | 1 |
| Bin | 1 | 0 | 23632 | 1 |
Port:
TRAN_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25833 | 1 |
| Bin | 1 | 0 | 27433 | 1 |
Port:
TRAN_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22441 | 1 |
| Bin | 1 | 0 | 24041 | 1 |
Port:
TRAN_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26355 | 1 |
| Bin | 1 | 0 | 27955 | 1 |
Port:
TRAN_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14208 | 1 |
| Bin | 1 | 0 | 15808 | 1 |
Port:
TRAN_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15135 | 1 |
| Bin | 1 | 0 | 16735 | 1 |
Port:
TRAN_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14400 | 1 |
| Bin | 1 | 0 | 16000 | 1 |
Port:
TRAN_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15059 | 1 |
| Bin | 1 | 0 | 16659 | 1 |
Port:
TRAN_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14849 | 1 |
| Bin | 1 | 0 | 16449 | 1 |
Port:
TRAN_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15821 | 1 |
| Bin | 1 | 0 | 17421 | 1 |
Port:
TRAN_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14688 | 1 |
| Bin | 1 | 0 | 16288 | 1 |
Port:
TRAN_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15846 | 1 |
| Bin | 1 | 0 | 17446 | 1 |
Port:
TRAN_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25928 | 1 |
| Bin | 1 | 0 | 27528 | 1 |
Port:
TRAN_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16627 | 1 |
| Bin | 1 | 0 | 18227 | 1 |
Port:
TRAN_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35438 | 1 |
| Bin | 1 | 0 | 37038 | 1 |
Port:
TRAN_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26739 | 1 |
| Bin | 1 | 0 | 28339 | 1 |
Port:
TRAN_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19032 | 1 |
| Bin | 1 | 0 | 20632 | 1 |
Port:
TRAN_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16938 | 1 |
| Bin | 1 | 0 | 18538 | 1 |
Port:
TRAN_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26470 | 1 |
| Bin | 1 | 0 | 28070 | 1 |
Port:
TRAN_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26680 | 1 |
| Bin | 1 | 0 | 28280 | 1 |
Port:
TRAN_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27552 | 1 |
| Bin | 1 | 0 | 29152 | 1 |
Port:
TRAN_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35377 | 1 |
| Bin | 1 | 0 | 36977 | 1 |
Port:
TRAN_DLC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1530 | 1 |
| Bin | 1 | 0 | 3129 | 1 |
Port:
TRAN_DLC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1943 | 1 |
| Bin | 1 | 0 | 3543 | 1 |
Port:
TRAN_DLC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1905 | 1 |
| Bin | 1 | 0 | 3504 | 1 |
Port:
TRAN_DLC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3494 | 1 |
| Bin | 1 | 0 | 5094 | 1 |
Port:
TRAN_IS_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1161 | 1 |
| Bin | 1 | 0 | 2759 | 1 |
Port:
TRAN_IDENT_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2564 | 1 |
| Bin | 1 | 0 | 4164 | 1 |
Port:
TRAN_FRAME_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2708 | 1 |
| Bin | 1 | 0 | 4308 | 1 |
Port:
TRAN_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2008 | 1 |
| Bin | 1 | 0 | 3608 | 1 |
Port:
TRAN_IDENTIFIER(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3946 | 1 |
| Bin | 1 | 0 | 5484 | 1 |
Port:
TRAN_IDENTIFIER(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3920 | 1 |
| Bin | 1 | 0 | 5542 | 1 |
Port:
TRAN_IDENTIFIER(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3792 | 1 |
| Bin | 1 | 0 | 5324 | 1 |
Port:
TRAN_IDENTIFIER(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4128 | 1 |
| Bin | 1 | 0 | 5746 | 1 |
Port:
TRAN_IDENTIFIER(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3888 | 1 |
| Bin | 1 | 0 | 5425 | 1 |
Port:
TRAN_IDENTIFIER(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4157 | 1 |
| Bin | 1 | 0 | 5770 | 1 |
Port:
TRAN_IDENTIFIER(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3886 | 1 |
| Bin | 1 | 0 | 5504 | 1 |
Port:
TRAN_IDENTIFIER(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4233 | 1 |
| Bin | 1 | 0 | 5783 | 1 |
Port:
TRAN_IDENTIFIER(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3889 | 1 |
| Bin | 1 | 0 | 5506 | 1 |
Port:
TRAN_IDENTIFIER(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4204 | 1 |
| Bin | 1 | 0 | 5749 | 1 |
Port:
TRAN_IDENTIFIER(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3808 | 1 |
| Bin | 1 | 0 | 5429 | 1 |
Port:
TRAN_IDENTIFIER(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1667 | 1 |
| Bin | 1 | 0 | 9368 | 1 |
Port:
TRAN_IDENTIFIER(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713 | 1 |
| Bin | 1 | 0 | 9584 | 1 |
Port:
TRAN_IDENTIFIER(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1692 | 1 |
| Bin | 1 | 0 | 9464 | 1 |
Port:
TRAN_IDENTIFIER(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1708 | 1 |
| Bin | 1 | 0 | 9676 | 1 |
Port:
TRAN_IDENTIFIER(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1710 | 1 |
| Bin | 1 | 0 | 9487 | 1 |
Port:
TRAN_IDENTIFIER(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1603 | 1 |
| Bin | 1 | 0 | 9370 | 1 |
Port:
TRAN_IDENTIFIER(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 9410 | 1 |
Port:
TRAN_IDENTIFIER(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1672 | 1 |
| Bin | 1 | 0 | 9469 | 1 |
Port:
TRAN_IDENTIFIER(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1704 | 1 |
| Bin | 1 | 0 | 9526 | 1 |
Port:
TRAN_IDENTIFIER(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1702 | 1 |
| Bin | 1 | 0 | 9536 | 1 |
Port:
TRAN_IDENTIFIER(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1736 | 1 |
| Bin | 1 | 0 | 9656 | 1 |
Port:
TRAN_IDENTIFIER(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1654 | 1 |
| Bin | 1 | 0 | 9406 | 1 |
Port:
TRAN_IDENTIFIER(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1706 | 1 |
| Bin | 1 | 0 | 9513 | 1 |
Port:
TRAN_IDENTIFIER(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1714 | 1 |
| Bin | 1 | 0 | 9618 | 1 |
Port:
TRAN_IDENTIFIER(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1700 | 1 |
| Bin | 1 | 0 | 9481 | 1 |
Port:
TRAN_IDENTIFIER(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 9571 | 1 |
Port:
TRAN_IDENTIFIER(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1744 | 1 |
| Bin | 1 | 0 | 9585 | 1 |
Port:
TRAN_IDENTIFIER(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 9381 | 1 |
Port:
TRAN_FRAME_TEST.FSTC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
Port:
TRAN_FRAME_TEST.FCRC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Port:
TRAN_FRAME_TEST.SDLC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 3284 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 183 | 1 |
| Bin | 1 | 0 | 1828 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 235 | 1 |
| Bin | 1 | 0 | 1880 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 429 | 1 |
| Bin | 1 | 0 | 2074 | 1 |
Port:
TRAN_FRAME_TEST.TPRM(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 646 | 1 |
| Bin | 1 | 0 | 2291 | 1 |
Port:
TRAN_FRAME_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25071 | 1 |
| Bin | 1 | 0 | 26671 | 1 |
Port:
TRAN_FRAME_PARITY_ERROR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 762 | 1 |
| Bin | 1 | 0 | 2362 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24816 | 1 |
| Bin | 1 | 0 | 26416 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4237 | 1 |
| Bin | 1 | 0 | 5837 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 455 | 1 |
| Bin | 1 | 0 | 2055 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9015 | 1 |
| Bin | 1 | 0 | 10615 | 1 |
Port:
TXTB_CHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10007 | 1 |
| Bin | 1 | 0 | 11607 | 1 |
Port:
TXTB_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78974 | 1 |
| Bin | 1 | 0 | 80574 | 1 |
Port:
REC_IDENT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34332 | 1 |
| Bin | 1 | 0 | 30165 | 1 |
Port:
REC_IDENT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20951 | 1 |
| Bin | 1 | 0 | 16748 | 1 |
Port:
REC_IDENT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34995 | 1 |
| Bin | 1 | 0 | 29978 | 1 |
Port:
REC_IDENT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26409 | 1 |
| Bin | 1 | 0 | 21440 | 1 |
Port:
REC_IDENT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37621 | 1 |
| Bin | 1 | 0 | 32560 | 1 |
Port:
REC_IDENT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27574 | 1 |
| Bin | 1 | 0 | 22162 | 1 |
Port:
REC_IDENT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37576 | 1 |
| Bin | 1 | 0 | 32729 | 1 |
Port:
REC_IDENT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26623 | 1 |
| Bin | 1 | 0 | 21662 | 1 |
Port:
REC_IDENT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34131 | 1 |
| Bin | 1 | 0 | 30013 | 1 |
Port:
REC_IDENT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25018 | 1 |
| Bin | 1 | 0 | 20939 | 1 |
Port:
REC_IDENT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35861 | 1 |
| Bin | 1 | 0 | 31802 | 1 |
Port:
REC_IDENT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6676 | 1 |
| Bin | 1 | 0 | 77411 | 1 |
Port:
REC_IDENT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 76980 | 1 |
Port:
REC_IDENT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6016 | 1 |
| Bin | 1 | 0 | 75936 | 1 |
Port:
REC_IDENT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6457 | 1 |
| Bin | 1 | 0 | 77301 | 1 |
Port:
REC_IDENT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6203 | 1 |
| Bin | 1 | 0 | 75854 | 1 |
Port:
REC_IDENT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6655 | 1 |
| Bin | 1 | 0 | 77348 | 1 |
Port:
REC_IDENT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6116 | 1 |
| Bin | 1 | 0 | 76014 | 1 |
Port:
REC_IDENT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6759 | 1 |
| Bin | 1 | 0 | 77172 | 1 |
Port:
REC_IDENT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6340 | 1 |
| Bin | 1 | 0 | 76882 | 1 |
Port:
REC_IDENT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7191 | 1 |
| Bin | 1 | 0 | 78168 | 1 |
Port:
REC_IDENT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6170 | 1 |
| Bin | 1 | 0 | 76119 | 1 |
Port:
REC_IDENT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 77753 | 1 |
Port:
REC_IDENT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6122 | 1 |
| Bin | 1 | 0 | 76213 | 1 |
Port:
REC_IDENT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6712 | 1 |
| Bin | 1 | 0 | 78180 | 1 |
Port:
REC_IDENT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6213 | 1 |
| Bin | 1 | 0 | 76204 | 1 |
Port:
REC_IDENT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7044 | 1 |
| Bin | 1 | 0 | 78347 | 1 |
Port:
REC_IDENT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6316 | 1 |
| Bin | 1 | 0 | 75925 | 1 |
Port:
REC_IDENT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6757 | 1 |
| Bin | 1 | 0 | 77490 | 1 |
Port:
REC_DLC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20320 | 1 |
| Bin | 1 | 0 | 58988 | 1 |
Port:
REC_DLC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22531 | 1 |
| Bin | 1 | 0 | 28242 | 1 |
Port:
REC_DLC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22383 | 1 |
| Bin | 1 | 0 | 27966 | 1 |
Port:
REC_DLC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26951 | 1 |
| Bin | 1 | 0 | 33011 | 1 |
Port:
REC_IDENT_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15760 | 1 |
| Bin | 1 | 0 | 17358 | 1 |
Port:
REC_FRAME_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28440 | 1 |
| Bin | 1 | 0 | 30036 | 1 |
Port:
REC_LBPF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 180 | 1 |
| Bin | 1 | 0 | 1780 | 1 |
Port:
REC_IS_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22038 | 1 |
| Bin | 1 | 0 | 23636 | 1 |
Port:
REC_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20406 | 1 |
| Bin | 1 | 0 | 22002 | 1 |
Port:
REC_ESI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2145 | 1 |
| Bin | 1 | 0 | 3743 | 1 |
Port:
REC_IVLD | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50520 | 1 |
| Bin | 1 | 0 | 52113 | 1 |
Port:
REC_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15179 | 1 |
| Bin | 1 | 0 | 16779 | 1 |
Port:
STORE_METADATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28520 | 1 |
| Bin | 1 | 0 | 30120 | 1 |
Port:
STORE_DATA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88897 | 1 |
| Bin | 1 | 0 | 90497 | 1 |
Port:
STORE_DATA_WORD(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 237198 | 1 |
| Bin | 1 | 0 | 238797 | 1 |
Port:
STORE_DATA_WORD(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 243752 | 1 |
| Bin | 1 | 0 | 245348 | 1 |
Port:
STORE_DATA_WORD(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 254056 | 1 |
| Bin | 1 | 0 | 255652 | 1 |
Port:
STORE_DATA_WORD(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 261408 | 1 |
| Bin | 1 | 0 | 263004 | 1 |
Port:
STORE_DATA_WORD(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270752 | 1 |
| Bin | 1 | 0 | 272349 | 1 |
Port:
STORE_DATA_WORD(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 281246 | 1 |
| Bin | 1 | 0 | 282842 | 1 |
Port:
STORE_DATA_WORD(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 289484 | 1 |
| Bin | 1 | 0 | 291079 | 1 |
Port:
STORE_DATA_WORD(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 297255 | 1 |
| Bin | 1 | 0 | 298852 | 1 |
Port:
STORE_DATA_WORD(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 286221 | 1 |
| Bin | 1 | 0 | 287818 | 1 |
Port:
STORE_DATA_WORD(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 294374 | 1 |
| Bin | 1 | 0 | 295971 | 1 |
Port:
STORE_DATA_WORD(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 302753 | 1 |
| Bin | 1 | 0 | 304349 | 1 |
Port:
STORE_DATA_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 311493 | 1 |
| Bin | 1 | 0 | 313091 | 1 |
Port:
STORE_DATA_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 323361 | 1 |
| Bin | 1 | 0 | 324957 | 1 |
Port:
STORE_DATA_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 330483 | 1 |
| Bin | 1 | 0 | 332080 | 1 |
Port:
STORE_DATA_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 338889 | 1 |
| Bin | 1 | 0 | 340488 | 1 |
Port:
STORE_DATA_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 345150 | 1 |
| Bin | 1 | 0 | 346748 | 1 |
Port:
STORE_DATA_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 386346 | 1 |
| Bin | 1 | 0 | 387945 | 1 |
Port:
STORE_DATA_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 400757 | 1 |
| Bin | 1 | 0 | 402354 | 1 |
Port:
STORE_DATA_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 409685 | 1 |
| Bin | 1 | 0 | 411281 | 1 |
Port:
STORE_DATA_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 419496 | 1 |
| Bin | 1 | 0 | 421093 | 1 |
Port:
STORE_DATA_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 432274 | 1 |
| Bin | 1 | 0 | 433870 | 1 |
Port:
STORE_DATA_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 442097 | 1 |
| Bin | 1 | 0 | 443695 | 1 |
Port:
STORE_DATA_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 454252 | 1 |
| Bin | 1 | 0 | 455847 | 1 |
Port:
STORE_DATA_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465041 | 1 |
| Bin | 1 | 0 | 466639 | 1 |
Port:
STORE_DATA_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 510943 | 1 |
| Bin | 1 | 0 | 512538 | 1 |
Port:
STORE_DATA_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522813 | 1 |
| Bin | 1 | 0 | 524410 | 1 |
Port:
STORE_DATA_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 532557 | 1 |
| Bin | 1 | 0 | 534152 | 1 |
Port:
STORE_DATA_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 542224 | 1 |
| Bin | 1 | 0 | 543819 | 1 |
Port:
STORE_DATA_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555100 | 1 |
| Bin | 1 | 0 | 556695 | 1 |
Port:
STORE_DATA_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564607 | 1 |
| Bin | 1 | 0 | 566201 | 1 |
Port:
STORE_DATA_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576164 | 1 |
| Bin | 1 | 0 | 577759 | 1 |
Port:
STORE_DATA_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586427 | 1 |
| Bin | 1 | 0 | 588021 | 1 |
Port:
REC_ABORT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30824 | 1 |
| Bin | 1 | 0 | 32424 | 1 |
Port:
SOF_PULSE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79747 | 1 |
| Bin | 1 | 0 | 81347 | 1 |
Port:
ARBITRATION_LOST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1172 | 1 |
| Bin | 1 | 0 | 2772 | 1 |
Port:
TRAN_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
BR_SHIFTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47787 | 1 |
| Bin | 1 | 0 | 49387 | 1 |
Port:
ERR_DETECTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123242 | 1 |
| Bin | 1 | 0 | 124842 | 1 |
Port:
FCS_CHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15989 | 1 |
| Bin | 1 | 0 | 17589 | 1 |
Port:
ERR_WARNING_LIMIT_PULSE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3183 | 1 |
| Bin | 1 | 0 | 4783 | 1 |
Port:
RX_TRIGGERS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33119362 | 1 |
| Bin | 1 | 0 | 33122562 | 1 |
Port:
RX_TRIGGERS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22070470 | 1 |
| Bin | 1 | 0 | 44169854 | 1 |
Port:
TX_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11044003 | 1 |
| Bin | 1 | 0 | 11045602 | 1 |
Port:
SYNC_CONTROL(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 99647 | 1 |
| Bin | 1 | 0 | 99642 | 1 |
Port:
SYNC_CONTROL(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91759 | 1 |
| Bin | 1 | 0 | 91764 | 1 |
Port:
NO_POS_RESYNC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 633738 | 1 |
| Bin | 1 | 0 | 635336 | 1 |
Port:
SP_CONTROL(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4206 | 1 |
| Bin | 1 | 0 | 5806 | 1 |
Port:
SP_CONTROL(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25548 | 1 |
| Bin | 1 | 0 | 27148 | 1 |
Port:
NBT_CTRS_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
DBT_CTRS_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66645 | 1 |
| Bin | 1 | 0 | 68245 | 1 |
Port:
RX_DATA_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1400896 | 1 |
| Bin | 1 | 0 | 1399296 | 1 |
Port:
TX_DATA_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635336 | 1 |
| Bin | 1 | 0 | 633738 | 1 |
Port:
SSP_RESET | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34780 | 1 |
| Bin | 1 | 0 | 36380 | 1 |
Port:
TRAN_DELAY_MEAS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35025 | 1 |
| Bin | 1 | 0 | 36625 | 1 |
Port:
BIT_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9381 | 1 |
| Bin | 1 | 0 | 10981 | 1 |
Port:
BTMC_RESET | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28129 | 1 |
| Bin | 1 | 0 | 29729 | 1 |
Port:
DBT_MEASURE_START | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2323 | 1 |
| Bin | 1 | 0 | 3923 | 1 |
Port:
GEN_FIRST_SSP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2323 | 1 |
| Bin | 1 | 0 | 3923 | 1 |
Port:
SYNC_EDGE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1555148 | 1 |
| Bin | 1 | 0 | 1556748 | 1 |
Port:
BIT_ERR_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66912 | 1 |
| Bin | 1 | 0 | 65320 | 1 |
Port:
PC_RX_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10015414 | 1 |
| Bin | 1 | 0 | 10017014 | 1 |
Signal:
ALC_ALC_BIT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
Signal:
ALC_ALC_BIT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1686 | 1 |
Signal:
ALC_ALC_BIT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
Signal:
ALC_ALC_BIT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 171 | 1 |
| Bin | 1 | 0 | 1769 | 1 |
Signal:
ALC_ALC_BIT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 1894 | 1 |
Signal:
ALC_ALC_ID_FIELD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
Signal:
ALC_ALC_ID_FIELD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1638 | 1 |
Signal:
ALC_ALC_ID_FIELD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Signal:
ERR_CAPT_ERR_TYPE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 793 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
Signal:
ERR_CAPT_ERR_TYPE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1252 | 1 |
| Bin | 1 | 0 | 2850 | 1 |
Signal:
ERR_CAPT_ERR_TYPE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 336 | 1 |
| Bin | 1 | 0 | 1935 | 1 |
Signal:
ERR_CAPT_ERR_POS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4185 | 1 |
| Bin | 1 | 0 | 2591 | 1 |
Signal:
ERR_CAPT_ERR_POS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4402 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
Signal:
ERR_CAPT_ERR_POS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3666 | 1 |
| Bin | 1 | 0 | 2070 | 1 |
Signal:
ERR_CAPT_ERR_POS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2960 | 1 |
| Bin | 1 | 0 | 1361 | 1 |
Signal:
ERR_CAPT_ERR_ERP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 290 | 1 |
| Bin | 1 | 0 | 1890 | 1 |
Signal:
IS_TRANSMITTER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19892 | 1 |
| Bin | 1 | 0 | 21492 | 1 |
Signal:
IS_RECEIVER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30888 | 1 |
| Bin | 1 | 0 | 32482 | 1 |
Signal:
IS_IDLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55452 | 1 |
| Bin | 1 | 0 | 57049 | 1 |
Signal:
ARBITRATION_LOST_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1172 | 1 |
| Bin | 1 | 0 | 2772 | 1 |
Signal:
SET_TRANSMITTER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 39810 | 1 |
| Bin | 1 | 0 | 41410 | 1 |
Signal:
SET_RECEIVER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30469 | 1 |
| Bin | 1 | 0 | 32069 | 1 |
Signal:
SET_IDLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95674 | 1 |
| Bin | 1 | 0 | 97274 | 1 |
Signal:
IS_ERR_ACTIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8424 | 1 |
| Bin | 1 | 0 | 8415 | 1 |
Signal:
IS_ERR_PASSIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
Signal:
IS_BUS_OFF_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8227 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Signal:
ERR_DETECTED_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123242 | 1 |
| Bin | 1 | 0 | 124842 | 1 |
Signal:
PRIMARY_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22658 | 1 |
| Bin | 1 | 0 | 24258 | 1 |
Signal:
ACT_ERR_OVR_FLAG | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19607 | 1 |
| Bin | 1 | 0 | 21205 | 1 |
Signal:
ERR_DELIM_LATE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 390 | 1 |
| Bin | 1 | 0 | 1990 | 1 |
Signal:
SET_ERR_ACTIVE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Signal:
ERR_CTRS_UNCHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 791 | 1 |
| Bin | 1 | 0 | 2391 | 1 |
Signal:
STUFF_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24816 | 1 |
| Bin | 1 | 0 | 26416 | 1 |
Signal:
DESTUFF_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55285 | 1 |
| Bin | 1 | 0 | 56885 | 1 |
Signal:
FIXED_STUFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13466 | 1 |
| Bin | 1 | 0 | 15066 | 1 |
Signal:
TX_FRAME_NO_SOF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
Signal:
DST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116920 | 1 |
| Bin | 1 | 0 | 118520 | 1 |
Signal:
DST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 241878 | 1 |
| Bin | 1 | 0 | 243473 | 1 |
Signal:
DST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 483649 | 1 |
| Bin | 1 | 0 | 485246 | 1 |
Signal:
BST_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33334 | 1 |
| Bin | 1 | 0 | 34934 | 1 |
Signal:
BST_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70225 | 1 |
| Bin | 1 | 0 | 71823 | 1 |
Signal:
BST_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 140700 | 1 |
| Bin | 1 | 0 | 142298 | 1 |
Signal:
STUFF_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20489 | 1 |
| Bin | 1 | 0 | 22089 | 1 |
Signal:
CRC_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55285 | 1 |
| Bin | 1 | 0 | 56885 | 1 |
Signal:
CRC_SPEC_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 112536 | 1 |
| Bin | 1 | 0 | 114132 | 1 |
Signal:
CRC_CALC_FROM_RX | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83068 | 1 |
| Bin | 1 | 0 | 84659 | 1 |
Signal:
CRC_15(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1452642 | 1 |
| Bin | 1 | 0 | 1454241 | 1 |
Signal:
CRC_15(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1404381 | 1 |
| Bin | 1 | 0 | 1405979 | 1 |
Signal:
CRC_15(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1416815 | 1 |
| Bin | 1 | 0 | 1418414 | 1 |
Signal:
CRC_15(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1431040 | 1 |
| Bin | 1 | 0 | 1432636 | 1 |
Signal:
CRC_15(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1444591 | 1 |
| Bin | 1 | 0 | 1446189 | 1 |
Signal:
CRC_15(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1438246 | 1 |
| Bin | 1 | 0 | 1439842 | 1 |
Signal:
CRC_15(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1452223 | 1 |
| Bin | 1 | 0 | 1453819 | 1 |
Signal:
CRC_15(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1489085 | 1 |
| Bin | 1 | 0 | 1490683 | 1 |
Signal:
CRC_15(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1428572 | 1 |
| Bin | 1 | 0 | 1430168 | 1 |
Signal:
CRC_15(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1442138 | 1 |
| Bin | 1 | 0 | 1443734 | 1 |
Signal:
CRC_15(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1454104 | 1 |
| Bin | 1 | 0 | 1455703 | 1 |
Signal:
CRC_15(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1453743 | 1 |
| Bin | 1 | 0 | 1455342 | 1 |
Signal:
CRC_15(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1440570 | 1 |
| Bin | 1 | 0 | 1442165 | 1 |
Signal:
CRC_15(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1456437 | 1 |
| Bin | 1 | 0 | 1458034 | 1 |
Signal:
CRC_15(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1470076 | 1 |
| Bin | 1 | 0 | 1471674 | 1 |
Signal:
CRC_17(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734039 | 1 |
| Bin | 1 | 0 | 1735633 | 1 |
Signal:
CRC_17(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1744508 | 1 |
| Bin | 1 | 0 | 1746106 | 1 |
Signal:
CRC_17(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1759054 | 1 |
| Bin | 1 | 0 | 1760651 | 1 |
Signal:
CRC_17(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1757156 | 1 |
| Bin | 1 | 0 | 1758753 | 1 |
Signal:
CRC_17(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1695908 | 1 |
| Bin | 1 | 0 | 1697506 | 1 |
Signal:
CRC_17(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1710517 | 1 |
| Bin | 1 | 0 | 1712115 | 1 |
Signal:
CRC_17(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1657718 | 1 |
| Bin | 1 | 0 | 1659317 | 1 |
Signal:
CRC_17(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1671362 | 1 |
| Bin | 1 | 0 | 1672959 | 1 |
Signal:
CRC_17(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1685982 | 1 |
| Bin | 1 | 0 | 1687581 | 1 |
Signal:
CRC_17(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1699437 | 1 |
| Bin | 1 | 0 | 1701036 | 1 |
Signal:
CRC_17(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713617 | 1 |
| Bin | 1 | 0 | 1715217 | 1 |
Signal:
CRC_17(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713382 | 1 |
| Bin | 1 | 0 | 1714978 | 1 |
Signal:
CRC_17(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1725540 | 1 |
| Bin | 1 | 0 | 1727138 | 1 |
Signal:
CRC_17(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1744070 | 1 |
| Bin | 1 | 0 | 1745668 | 1 |
Signal:
CRC_17(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713985 | 1 |
| Bin | 1 | 0 | 1715584 | 1 |
Signal:
CRC_17(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1729286 | 1 |
| Bin | 1 | 0 | 1730885 | 1 |
Signal:
CRC_17(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1757719 | 1 |
| Bin | 1 | 0 | 1759317 | 1 |
Signal:
CRC_21(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1738348 | 1 |
| Bin | 1 | 0 | 1739941 | 1 |
Signal:
CRC_21(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1694492 | 1 |
| Bin | 1 | 0 | 1696089 | 1 |
Signal:
CRC_21(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1709182 | 1 |
| Bin | 1 | 0 | 1710780 | 1 |
Signal:
CRC_21(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1723668 | 1 |
| Bin | 1 | 0 | 1725266 | 1 |
Signal:
CRC_21(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1736428 | 1 |
| Bin | 1 | 0 | 1738027 | 1 |
Signal:
CRC_21(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1749537 | 1 |
| Bin | 1 | 0 | 1751135 | 1 |
Signal:
CRC_21(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1762507 | 1 |
| Bin | 1 | 0 | 1764105 | 1 |
Signal:
CRC_21(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1777446 | 1 |
| Bin | 1 | 0 | 1779044 | 1 |
Signal:
CRC_21(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1718146 | 1 |
| Bin | 1 | 0 | 1719743 | 1 |
Signal:
CRC_21(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1733293 | 1 |
| Bin | 1 | 0 | 1734892 | 1 |
Signal:
CRC_21(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1723964 | 1 |
| Bin | 1 | 0 | 1725560 | 1 |
Signal:
CRC_21(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1737663 | 1 |
| Bin | 1 | 0 | 1739261 | 1 |
Signal:
CRC_21(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1753350 | 1 |
| Bin | 1 | 0 | 1754945 | 1 |
Signal:
CRC_21(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1768568 | 1 |
| Bin | 1 | 0 | 1770168 | 1 |
Signal:
CRC_21(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1710305 | 1 |
| Bin | 1 | 0 | 1711902 | 1 |
Signal:
CRC_21(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1724000 | 1 |
| Bin | 1 | 0 | 1725597 | 1 |
Signal:
CRC_21(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1737131 | 1 |
| Bin | 1 | 0 | 1738729 | 1 |
Signal:
CRC_21(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1753239 | 1 |
| Bin | 1 | 0 | 1754837 | 1 |
Signal:
CRC_21(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1752204 | 1 |
| Bin | 1 | 0 | 1753800 | 1 |
Signal:
CRC_21(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1764851 | 1 |
| Bin | 1 | 0 | 1766449 | 1 |
Signal:
CRC_21(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1777838 | 1 |
| Bin | 1 | 0 | 1779434 | 1 |
Signal:
SP_CONTROL_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4206 | 1 |
| Bin | 1 | 0 | 5806 | 1 |
Signal:
SP_CONTROL_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25548 | 1 |
| Bin | 1 | 0 | 27148 | 1 |
Signal:
SP_CONTROL_Q(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2348 | 1 |
| Bin | 1 | 0 | 3948 | 1 |
Signal:
SP_CONTROL_Q(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18058 | 1 |
| Bin | 1 | 0 | 19658 | 1 |
Signal:
TRAN_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Signal:
REC_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15179 | 1 |
| Bin | 1 | 0 | 16779 | 1 |
Signal:
TX_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 249 | 1 |
| Bin | 1 | 0 | 1849 | 1 |
Signal:
TX_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 521 | 1 |
| Bin | 1 | 0 | 2121 | 1 |
Signal:
TX_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 488 | 1 |
| Bin | 1 | 0 | 2088 | 1 |
Signal:
TX_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 811 | 1 |
| Bin | 1 | 0 | 2411 | 1 |
Signal:
TX_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1931 | 1 |
| Bin | 1 | 0 | 3531 | 1 |
Signal:
TX_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12094 | 1 |
| Bin | 1 | 0 | 13694 | 1 |
Signal:
TX_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2980 | 1 |
| Bin | 1 | 0 | 4580 | 1 |
Signal:
TX_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3318 | 1 |
| Bin | 1 | 0 | 4918 | 1 |
Signal:
TX_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3517 | 1 |
| Bin | 1 | 0 | 5117 | 1 |
Signal:
RX_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 1736 | 1 |
Signal:
RX_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 360 | 1 |
| Bin | 1 | 0 | 1960 | 1 |
Signal:
RX_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 1864 | 1 |
Signal:
RX_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 332 | 1 |
| Bin | 1 | 0 | 1931 | 1 |
Signal:
RX_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 519 | 1 |
| Bin | 1 | 0 | 2119 | 1 |
Signal:
RX_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 686 | 1 |
| Bin | 1 | 0 | 2285 | 1 |
Signal:
RX_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 627 | 1 |
| Bin | 1 | 0 | 2227 | 1 |
Signal:
RX_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1208 | 1 |
| Bin | 1 | 0 | 2808 | 1 |
Signal:
RX_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11221 | 1 |
| Bin | 1 | 0 | 12815 | 1 |
Signal:
NORM_ERR_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
Signal:
NORM_ERR_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 69 | 1 |
| Bin | 1 | 0 | 1668 | 1 |
Signal:
NORM_ERR_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
Signal:
NORM_ERR_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Signal:
NORM_ERR_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Signal:
NORM_ERR_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Signal:
NORM_ERR_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
Signal:
NORM_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Signal:
NORM_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Signal:
NORM_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
Signal:
NORM_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1759 | 1 |
Signal:
NORM_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 1878 | 1 |
Signal:
NORM_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 600 | 1 |
| Bin | 1 | 0 | 2194 | 1 |
Signal:
NORM_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1361 | 1 |
| Bin | 1 | 0 | 2956 | 1 |
Signal:
NORM_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3048 | 1 |
| Bin | 1 | 0 | 4645 | 1 |
Signal:
NORM_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11189 | 1 |
| Bin | 1 | 0 | 12783 | 1 |
Signal:
DATA_ERR_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Signal:
DATA_ERR_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
Signal:
DATA_ERR_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Signal:
DATA_ERR_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
Signal:
DATA_ERR_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Signal:
DATA_ERR_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
Signal:
DATA_ERR_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
Signal:
DATA_ERR_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 85 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
Signal:
DATA_ERR_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1701 | 1 |
Signal:
DATA_ERR_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 138 | 1 |
| Bin | 1 | 0 | 1735 | 1 |
Signal:
DATA_ERR_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Signal:
DATA_ERR_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 359 | 1 |
| Bin | 1 | 0 | 1956 | 1 |
Signal:
DATA_ERR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 679 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
Signal:
DATA_ERR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1295 | 1 |
| Bin | 1 | 0 | 2892 | 1 |
Signal:
DATA_ERR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2524 | 1 |
| Bin | 1 | 0 | 4120 | 1 |
Signal:
DATA_ERR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5478 | 1 |
| Bin | 1 | 0 | 7073 | 1 |
Signal:
PC_TX_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11044003 | 1 |
| Bin | 1 | 0 | 11045602 | 1 |
Signal:
PC_RX_TRIGGER_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10015414 | 1 |
| Bin | 1 | 0 | 10017014 | 1 |
Signal:
PC_TX_DATA_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 644444 | 1 |
| Bin | 1 | 0 | 642846 | 1 |
Signal:
PC_RX_DATA_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Signal:
CRC_DATA_TX_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635351 | 1 |
| Bin | 1 | 0 | 633753 | 1 |
Signal:
CRC_DATA_TX_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 644444 | 1 |
| Bin | 1 | 0 | 642846 | 1 |
Signal:
CRC_DATA_RX_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1396008 | 1 |
| Bin | 1 | 0 | 1397599 | 1 |
Signal:
CRC_DATA_RX_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Signal:
CRC_TRIG_TX_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11079571 | 1 |
| Bin | 1 | 0 | 11081170 | 1 |
Signal:
CRC_TRIG_TX_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11044003 | 1 |
| Bin | 1 | 0 | 11045602 | 1 |
Signal:
CRC_TRIG_RX_WBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10955682 | 1 |
| Bin | 1 | 0 | 10957282 | 1 |
Signal:
CRC_TRIG_RX_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10015414 | 1 |
| Bin | 1 | 0 | 10017014 | 1 |
Signal:
BST_DATA_IN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 644444 | 1 |
| Bin | 1 | 0 | 642846 | 1 |
Signal:
BST_DATA_OUT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635351 | 1 |
| Bin | 1 | 0 | 633753 | 1 |
Signal:
BST_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11044003 | 1 |
| Bin | 1 | 0 | 11045602 | 1 |
Signal:
DATA_HALT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 944735 | 1 |
| Bin | 1 | 0 | 946335 | 1 |
Signal:
BDS_DATA_IN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1401177 | 1 |
| Bin | 1 | 0 | 1399577 | 1 |
Signal:
BDS_DATA_OUT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Signal:
BDS_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22084127 | 1 |
| Bin | 1 | 0 | 22085727 | 1 |
Signal:
DESTUFFED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1019821 | 1 |
| Bin | 1 | 0 | 1021421 | 1 |
Signal:
TX_FRAME_CTR(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Signal:
TX_FRAME_CTR(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108 | 1 |
| Bin | 1 | 0 | 1708 | 1 |
Signal:
TX_FRAME_CTR(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Signal:
TX_FRAME_CTR(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
Signal:
TX_FRAME_CTR(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 1691 | 1 |
Signal:
TX_FRAME_CTR(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
Signal:
TX_FRAME_CTR(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Signal:
TX_FRAME_CTR(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Signal:
TX_FRAME_CTR(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
Signal:
TX_FRAME_CTR(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Signal:
TX_FRAME_CTR(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Signal:
TX_FRAME_CTR(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
Signal:
TX_FRAME_CTR(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
Signal:
TX_FRAME_CTR(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Signal:
TX_FRAME_CTR(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
Signal:
TX_FRAME_CTR(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
Signal:
TX_FRAME_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
Signal:
TX_FRAME_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Signal:
TX_FRAME_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Signal:
TX_FRAME_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
Signal:
TX_FRAME_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
Signal:
TX_FRAME_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
Signal:
TX_FRAME_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Signal:
TX_FRAME_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
Signal:
TX_FRAME_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
Signal:
TX_FRAME_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Signal:
TX_FRAME_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 1729 | 1 |
Signal:
TX_FRAME_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 1752 | 1 |
Signal:
TX_FRAME_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 1863 | 1 |
Signal:
TX_FRAME_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 593 | 1 |
| Bin | 1 | 0 | 2193 | 1 |
Signal:
TX_FRAME_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1072 | 1 |
| Bin | 1 | 0 | 2672 | 1 |
Signal:
TX_FRAME_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2211 | 1 |
| Bin | 1 | 0 | 3811 | 1 |
Signal:
RX_FRAME_CTR(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
RX_FRAME_CTR(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Signal:
RX_FRAME_CTR(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Signal:
RX_FRAME_CTR(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
Signal:
RX_FRAME_CTR(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
Signal:
RX_FRAME_CTR(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Signal:
RX_FRAME_CTR(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Signal:
RX_FRAME_CTR(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Signal:
RX_FRAME_CTR(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
Signal:
RX_FRAME_CTR(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
RX_FRAME_CTR(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Signal:
RX_FRAME_CTR(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
Signal:
RX_FRAME_CTR(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Signal:
RX_FRAME_CTR(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
Signal:
RX_FRAME_CTR(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Signal:
RX_FRAME_CTR(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1648 | 1 |
Signal:
RX_FRAME_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
Signal:
RX_FRAME_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
Signal:
RX_FRAME_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
Signal:
RX_FRAME_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
Signal:
RX_FRAME_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
Signal:
RX_FRAME_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
Signal:
RX_FRAME_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
RX_FRAME_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
Signal:
RX_FRAME_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
Signal:
RX_FRAME_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Signal:
RX_FRAME_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 222 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
Signal:
RX_FRAME_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 355 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
Signal:
RX_FRAME_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 746 | 1 |
| Bin | 1 | 0 | 2344 | 1 |
Signal:
RX_FRAME_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1495 | 1 |
| Bin | 1 | 0 | 3093 | 1 |
Signal:
RX_FRAME_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2959 | 1 |
| Bin | 1 | 0 | 4557 | 1 |
Signal:
RX_FRAME_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5919 | 1 |
| Bin | 1 | 0 | 7518 | 1 |
Signal:
TX_DATA_WBS_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635336 | 1 |
| Bin | 1 | 0 | 633738 | 1 |
Signal:
LPB_DOMINANT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1394904 | 1 |
| Bin | 1 | 0 | 1393306 | 1 |
Signal:
FORM_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 87083 | 1 |
| Bin | 1 | 0 | 88683 | 1 |
Signal:
ACK_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8001 | 1 |
| Bin | 1 | 0 | 9601 | 1 |
Signal:
CRC_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1612 | 1 |
| Bin | 1 | 0 | 3212 | 1 |
Signal:
LOAD_INIT_VECT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 112514 | 1 |
| Bin | 1 | 0 | 114114 | 1 |
Signal:
RETR_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
Signal:
RETR_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 132 | 1 |
| Bin | 1 | 0 | 1732 | 1 |
Signal:
RETR_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 255 | 1 |
| Bin | 1 | 0 | 1855 | 1 |
Signal:
RETR_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Signal:
DECREMENT_REC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14982 | 1 |
| Bin | 1 | 0 | 16582 | 1 |
Signal:
BIT_ERR_AFTER_ACK_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8 | 1 |
| Bin | 1 | 0 | 1608 | 1 |
Signal:
MR_STATUS_PEXS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
Signal:
MR_STATUS_EWL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 2391 | 1 |
Covered expressions:
"and" expression
899: lpb_dominant <= rx_data_wbs and bst_data_out;
<---LHS---> <---RHS----> | LHS | RHS | Count | Threshold |
|---|
| Bin | '0' | '1' | 1402338 | 1 |
| Bin | '1' | '0' | 628602 | 1 |
| Bin | '1' | '1' | 1394904 | 1 |
"=" expression
910: lpb_dominant when (mr_mode_bmm = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 6563575 | 1 |
| Bin | True | 1881 | 1 |
"=" expression
917: tx_data_wbs_i <= RECESSIVE when (mr_settings_ena = CTU_CAN_DISABLED) else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1277198 | 1 |
| Bin | True | 8080 | 1 |
"=" expression
918: RECESSIVE when (mr_mode_bmm = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1277148 | 1 |
| Bin | True | 50 | 1 |
"=" expression
925: no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 636936 | 1 |
| Bin | True | 633738 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: