NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.FEATURE_TEST_AGENT_GEN.FEATURE_TEST_AGENT_INST.TEST_NODE_INST.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.SETTINGS_RTRLE_REG_COMP

File:  /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average
BIT_GEN(0) N.A. N.A. N.A. N.A. N.A. N.A. N.A.

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.FEATURE_TEST_AGENT_GEN.FEATURE_TEST_AGENT_INST.TEST_NODE_INST.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.SETTINGS_RTRLE_REG_COMP N.A. N.A. N.A. N.A. N.A. N.A. N.A.

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

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