NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_DBT_INST	100.0 % (20/20)	100.0 % (20/20)	100.0 % (108/108)	100.0 % (29/29)	N.A.	N.A.	100.0 % (177/177)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

155:    tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp)) 
156:                              else 
157:                          '0';

Count: 80005255
Threshold: 1

Signal assignment statement:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
Count: 35091299
Threshold: 1

Signal assignment statement:

157: '0';
Count: 44913956
Threshold: 1

If statement:

165:    tq_counter_d <= 
166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
167:                                   else 
168:        std_logic_vector(unsigned(tq_counter_q) + 1);

Count: 194418437
Threshold: 1

Signal assignment statement:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
Count: 113270898
Threshold: 1

Signal assignment statement:

168: std_logic_vector(unsigned(tq_counter_q) + 1);
Count: 81147539
Threshold: 1

If statement:

172:        if (res_n = '0') then 
173:            tq_counter_q <= std_logic_vector(C_TQ_RST); 
...
177:            end if; 
178:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

173: tq_counter_q <= std_logic_vector(C_TQ_RST);
Count: 2418499
Threshold: 1

If statement:

175:            if (ctrs_en = '1') then 
176:                tq_counter_q <= tq_counter_d; 
177:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

176: tq_counter_q <= tq_counter_d;
Count: 138063946
Threshold: 1

If statement:

189:    segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else 
190:                      std_logic_vector(unsigned(segm_counter_q) + 1);

Count: 137448518
Threshold: 1

Signal assignment statement:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
Count: 32157308
Threshold: 1

Signal assignment statement:

190: std_logic_vector(unsigned(segm_counter_q) + 1);
Count: 105291210
Threshold: 1

If statement:

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
193:                           else 
194:                       '0';

Count: 114556919
Threshold: 1

Signal assignment statement:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
Count: 67245418
Threshold: 1

Signal assignment statement:

194: '0';
Count: 47311501
Threshold: 1

If statement:

198:        if (res_n = '0') then 
199:            segm_counter_q <= (others => '0'); 
...
203:            end if; 
204:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

199: segm_counter_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

201:            if (segm_counter_ce = '1') then 
202:                segm_counter_q <= segm_counter_d; 
203:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

202: segm_counter_q <= segm_counter_d;
Count: 105279971
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))

	Evaluated to	Count	Threshold
Bin	True	35091299	1
Bin	False	44913956	1

"if" / "when" / "else" condition:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	True	113270898	1
Bin	False	81147539	1

"if" / "when" / "else" condition:

172: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

174: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	138063946	1
Bin	False	388310354	1

"if" / "when" / "else" condition:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	32157308	1
Bin	False	105291210	1

"if" / "when" / "else" condition:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	True	67245418	1
Bin	False	47311501	1

"if" / "when" / "else" condition:

198: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

200: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	105279971	1
Bin	False	421094329	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

BRP(7)

	From	To	Count	Threshold
Bin	0	1	19	1
Bin	1	0	1619	1

Port:

BRP(6)

	From	To	Count	Threshold
Bin	0	1	27	1
Bin	1	0	1627	1

Port:

BRP(5)

	From	To	Count	Threshold
Bin	0	1	18	1
Bin	1	0	1618	1

Port:

BRP(4)

	From	To	Count	Threshold
Bin	0	1	28	1
Bin	1	0	1628	1

Port:

BRP(3)

	From	To	Count	Threshold
Bin	0	1	25	1
Bin	1	0	1625	1

Port:

BRP(2)

	From	To	Count	Threshold
Bin	0	1	4843	1
Bin	1	0	3253	1

Port:

BRP(1)

	From	To	Count	Threshold
Bin	0	1	758	1
Bin	1	0	2356	1

Port:

BRP(0)

	From	To	Count	Threshold
Bin	0	1	2600	1
Bin	1	0	4192	1

Port:

TQ_RESET

	From	To	Count	Threshold
Bin	0	1	22118120	1
Bin	1	0	22119720	1

Port:

BT_RESET

	From	To	Count	Threshold
Bin	0	1	22118120	1
Bin	1	0	22119720	1

Port:

CTRS_EN

	From	To	Count	Threshold
Bin	0	1	66645	1
Bin	1	0	68245	1

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	35091299	1
Bin	1	0	35092890	1

Port:

SEGM_COUNTER(6)

	From	To	Count	Threshold
Bin	0	1	142554	1
Bin	1	0	144154	1

Port:

SEGM_COUNTER(5)

	From	To	Count	Threshold
Bin	0	1	246745	1
Bin	1	0	248345	1

Port:

SEGM_COUNTER(4)

	From	To	Count	Threshold
Bin	0	1	794895	1
Bin	1	0	796495	1

Port:

SEGM_COUNTER(3)

	From	To	Count	Threshold
Bin	0	1	4519840	1
Bin	1	0	4521440	1

Port:

SEGM_COUNTER(2)

	From	To	Count	Threshold
Bin	0	1	12002319	1
Bin	1	0	12003919	1

Port:

SEGM_COUNTER(1)

	From	To	Count	Threshold
Bin	0	1	22876595	1
Bin	1	0	22878195	1

Port:

SEGM_COUNTER(0)

	From	To	Count	Threshold
Bin	0	1	42573590	1
Bin	1	0	42575190	1

Signal:

TQ_COUNTER_D(7)

	From	To	Count	Threshold
Bin	0	1	21715	1
Bin	1	0	23315	1

Signal:

TQ_COUNTER_D(6)

	From	To	Count	Threshold
Bin	0	1	43430	1
Bin	1	0	45030	1

Signal:

TQ_COUNTER_D(5)

	From	To	Count	Threshold
Bin	0	1	86860	1
Bin	1	0	88460	1

Signal:

TQ_COUNTER_D(4)

	From	To	Count	Threshold
Bin	0	1	176024	1
Bin	1	0	177624	1

Signal:

TQ_COUNTER_D(3)

	From	To	Count	Threshold
Bin	0	1	368330	1
Bin	1	0	369930	1

Signal:

TQ_COUNTER_D(2)

	From	To	Count	Threshold
Bin	0	1	4753750	1
Bin	1	0	4755350	1

Signal:

TQ_COUNTER_D(1)

	From	To	Count	Threshold
Bin	0	1	37622679	1
Bin	1	0	37621088	1

Signal:

TQ_COUNTER_D(0)

	From	To	Count	Threshold
Bin	0	1	43069917	1
Bin	1	0	43071508	1

Signal:

TQ_COUNTER_Q(7)

	From	To	Count	Threshold
Bin	0	1	21715	1
Bin	1	0	23315	1

Signal:

TQ_COUNTER_Q(6)

	From	To	Count	Threshold
Bin	0	1	43430	1
Bin	1	0	45030	1

Signal:

TQ_COUNTER_Q(5)

	From	To	Count	Threshold
Bin	0	1	86860	1
Bin	1	0	88460	1

Signal:

TQ_COUNTER_Q(4)

	From	To	Count	Threshold
Bin	0	1	176024	1
Bin	1	0	177624	1

Signal:

TQ_COUNTER_Q(3)

	From	To	Count	Threshold
Bin	0	1	364280	1
Bin	1	0	365880	1

Signal:

TQ_COUNTER_Q(2)

	From	To	Count	Threshold
Bin	0	1	861195	1
Bin	1	0	862795	1

Signal:

TQ_COUNTER_Q(1)

	From	To	Count	Threshold
Bin	0	1	36494146	1
Bin	1	0	36495745	1

Signal:

TQ_COUNTER_Q(0)

	From	To	Count	Threshold
Bin	0	1	38049249	1
Bin	1	0	38047650	1

Signal:

TQ_COUNTER_EXPIRED

	From	To	Count	Threshold
Bin	0	1	35091299	1
Bin	1	0	35092890	1

Signal:

TQ_EDGE_I

	From	To	Count	Threshold
Bin	0	1	35091299	1
Bin	1	0	35092890	1

Signal:

SEGM_COUNTER_D(6)

	From	To	Count	Threshold
Bin	0	1	167949	1
Bin	1	0	169549	1

Signal:

SEGM_COUNTER_D(5)

	From	To	Count	Threshold
Bin	0	1	253065	1
Bin	1	0	254665	1

Signal:

SEGM_COUNTER_D(4)

	From	To	Count	Threshold
Bin	0	1	800585	1
Bin	1	0	802185	1

Signal:

SEGM_COUNTER_D(3)

	From	To	Count	Threshold
Bin	0	1	4536119	1
Bin	1	0	4537719	1

Signal:

SEGM_COUNTER_D(2)

	From	To	Count	Threshold
Bin	0	1	12035573	1
Bin	1	0	12037173	1

Signal:

SEGM_COUNTER_D(1)

	From	To	Count	Threshold
Bin	0	1	24770417	1
Bin	1	0	24772017	1

Signal:

SEGM_COUNTER_D(0)

	From	To	Count	Threshold
Bin	0	1	62714418	1
Bin	1	0	62712818	1

Signal:

SEGM_COUNTER_Q(6)

	From	To	Count	Threshold
Bin	0	1	142554	1
Bin	1	0	144154	1

Signal:

SEGM_COUNTER_Q(5)

	From	To	Count	Threshold
Bin	0	1	246745	1
Bin	1	0	248345	1

Signal:

SEGM_COUNTER_Q(4)

	From	To	Count	Threshold
Bin	0	1	794895	1
Bin	1	0	796495	1

Signal:

SEGM_COUNTER_Q(3)

	From	To	Count	Threshold
Bin	0	1	4519840	1
Bin	1	0	4521440	1

Signal:

SEGM_COUNTER_Q(2)

	From	To	Count	Threshold
Bin	0	1	12002319	1
Bin	1	0	12003919	1

Signal:

SEGM_COUNTER_Q(1)

	From	To	Count	Threshold
Bin	0	1	22876595	1
Bin	1	0	22878195	1

Signal:

SEGM_COUNTER_Q(0)

	From	To	Count	Threshold
Bin	0	1	42573590	1
Bin	1	0	42575190	1

Signal:

SEGM_COUNTER_CE

	From	To	Count	Threshold
Bin	0	1	47272415	1
Bin	1	0	47274015	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	False	85457029	1
Bin	True	108961408	1

"=" expression

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	False	165975043	1
Bin	True	28443394	1

"or" expression

166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
                                             <---------LHS---------->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	81147539	1
Bin	False	True	4309490	1
Bin	True	False	84827504	1

"=" expression

172: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	False	388310354	1
Bin	True	138063946	1

"=" expression

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	False	105291210	1
Bin	True	32157308	1

"=" expression

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	False	89276868	1
Bin	True	25280051	1

"=" expression

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	False	40565896	1
Bin	True	73991023	1

"=" expression

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	False	24336021	1
Bin	True	90220898	1

"and" expression

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
                                                         <-----LHS----->     <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	38269035	1
Bin	True	False	22039160	1
Bin	True	True	51951863	1

"or" expression

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
                                     <----LHS----->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	47311501	1
Bin	False	True	41965367	1
Bin	True	False	15293555	1

"=" expression

198: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	421094329	1
Bin	True	105279971	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_DBT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal: