NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_DBT_INST	100.0 % (23/23)	100.0 % (20/20)	100.0 % (108/108)	100.0 % (29/29)	N.A.	N.A.	100.0 % (180/180)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_DBT_INST

100.0 % (23/23)

100.0 % (20/20)

100.0 % (108/108)

100.0 % (29/29)

N.A.

100.0 % (180/180)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

155:    tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp)) 
156:                              else 
157:                          '0';

Count: 79039344
Threshold: 1

Signal assignment statement on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
Count: 34598889
Threshold: 1

Signal assignment statement on line 157:

157: '0';
Count: 44440455
Threshold: 1

If statement on lines 165 to 168:

165:    tq_counter_d <= 
166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
167:                                   else 
168:        std_logic_vector(unsigned(tq_counter_q) + 1);

Count: 193857450
Threshold: 1

Signal assignment statement on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
Count: 113593817
Threshold: 1

Signal assignment statement on line 168:

168: std_logic_vector(unsigned(tq_counter_q) + 1);
Count: 80263633
Threshold: 1

If statement on lines 172 to 178:

172:        if (res_n = '0') then 
173:            tq_counter_q <= std_logic_vector(C_TQ_RST); 
...
177:            end if; 
178:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 173:

173: tq_counter_q <= std_logic_vector(C_TQ_RST);
Count: 2424883
Threshold: 1

If statement on lines 175 to 177:

175:            if (ctrs_en = '1') then 
176:                tq_counter_q <= tq_counter_d; 
177:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 176:

176: tq_counter_q <= tq_counter_d;
Count: 137105515
Threshold: 1

Signal assignment statement on line 184:

184: tq_edge_i <= tq_counter_expired;
Count: 69200970
Threshold: 1

If statement on lines 189 to 190:

189:    segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else 
190:                      std_logic_vector(unsigned(segm_counter_q) + 1);

Count: 138353934
Threshold: 1

Signal assignment statement on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
Count: 32799616
Threshold: 1

Signal assignment statement on line 190:

190: std_logic_vector(unsigned(segm_counter_q) + 1);
Count: 105554318
Threshold: 1

If statement on lines 192 to 194:

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
193:                           else 
194:                       '0';

Count: 114963765
Threshold: 1

Signal assignment statement on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
Count: 67395407
Threshold: 1

Signal assignment statement on line 194:

194: '0';
Count: 47568358
Threshold: 1

If statement on lines 198 to 204:

198:        if (res_n = '0') then 
199:            segm_counter_q <= (others => '0'); 
...
203:            end if; 
204:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 199:

199: segm_counter_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 201 to 203:

201:            if (segm_counter_ce = '1') then 
202:                segm_counter_q <= segm_counter_d; 
203:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 202:

202: segm_counter_q <= segm_counter_d;
Count: 105543140
Threshold: 1

Signal assignment statement on line 210:

210: segm_counter <= segm_counter_q;
Count: 92726333
Threshold: 1

Signal assignment statement on line 211:

211: tq_edge <= tq_edge_i;
Count: 69200970
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))

	Evaluated to	Count	Threshold
Bin	True	34598889	1
Bin	False	44440455	1

"if" / "when" / "else" condition on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	True	113593817	1
Bin	False	80263633	1

"if" / "when" / "else" condition on line 172:

172: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 174:

174: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 175:

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	137105515	1
Bin	False	406686163	1

"if" / "when" / "else" condition on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	32799616	1
Bin	False	105554318	1

"if" / "when" / "else" condition on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	True	67395407	1
Bin	False	47568358	1

"if" / "when" / "else" condition on line 198:

198: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 200:

200: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 201:

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	105543140	1
Bin	False	438248538	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TQ_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BT_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	34598889	1
Bin	1	0	34600480	1

Port:

SEGM_COUNTER

	Element	From	To	Count	Threshold
Bin	(6)	0	1	141676	1
Bin	(6)	1	0	143277	1
Bin	(5)	0	1	246419	1
Bin	(5)	1	0	248020	1
Bin	(4)	0	1	788153	1
Bin	(4)	1	0	789754	1
Bin	(3)	0	1	4490644	1
Bin	(3)	1	0	4492245	1
Bin	(2)	0	1	11946010	1
Bin	(2)	1	0	11947611	1
Bin	(1)	0	1	22767194	1
Bin	(1)	1	0	22768795	1
Bin	(0)	0	1	42344657	1
Bin	(0)	1	0	42346257	1

Signal:

TQ_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	21715	1
Bin	(7)	1	0	23316	1
Bin	(6)	0	1	43430	1
Bin	(6)	1	0	45031	1
Bin	(5)	0	1	86860	1
Bin	(5)	1	0	88461	1
Bin	(4)	0	1	173735	1
Bin	(4)	1	0	175336	1
Bin	(3)	0	1	371454	1
Bin	(3)	1	0	373055	1
Bin	(2)	0	1	4659238	1
Bin	(2)	1	0	4660839	1
Bin	(1)	0	1	37211070	1
Bin	(1)	1	0	37209479	1
Bin	(0)	0	1	42563976	1
Bin	(0)	1	0	42565567	1

Signal:

TQ_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	21715	1
Bin	(7)	1	0	23316	1
Bin	(6)	0	1	43430	1
Bin	(6)	1	0	45031	1
Bin	(5)	0	1	86860	1
Bin	(5)	1	0	88461	1
Bin	(4)	0	1	173735	1
Bin	(4)	1	0	175336	1
Bin	(3)	0	1	371449	1
Bin	(3)	1	0	373050	1
Bin	(2)	0	1	954168	1
Bin	(2)	1	0	955769	1
Bin	(1)	0	1	36017664	1
Bin	(1)	1	0	36019264	1
Bin	(0)	0	1	37670621	1
Bin	(0)	1	0	37669021	1

Signal:

TQ_COUNTER_EXPIRED

	From	To	Count	Threshold
Bin	0	1	34598889	1
Bin	1	0	34600480	1

Signal:

TQ_EDGE_I

	From	To	Count	Threshold
Bin	0	1	34598889	1
Bin	1	0	34600480	1

Signal:

SEGM_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(6)	0	1	165678	1
Bin	(6)	1	0	167279	1
Bin	(5)	0	1	252971	1
Bin	(5)	1	0	254572	1
Bin	(4)	0	1	795223	1
Bin	(4)	1	0	796824	1
Bin	(3)	0	1	4508433	1
Bin	(3)	1	0	4510034	1
Bin	(2)	0	1	11980269	1
Bin	(2)	1	0	11981870	1
Bin	(1)	0	1	24632367	1
Bin	(1)	1	0	24633967	1
Bin	(0)	0	1	63206457	1
Bin	(0)	1	0	63204857	1

Signal:

SEGM_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(6)	0	1	141676	1
Bin	(6)	1	0	143277	1
Bin	(5)	0	1	246419	1
Bin	(5)	1	0	248020	1
Bin	(4)	0	1	788153	1
Bin	(4)	1	0	789754	1
Bin	(3)	0	1	4490644	1
Bin	(3)	1	0	4492245	1
Bin	(2)	0	1	11946010	1
Bin	(2)	1	0	11947611	1
Bin	(1)	0	1	22767194	1
Bin	(1)	1	0	22768795	1
Bin	(0)	0	1	42344657	1
Bin	(0)	1	0	42346257	1

Signal:

SEGM_COUNTER_CE

	From	To	Count	Threshold
Bin	0	1	47528721	1
Bin	1	0	47530322	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

 tq_counter_expired = '1' or tq_reset = '1' 
 <---------LHS---------->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	80263633	1
Bin	False	True	4366570	1
Bin	True	False	84505374	1

"=" expression on line 166:

tq_counter_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	84630203	1
Bin	True	109227247	1

"=" expression on line 166:

tq_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	164769007	1
Bin	True	29088443	1

"=" expression on line 172:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 175:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	406686163	1
Bin	True	137105515	1

"=" expression on line 189:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	105554318	1
Bin	True	32799616	1

"or" expression on line 192:

 (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
  <----LHS----->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	47568358	1
Bin	False	True	41445388	1
Bin	True	False	16016679	1

"=" expression on line 192:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	89013746	1
Bin	True	25950019	1

"and" expression on line 192:

 tq_edge_i = '1' and ctrs_en = '1' 
 <-----LHS----->     <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	37752198	1
Bin	True	False	23372049	1
Bin	True	True	51378728	1

"=" expression on line 192:

tq_edge_i = '1'

	Evaluated to	Count	Threshold
Bin	False	40212988	1
Bin	True	74750777	1

"=" expression on line 192:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	25832839	1
Bin	True	89130926	1

"=" expression on line 198:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 201:

segm_counter_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	438248538	1
Bin	True	105543140	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_DBT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

Signal assignment statement on line 155:

Signal assignment statement on line 157:

If statement on lines 165 to 168:

Signal assignment statement on line 166:

Signal assignment statement on line 168:

If statement on lines 172 to 178:

Signal assignment statement on line 173:

If statement on lines 175 to 177:

Signal assignment statement on line 176:

Signal assignment statement on line 184:

If statement on lines 189 to 190:

Signal assignment statement on line 189:

Signal assignment statement on line 190:

If statement on lines 192 to 194:

Signal assignment statement on line 192:

Signal assignment statement on line 194:

If statement on lines 198 to 204:

Signal assignment statement on line 199:

If statement on lines 201 to 203:

Signal assignment statement on line 202:

Signal assignment statement on line 210:

Signal assignment statement on line 211:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 172:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 175:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 192:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 200:

"if" / "when" / "else" condition on line 201:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 172:

"=" expression on line 175:

"=" expression on line 189:

"or" expression on line 192:

"=" expression on line 192:

"and" expression on line 192:

"=" expression on line 192:

"=" expression on line 192:

"=" expression on line 198:

"=" expression on line 201:

Uncovered FSM states:

Excluded FSM states: