NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST.SEGM_END_REQ_CAPTURE(1)	100.0 % (10/10)	100.0 % (10/10)	N.A.	100.0 % (13/13)	N.A.	N.A.	100.0 % (33/33)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

198:        segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else 
199:                                  req_input(i);

Count: 75694457
Threshold: 1

Signal assignment statement:

198: segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else
Count: 41208791
Threshold: 1

Signal assignment statement:

199: req_input(i);
Count: 34485666
Threshold: 1

If statement:

201:        segm_end_req_capt_ce(i) <= 
202:            '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else 
203:            '0';

Count: 75694457
Threshold: 1

Signal assignment statement:

202: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else
Count: 53588868
Threshold: 1

Signal assignment statement:

203: '0';
Count: 22105589
Threshold: 1

If statement:

207:            if (res_n = '0') then 
208:                segm_end_req_capt_q(i) <= '0'; 
...
212:                end if; 
213:            end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

208: segm_end_req_capt_q(i) <= '0';
Count: 2418499
Threshold: 1

If statement:

210:                if (segm_end_req_capt_ce(i) = '1') then 
211:                    segm_end_req_capt_q(i) <= segm_end_req_capt_d(i); 
212:                end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

211: segm_end_req_capt_q(i) <= segm_end_req_capt_d(i);
Count: 39429158
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

198: segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else

	Evaluated to	Count	Threshold
Bin	True	41208791	1
Bin	False	34485666	1

"if" / "when" / "else" condition:

202: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else

	Evaluated to	Count	Threshold
Bin	True	53588868	1
Bin	False	22105589	1

"if" / "when" / "else" condition:

207: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

209: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

210: if (segm_end_req_capt_ce(i) = '1') then

	Evaluated to	Count	Threshold
Bin	True	39429158	1
Bin	False	486945142	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

"or" expression

202:            '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else 
                          <------------LHS------------->    <------RHS------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

Covered expressions:

"=" expression

198: segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else

	Evaluated to	Count	Threshold
Bin	False	34485666	1
Bin	True	41208791	1

"=" expression

202: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else

	Evaluated to	Count	Threshold
Bin	False	34485666	1
Bin	True	41208791	1

"=" expression

202: '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else

	Evaluated to	Count	Threshold
Bin	False	22105589	1
Bin	True	12380077	1

"or" expression

202:            '1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else 
                          <------------LHS------------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	22105589	1
Bin	False	True	12380077	1

"=" expression

207: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

210: if (segm_end_req_capt_ce(i) = '1') then

	Evaluated to	Count	Threshold
Bin	False	486945142	1
Bin	True	39429158	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.SEGMENT_END_DETECTOR_INST.SEGM_END_REQ_CAPTURE(1)

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

"or" expression

Covered expressions:

"=" expression

"=" expression

"=" expression

"or" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: