NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.FILT_SUP_GEN_TRUE	100.0 % (11/11)	100.0 % (10/10)	N.A.	100.0 % (30/30)	N.A.	N.A.	100.0 % (51/51)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED 
359:                                    and rec_is_rtr = RTR_FRAME) 
360:                              else 
361:                          '0';

Count: 29542
Threshold: 1

Signal assignment statement:

358: drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED
Count: 4
Threshold: 1

Signal assignment statement:

361: '0';
Count: 29538
Threshold: 1

If statement:

363:        filter_result <= '1' when (rec_ivld = '0') else 
364:                         '0' when (drop_rtr_frame = '1') else 
...
369:                             else 
370:                         '0';

Count: 46717
Threshold: 1

Signal assignment statement:

363: filter_result <= '1' when (rec_ivld = '0') else
Count: 23371
Threshold: 1

Signal assignment statement:

364: '0' when (drop_rtr_frame = '1') else
Count: 4
Threshold: 1

Signal assignment statement:

365: '1' when (int_filter_a_valid = '1' or
Count: 19200
Threshold: 1

Signal assignment statement:

370: '0';
Count: 4142
Threshold: 1

If statement:

372:        ident_valid_d <=  filter_result when (mr_mode_afm = '1') 
373:                                        else 
374:                                    '1';

Count: 8404
Threshold: 1

Signal assignment statement:

372: ident_valid_d <= filter_result when (mr_mode_afm = '1')
Count: 5704
Threshold: 1

Signal assignment statement:

374: '1';
Count: 2700
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED 
359:                                    and rec_is_rtr = RTR_FRAME)

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	29538	1

"if" / "when" / "else" condition:

363: filter_result <= '1' when (rec_ivld = '0') else

	Evaluated to	Count	Threshold
Bin	True	23371	1
Bin	False	23346	1

"if" / "when" / "else" condition:

364: '0' when (drop_rtr_frame = '1') else

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	23342	1

"if" / "when" / "else" condition:

365:                         '1' when (int_filter_a_valid = '1' or 
366:                                   int_filter_b_valid = '1' or 
367:                                   int_filter_c_valid = '1' or 
368:                                   int_filter_ran_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	19200	1
Bin	False	4142	1

"if" / "when" / "else" condition:

372: ident_valid_d <= filter_result when (mr_mode_afm = '1')

	Evaluated to	Count	Threshold
Bin	True	5704	1
Bin	False	2700	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

358: drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED

	Evaluated to	Count	Threshold
Bin	False	29534	1
Bin	True	8	1

"=" expression

359: and rec_is_rtr = RTR_FRAME)

	Evaluated to	Count	Threshold
Bin	False	15761	1
Bin	True	13781	1

"and" expression

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED 
359:                                    and rec_is_rtr = RTR_FRAME)

	LHS	RHS	Count	Threshold
Bin	False	True	13777	1
Bin	True	False	4	1
Bin	True	True	4	1

"=" expression

363: filter_result <= '1' when (rec_ivld = '0') else

	Evaluated to	Count	Threshold
Bin	False	23346	1
Bin	True	23371	1

"=" expression

364: '0' when (drop_rtr_frame = '1') else

	Evaluated to	Count	Threshold
Bin	False	23342	1
Bin	True	4	1

"=" expression

365: '1' when (int_filter_a_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	4432	1
Bin	True	18910	1

"=" expression

366: int_filter_b_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	23040	1
Bin	True	302	1

"or" expression

365:                         '1' when (int_filter_a_valid = '1' or 
366:                                   int_filter_b_valid = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	4295	1
Bin	False	True	137	1
Bin	True	False	18745	1

"=" expression

367: int_filter_c_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	23028	1
Bin	True	314	1

"or" expression

365:                         '1' when (int_filter_a_valid = '1' or 
366:                                   int_filter_b_valid = '1' or 
367:                                   int_filter_c_valid = '1' or

	LHS	RHS	Count	Threshold
Bin	False	False	4146	1
Bin	False	True	149	1
Bin	True	False	18882	1

"=" expression

368: int_filter_ran_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	23173	1
Bin	True	169	1

"or" expression

365:                         '1' when (int_filter_a_valid = '1' or 
366:                                   int_filter_b_valid = '1' or 
367:                                   int_filter_c_valid = '1' or 
368:                                   int_filter_ran_valid = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	4142	1
Bin	False	True	4	1
Bin	True	False	19031	1

"=" expression

372: ident_valid_d <= filter_result when (mr_mode_afm = '1')

	Evaluated to	Count	Threshold
Bin	False	2700	1
Bin	True	5704	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.FILT_SUP_GEN_TRUE

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"=" expression

"=" expression

"or" expression

"=" expression

"or" expression

"=" expression

"or" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: