NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.FILT_SUP_GEN_TRUE	100.0 % (11/11)	100.0 % (10/10)	N.A.	100.0 % (30/30)	N.A.	N.A.	100.0 % (51/51)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.FILT_SUP_GEN_TRUE

100.0 % (11/11)

100.0 % (10/10)

N.A.

100.0 % (30/30)

N.A.

100.0 % (51/51)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 358 to 361:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED 
359:                                    and rec_is_rtr = RTR_FRAME) 
360:                              else 
361:                          '0';

Count: 28730
Threshold: 1

Signal assignment statement on line 358:

358: drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED
Count: 4
Threshold: 1

Signal assignment statement on line 361:

361: '0';
Count: 28726
Threshold: 1

If statement on lines 363 to 370:

363:        filter_result <= '1' when (rec_ivld = '0') else 
364:                         '0' when (drop_rtr_frame = '1') else 
...
369:                             else 
370:                         '0';

Count: 47443
Threshold: 1

Signal assignment statement on line 363:

363: filter_result <= '1' when (rec_ivld = '0') else
Count: 23667
Threshold: 1

Signal assignment statement on line 364:

364: '0' when (drop_rtr_frame = '1') else
Count: 4
Threshold: 1

Signal assignment statement on line 365:

365: '1' when (int_filter_a_valid = '1' or
Count: 19591
Threshold: 1

Signal assignment statement on line 370:

370: '0';
Count: 4181
Threshold: 1

If statement on lines 372 to 374:

372:        ident_valid_d <=  filter_result when (mr_mode_afm = '1') 
373:                                        else 
374:                                    '1';

Count: 8482
Threshold: 1

Signal assignment statement on line 372:

372: ident_valid_d <= filter_result when (mr_mode_afm = '1')
Count: 5782
Threshold: 1

Signal assignment statement on line 374:

374: '1';
Count: 2700
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 358 to 359:

358:        drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED 
359:                                    and rec_is_rtr = RTR_FRAME)

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	28726	1

"if" / "when" / "else" condition on line 363:

363: filter_result <= '1' when (rec_ivld = '0') else

	Evaluated to	Count	Threshold
Bin	True	23667	1
Bin	False	23776	1

"if" / "when" / "else" condition on line 364:

364: '0' when (drop_rtr_frame = '1') else

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	23772	1

"if" / "when" / "else" condition on lines 365 to 368:

365:                         '1' when (int_filter_a_valid = '1' or 
366:                                   int_filter_b_valid = '1' or 
367:                                   int_filter_c_valid = '1' or 
368:                                   int_filter_ran_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	19591	1
Bin	False	4181	1

"if" / "when" / "else" condition on line 372:

372: ident_valid_d <= filter_result when (mr_mode_afm = '1')

	Evaluated to	Count	Threshold
Bin	True	5782	1
Bin	False	2700	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on lines 358 to 359:

 mr_settings_fdrf = DROP_RF_ENABLED and rec_is_rtr = RTR_FRAME 
 <--------------LHS--------------->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	13371	1
Bin	True	False	4	1
Bin	True	True	4	1

"=" expression on line 358:

mr_settings_fdrf = DROP_RF_ENABLED

	Evaluated to	Count	Threshold
Bin	False	28722	1
Bin	True	8	1

"=" expression on line 359:

rec_is_rtr = RTR_FRAME

	Evaluated to	Count	Threshold
Bin	False	15355	1
Bin	True	13375	1

"=" expression on line 363:

rec_ivld = '0'

	Evaluated to	Count	Threshold
Bin	False	23776	1
Bin	True	23667	1

"=" expression on line 364:

drop_rtr_frame = '1'

	Evaluated to	Count	Threshold
Bin	False	23772	1
Bin	True	4	1

"or" expression on lines 365 to 368:

 int_filter_a_valid = '1' or int_filter_b_valid = '1' or int_filter_c_valid = '1' or int_filter_ran_valid = '1' 
 <-------------------------------------LHS-------------------------------------->    <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	4181	1
Bin	False	True	3	1
Bin	True	False	19423	1

"or" expression on lines 365 to 367:

 int_filter_a_valid = '1' or int_filter_b_valid = '1' or int_filter_c_valid = '1' 
 <-----------------------LHS------------------------>    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	4184	1
Bin	False	True	151	1
Bin	True	False	19272	1

"or" expression on lines 365 to 366:

 int_filter_a_valid = '1' or int_filter_b_valid = '1' 
 <---------LHS---------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	4335	1
Bin	False	True	167	1
Bin	True	False	19105	1

"=" expression on line 365:

int_filter_a_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	4502	1
Bin	True	19270	1

"=" expression on line 366:

int_filter_b_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	23440	1
Bin	True	332	1

"=" expression on line 367:

int_filter_c_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	23456	1
Bin	True	316	1

"=" expression on line 368:

int_filter_ran_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	23604	1
Bin	True	168	1

"=" expression on line 372:

mr_mode_afm = '1'

	Evaluated to	Count	Threshold
Bin	False	2700	1
Bin	True	5782	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.FILT_SUP_GEN_TRUE