NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TXTB_PORT_A_CS_GEN(6)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TXTB_PORT_A_CS_GEN(6)

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (5/5)

N.A.

100.0 % (10/10)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 376 to 378:

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1') 
377:                                 else 
378:                             '0';

Count: 10611399
Threshold: 1

Signal assignment statement on line 376:

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1')

Count: 11345
Threshold: 1

Signal assignment statement on line 378:

378: '0';
Count: 10600054
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 376:

376:        txtb_port_a_cs(i) <= '1' when (adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1')

	Evaluated to	Count	Threshold
Bin	True	11345	1
Bin	False	10600054	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 376:

 adress(11 downto 8) = buf_addr(i) and scs_and_swr = '1' 
 <--------------LHS-------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	501127	1
Bin	True	False	11366	1
Bin	True	True	11345	1

"=" expression on line 376:

scs_and_swr = '1'

	Evaluated to	Count	Threshold
Bin	False	10098927	1
Bin	True	512472	1