NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.PRIORITY_DECODER_INST.FILL_ZEROES_GEN

File:  /__w/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/priority_decoder.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.PRIORITY_DECODER_INST.FILL_ZEROES_GEN 100.0 % (2/2) N.A. N.A. N.A. N.A. N.A. 100.0 % (2/2)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Signal assignment statement:

191:        l0_prio(7 downto G_TXT_BUFFER_COUNT)  <= (others => (others => '0')); 
Count: 1435
Threshold: 1

Signal assignment statement:

192:        l0_valid(7 downto G_TXT_BUFFER_COUNT) <= (others => '0'); 
Count: 1435
Threshold: 1

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