NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 4393
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 4393
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 140576
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 4393
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	316	1
Bin	1	0	471	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	254	1
Bin	1	0	409	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	248	1
Bin	1	0	403	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	827	1
Bin	1	0	978	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	714	1
Bin	1	0	865	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	715	1
Bin	1	0	863	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	510	1
Bin	1	0	659	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	496	1
Bin	1	0	646	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	902	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	608	1
Bin	1	0	759	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	546	1
Bin	1	0	694	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	771	1
Bin	1	0	920	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	774	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	760	1
Bin	1	0	910	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	449	1
Bin	1	0	600	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	397	1
Bin	1	0	551	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	607	1
Bin	1	0	759	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	398	1
Bin	1	0	552	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	633	1
Bin	1	0	786	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	454	1
Bin	1	0	605	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	645	1
Bin	1	0	796	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	822	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	960	1
Bin	1	0	1109	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	684	1
Bin	1	0	835	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	1064	1
Bin	1	0	1208	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	825	1
Bin	1	0	974	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	504	1
Bin	1	0	654	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	600	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	791	1
Bin	1	0	940	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	946	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	793	1
Bin	1	0	943	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	567	1
Bin	1	0	710	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	1130	1
Bin	1	0	984	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	29664	1
Bin	'0'	'1'	12089	1
Bin	'1'	'0'	80194	1
Bin	'1'	'1'	13349	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

Loop statement:

Variable assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: