NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BYTE_SHIFT_REG_GEN(0)	100.0 % (6/6)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (16/16)
BYTE_SHIFT_REG_GEN(1)	100.0 % (8/8)	100.0 % (8/8)	N.A.	100.0 % (6/6)	N.A.	N.A.	100.0 % (22/22)
BYTE_SHIFT_REG_GEN(2)	100.0 % (8/8)	100.0 % (8/8)	N.A.	100.0 % (6/6)	N.A.	N.A.	100.0 % (22/22)
BYTE_SHIFT_REG_GEN(3)	100.0 % (8/8)	100.0 % (8/8)	N.A.	100.0 % (6/6)	N.A.	N.A.	100.0 % (22/22)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BYTE_SHIFT_REG_GEN(0)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (16/16)

BYTE_SHIFT_REG_GEN(1)

100.0 % (8/8)

N.A.

100.0 % (6/6)

N.A.

100.0 % (22/22)

BYTE_SHIFT_REG_GEN(2)

100.0 % (8/8)

N.A.

100.0 % (6/6)

N.A.

100.0 % (22/22)

BYTE_SHIFT_REG_GEN(3)

100.0 % (8/8)

N.A.

100.0 % (6/6)

N.A.

100.0 % (22/22)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST	N.A.	N.A.	100.0 % (156/156)	N.A.	N.A.	N.A.	100.0 % (156/156)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST

N.A.

100.0 % (156/156)

N.A.

100.0 % (156/156)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

CLK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INPUT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BYTE_CLOCK_ENA

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

BYTE_INPUT_SEL

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file

Covered toggles:

Port:

REG_STAT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	797759	1
Bin	(31)	1	0	1345915	1
Bin	(30)	0	1	738481	1
Bin	(30)	1	0	1349417	1
Bin	(29)	0	1	677978	1
Bin	(29)	1	0	1555654	1
Bin	(28)	0	1	760142	1
Bin	(28)	1	0	1481744	1
Bin	(27)	0	1	696020	1
Bin	(27)	1	0	1583015	1
Bin	(26)	0	1	774677	1
Bin	(26)	1	0	1515531	1
Bin	(25)	0	1	701865	1
Bin	(25)	1	0	1589944	1
Bin	(24)	0	1	784525	1
Bin	(24)	1	0	1526151	1
Bin	(23)	0	1	1291518	1
Bin	(23)	1	0	2224621	1
Bin	(22)	0	1	794540	1
Bin	(22)	1	0	1477398	1
Bin	(21)	0	1	737786	1
Bin	(21)	1	0	1514058	1
Bin	(20)	0	1	856090	1
Bin	(20)	1	0	1425752	1
Bin	(19)	0	1	760767	1
Bin	(19)	1	0	1382985	1
Bin	(18)	0	1	837605	1
Bin	(18)	1	0	1329565	1
Bin	(17)	0	1	762767	1
Bin	(17)	1	0	1350229	1
Bin	(16)	0	1	831637	1
Bin	(16)	1	0	1308141	1
Bin	(15)	0	1	825661	1
Bin	(15)	1	0	1160139	1
Bin	(14)	0	1	1066153	1
Bin	(14)	1	0	1084820	1
Bin	(13)	0	1	873022	1
Bin	(13)	1	0	1252658	1
Bin	(12)	0	1	1054228	1
Bin	(12)	1	0	1117151	1
Bin	(11)	0	1	900807	1
Bin	(11)	1	0	1276765	1
Bin	(10)	0	1	1083937	1
Bin	(10)	1	0	1166460	1
Bin	(9)	0	1	920833	1
Bin	(9)	1	0	1293150	1
Bin	(8)	0	1	1096885	1
Bin	(8)	1	0	1162967	1
Bin	(7)	0	1	977828	1
Bin	(7)	1	0	1371345	1
Bin	(6)	0	1	1073700	1
Bin	(6)	1	0	1046427	1
Bin	(5)	0	1	1048643	1
Bin	(5)	1	0	1145000	1
Bin	(4)	0	1	1146015	1
Bin	(4)	1	0	1094256	1
Bin	(3)	0	1	1046930	1
Bin	(3)	1	0	1243314	1
Bin	(2)	0	1	1732267	1
Bin	(2)	1	0	1631364	1
Bin	(1)	0	1	1073389	1
Bin	(1)	1	0	1101870	1
Bin	(0)	0	1	1123379	1
Bin	(0)	1	0	1076052	1

Signal:

SHIFT_REG_Q

	Element	From	To	Count	Threshold
Bin	(0)(7)	0	1	2542245	1
Bin	(0)(7)	1	0	3305269	1
Bin	(0)(6)	0	1	1100526	1
Bin	(0)(6)	1	0	983407	1
Bin	(0)(5)	0	1	1048643	1
Bin	(0)(5)	1	0	1058619	1
Bin	(0)(4)	0	1	1146015	1
Bin	(0)(4)	1	0	1015716	1
Bin	(0)(3)	0	1	1046930	1
Bin	(0)(3)	1	0	1172171	1
Bin	(0)(2)	0	1	1134133	1
Bin	(0)(2)	1	0	1045383	1
Bin	(0)(1)	0	1	1073389	1
Bin	(0)(1)	1	0	1101870	1
Bin	(0)(0)	0	1	1123379	1
Bin	(0)(0)	1	0	1076052	1
Bin	(1)(7)	0	1	2385654	1
Bin	(1)(7)	1	0	3461860	1
Bin	(1)(6)	0	1	1090367	1
Bin	(1)(6)	1	0	1103071	1
Bin	(1)(5)	0	1	873022	1
Bin	(1)(5)	1	0	1252658	1
Bin	(1)(4)	0	1	1054228	1
Bin	(1)(4)	1	0	1117151	1
Bin	(1)(3)	0	1	900807	1
Bin	(1)(3)	1	0	1276765	1
Bin	(1)(2)	0	1	1083937	1
Bin	(1)(2)	1	0	1166460	1
Bin	(1)(1)	0	1	920833	1
Bin	(1)(1)	1	0	1293150	1
Bin	(1)(0)	0	1	1096885	1
Bin	(1)(0)	1	0	1162967	1
Bin	(2)(7)	0	1	2163010	1
Bin	(2)(7)	1	0	3684504	1
Bin	(2)(6)	0	1	817018	1
Bin	(2)(6)	1	0	1349250	1
Bin	(2)(5)	0	1	737786	1
Bin	(2)(5)	1	0	1344272	1
Bin	(2)(4)	0	1	814041	1
Bin	(2)(4)	1	0	1267755	1
Bin	(2)(3)	0	1	760767	1
Bin	(2)(3)	1	0	1382985	1
Bin	(2)(2)	0	1	837605	1
Bin	(2)(2)	1	0	1329565	1
Bin	(2)(1)	0	1	762767	1
Bin	(2)(1)	1	0	1350229	1
Bin	(2)(0)	0	1	831637	1
Bin	(2)(0)	1	0	1308141	1
Bin	(3)(7)	0	1	797759	1
Bin	(3)(7)	1	0	1345915	1
Bin	(3)(6)	0	1	738481	1
Bin	(3)(6)	1	0	1349417	1
Bin	(3)(5)	0	1	677978	1
Bin	(3)(5)	1	0	1555654	1
Bin	(3)(4)	0	1	760142	1
Bin	(3)(4)	1	0	1481744	1
Bin	(3)(3)	0	1	696020	1
Bin	(3)(3)	1	0	1583015	1
Bin	(3)(2)	0	1	774677	1
Bin	(3)(2)	1	0	1515531	1
Bin	(3)(1)	0	1	701865	1
Bin	(3)(1)	1	0	1589944	1
Bin	(3)(0)	0	1	784525	1
Bin	(3)(0)	1	0	1526151	1

Signal:

SHIFT_REG_IN

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1270694	1
Bin	(3)	1	0	2434874	1
Bin	(2)	0	1	1349104	1
Bin	(2)	1	0	2356464	1
Bin	(1)	0	1	1620275	1
Bin	(1)	1	0	2085293	1
Bin	(0)	0	1	1870300	1
Bin	(0)	1	0	1836869	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: