Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.SHIFT_REG_BYTE_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| BYTE_SHIFT_REG_GEN(0) |
100.0 % (4/4) |
100.0 % (6/6) |
N.A. |
100.0 % (4/4) |
N.A. |
N.A. |
100.0 % (14/14) |
| BYTE_SHIFT_REG_GEN(1) |
100.0 % (7/7) |
100.0 % (8/8) |
N.A. |
100.0 % (6/6) |
N.A. |
N.A. |
100.0 % (21/21) |
| BYTE_SHIFT_REG_GEN(2) |
100.0 % (7/7) |
100.0 % (8/8) |
N.A. |
100.0 % (6/6) |
N.A. |
N.A. |
100.0 % (21/21) |
| BYTE_SHIFT_REG_GEN(3) |
100.0 % (7/7) |
100.0 % (8/8) |
N.A. |
100.0 % (6/6) |
N.A. |
N.A. |
100.0 % (21/21) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered toggles:
Port:
CLK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63366 | 1 |
| Bin | 1 | 0 | 63357 | 1 |
Port:
INPUT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Port:
BYTE_CLOCK_ENA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2782947 | 1 |
| Bin | 1 | 0 | 9714712 | 1 |
Port:
BYTE_CLOCK_ENA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2827443 | 1 |
| Bin | 1 | 0 | 9670216 | 1 |
Port:
BYTE_CLOCK_ENA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2876978 | 1 |
| Bin | 1 | 0 | 9620681 | 1 |
Port:
BYTE_CLOCK_ENA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3011469 | 1 |
| Bin | 1 | 0 | 9486190 | 1 |
Port:
BYTE_INPUT_SEL(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
BYTE_INPUT_SEL(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
BYTE_INPUT_SEL(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
REG_STAT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 809143 | 1 |
| Bin | 1 | 0 | 1320780 | 1 |
Port:
REG_STAT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 755072 | 1 |
| Bin | 1 | 0 | 1327389 | 1 |
Port:
REG_STAT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 675152 | 1 |
| Bin | 1 | 0 | 1551895 | 1 |
Port:
REG_STAT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 756520 | 1 |
| Bin | 1 | 0 | 1450822 | 1 |
Port:
REG_STAT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 720758 | 1 |
| Bin | 1 | 0 | 1527004 | 1 |
Port:
REG_STAT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 765596 | 1 |
| Bin | 1 | 0 | 1536247 | 1 |
Port:
REG_STAT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 721335 | 1 |
| Bin | 1 | 0 | 1617287 | 1 |
Port:
REG_STAT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 788309 | 1 |
| Bin | 1 | 0 | 1544140 | 1 |
Port:
REG_STAT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1291605 | 1 |
| Bin | 1 | 0 | 2231838 | 1 |
Port:
REG_STAT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 800362 | 1 |
| Bin | 1 | 0 | 1485632 | 1 |
Port:
REG_STAT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 748554 | 1 |
| Bin | 1 | 0 | 1490404 | 1 |
Port:
REG_STAT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 857095 | 1 |
| Bin | 1 | 0 | 1398168 | 1 |
Port:
REG_STAT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 764539 | 1 |
| Bin | 1 | 0 | 1415260 | 1 |
Port:
REG_STAT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 827969 | 1 |
| Bin | 1 | 0 | 1286814 | 1 |
Port:
REG_STAT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 785177 | 1 |
| Bin | 1 | 0 | 1377833 | 1 |
Port:
REG_STAT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 852005 | 1 |
| Bin | 1 | 0 | 1324565 | 1 |
Port:
REG_STAT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 834900 | 1 |
| Bin | 1 | 0 | 1168195 | 1 |
Port:
REG_STAT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1068357 | 1 |
| Bin | 1 | 0 | 1079565 | 1 |
Port:
REG_STAT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 876473 | 1 |
| Bin | 1 | 0 | 1276591 | 1 |
Port:
REG_STAT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1051105 | 1 |
| Bin | 1 | 0 | 1120047 | 1 |
Port:
REG_STAT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 912126 | 1 |
| Bin | 1 | 0 | 1296182 | 1 |
Port:
REG_STAT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1081343 | 1 |
| Bin | 1 | 0 | 1133074 | 1 |
Port:
REG_STAT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 932226 | 1 |
| Bin | 1 | 0 | 1330255 | 1 |
Port:
REG_STAT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1115680 | 1 |
| Bin | 1 | 0 | 1176644 | 1 |
Port:
REG_STAT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 987526 | 1 |
| Bin | 1 | 0 | 1359350 | 1 |
Port:
REG_STAT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1076044 | 1 |
| Bin | 1 | 0 | 1060727 | 1 |
Port:
REG_STAT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1073077 | 1 |
| Bin | 1 | 0 | 1141412 | 1 |
Port:
REG_STAT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1126778 | 1 |
| Bin | 1 | 0 | 1111461 | 1 |
Port:
REG_STAT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1047270 | 1 |
| Bin | 1 | 0 | 1263068 | 1 |
Port:
REG_STAT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1741862 | 1 |
| Bin | 1 | 0 | 1618121 | 1 |
Port:
REG_STAT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1084527 | 1 |
| Bin | 1 | 0 | 1106097 | 1 |
Port:
REG_STAT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1129593 | 1 |
| Bin | 1 | 0 | 1071794 | 1 |
Signal:
SHIFT_REG_Q(0)(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2562726 | 1 |
| Bin | 1 | 0 | 3272046 | 1 |
Signal:
SHIFT_REG_Q(0)(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1104280 | 1 |
| Bin | 1 | 0 | 988261 | 1 |
Signal:
SHIFT_REG_Q(0)(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1073077 | 1 |
| Bin | 1 | 0 | 1054318 | 1 |
Signal:
SHIFT_REG_Q(0)(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1126778 | 1 |
| Bin | 1 | 0 | 1032697 | 1 |
Signal:
SHIFT_REG_Q(0)(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1047270 | 1 |
| Bin | 1 | 0 | 1185182 | 1 |
Signal:
SHIFT_REG_Q(0)(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1133117 | 1 |
| Bin | 1 | 0 | 1042176 | 1 |
Signal:
SHIFT_REG_Q(0)(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1084527 | 1 |
| Bin | 1 | 0 | 1106097 | 1 |
Signal:
SHIFT_REG_Q(0)(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1129593 | 1 |
| Bin | 1 | 0 | 1071794 | 1 |
Signal:
SHIFT_REG_Q(1)(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2392420 | 1 |
| Bin | 1 | 0 | 3442352 | 1 |
Signal:
SHIFT_REG_Q(1)(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1092517 | 1 |
| Bin | 1 | 0 | 1096819 | 1 |
Signal:
SHIFT_REG_Q(1)(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 876473 | 1 |
| Bin | 1 | 0 | 1276591 | 1 |
Signal:
SHIFT_REG_Q(1)(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1051105 | 1 |
| Bin | 1 | 0 | 1120047 | 1 |
Signal:
SHIFT_REG_Q(1)(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 912126 | 1 |
| Bin | 1 | 0 | 1296182 | 1 |
Signal:
SHIFT_REG_Q(1)(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1081343 | 1 |
| Bin | 1 | 0 | 1133074 | 1 |
Signal:
SHIFT_REG_Q(1)(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 932226 | 1 |
| Bin | 1 | 0 | 1330255 | 1 |
Signal:
SHIFT_REG_Q(1)(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1115680 | 1 |
| Bin | 1 | 0 | 1176644 | 1 |
Signal:
SHIFT_REG_Q(2)(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2169533 | 1 |
| Bin | 1 | 0 | 3665239 | 1 |
Signal:
SHIFT_REG_Q(2)(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 822421 | 1 |
| Bin | 1 | 0 | 1355023 | 1 |
Signal:
SHIFT_REG_Q(2)(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 748554 | 1 |
| Bin | 1 | 0 | 1327830 | 1 |
Signal:
SHIFT_REG_Q(2)(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 816311 | 1 |
| Bin | 1 | 0 | 1258872 | 1 |
Signal:
SHIFT_REG_Q(2)(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 764539 | 1 |
| Bin | 1 | 0 | 1415260 | 1 |
Signal:
SHIFT_REG_Q(2)(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 827969 | 1 |
| Bin | 1 | 0 | 1286814 | 1 |
Signal:
SHIFT_REG_Q(2)(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 785177 | 1 |
| Bin | 1 | 0 | 1377833 | 1 |
Signal:
SHIFT_REG_Q(2)(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 852005 | 1 |
| Bin | 1 | 0 | 1324565 | 1 |
Signal:
SHIFT_REG_Q(3)(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 809143 | 1 |
| Bin | 1 | 0 | 1320780 | 1 |
Signal:
SHIFT_REG_Q(3)(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 755072 | 1 |
| Bin | 1 | 0 | 1327389 | 1 |
Signal:
SHIFT_REG_Q(3)(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 675152 | 1 |
| Bin | 1 | 0 | 1551895 | 1 |
Signal:
SHIFT_REG_Q(3)(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 756520 | 1 |
| Bin | 1 | 0 | 1450822 | 1 |
Signal:
SHIFT_REG_Q(3)(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 720758 | 1 |
| Bin | 1 | 0 | 1527004 | 1 |
Signal:
SHIFT_REG_Q(3)(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 765596 | 1 |
| Bin | 1 | 0 | 1536247 | 1 |
Signal:
SHIFT_REG_Q(3)(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 721335 | 1 |
| Bin | 1 | 0 | 1617287 | 1 |
Signal:
SHIFT_REG_Q(3)(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 788309 | 1 |
| Bin | 1 | 0 | 1544140 | 1 |
Signal:
SHIFT_REG_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1259845 | 1 |
| Bin | 1 | 0 | 2427356 | 1 |
Signal:
SHIFT_REG_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1336891 | 1 |
| Bin | 1 | 0 | 2350310 | 1 |
Signal:
SHIFT_REG_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1616456 | 1 |
| Bin | 1 | 0 | 2070745 | 1 |
Signal:
SHIFT_REG_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1864091 | 1 |
| Bin | 1 | 0 | 1824710 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: