NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST.INT_MODULE_GEN(4).INT_MODULE_INST	100.0 % (18/18)	100.0 % (24/24)	100.0 % (30/30)	100.0 % (26/26)	N.A.	N.A.	100.0 % (98/98)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

159:        if (res_n = '0') then 
160:            int_status <= '0'; 
...
172:            end if; 
173:        end if;

Count: 1055178613
Threshold: 1

Signal assignment statement:

160: int_status <= '0';
Count: 67326
Threshold: 1

If statement:

165:            if (int_status_set = '1' and int_mask_i = '0') then 
166:                int_status <= '1'; 
...
171: 
172:            end if;

Count: 527548992
Threshold: 1

Signal assignment statement:

166: int_status <= '1';
Count: 7836
Threshold: 1

Signal assignment statement:

170: int_status <= '0';
Count: 80
Threshold: 1

If statement:

183:        if (res_n = '0') then 
184:            int_mask_i <= '0'; 
...
192: 
193:        end if;

Count: 1055178613
Threshold: 1

Signal assignment statement:

184: int_mask_i <= '0';
Count: 67326
Threshold: 1

If statement:

189:            if (int_mask_load = '1') then 
190:                int_mask_i <= int_mask_next; 
191:            end if;

Count: 527548992
Threshold: 1

Signal assignment statement:

190: int_mask_i <= int_mask_next;
Count: 475
Threshold: 1

Signal assignment statement:

196: int_mask_load <= int_mask_set or int_mask_clear;
Count: 5575
Threshold: 1

If statement:

197:    int_mask_next <= '1' when (int_mask_set = '1') 
198:                         else 
199:                     '0';

Count: 4160
Threshold: 1

Signal assignment statement:

197: int_mask_next <= '1' when (int_mask_set = '1')
Count: 10
Threshold: 1

Signal assignment statement:

199: '0';
Count: 4150
Threshold: 1

If statement:

206:        if (res_n = '0') then 
207:            int_ena_i <= '0'; 
...
219:            end if; 
220:        end if;

Count: 1055178613
Threshold: 1

Signal assignment statement:

207: int_ena_i <= '0';
Count: 67326
Threshold: 1

If statement:

212:            if (int_ena_set = '1') then 
213:                int_ena_i <= '1'; 
...
218: 
219:            end if;

Count: 527548992
Threshold: 1

Signal assignment statement:

213: int_ena_i <= '1';
Count: 15
Threshold: 1

Signal assignment statement:

217: int_ena_i <= '0';
Count: 527
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

159: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	67326	1
Bin	False	1055111287	1

"if" / "when" / "else" condition:

162: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	527548992	1
Bin	False	527562295	1

"if" / "when" / "else" condition:

165: if (int_status_set = '1' and int_mask_i = '0') then

	Evaluated to	Count	Threshold
Bin	True	7836	1
Bin	False	527541156	1

"if" / "when" / "else" condition:

169: elsif (int_status_clear = '1') then

	Evaluated to	Count	Threshold
Bin	True	80	1
Bin	False	527541076	1

"if" / "when" / "else" condition:

183: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	67326	1
Bin	False	1055111287	1

"if" / "when" / "else" condition:

186: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	527548992	1
Bin	False	527562295	1

"if" / "when" / "else" condition:

189: if (int_mask_load = '1') then

	Evaluated to	Count	Threshold
Bin	True	475	1
Bin	False	527548517	1

"if" / "when" / "else" condition:

197: int_mask_next <= '1' when (int_mask_set = '1')

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	4150	1

"if" / "when" / "else" condition:

206: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	67326	1
Bin	False	1055111287	1

"if" / "when" / "else" condition:

209: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	527548992	1
Bin	False	527562295	1

"if" / "when" / "else" condition:

212: if (int_ena_set = '1') then

	Evaluated to	Count	Threshold
Bin	True	15	1
Bin	False	527548977	1

"if" / "when" / "else" condition:

216: elsif (int_ena_clear = '1') then

	Evaluated to	Count	Threshold
Bin	True	527	1
Bin	False	527548450	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

INT_STATUS_SET

	From	To	Count	Threshold
Bin	0	1	15989	1
Bin	1	0	17589	1

Port:

INT_STATUS_CLEAR

	From	To	Count	Threshold
Bin	0	1	80	1
Bin	1	0	1747	1

Port:

INT_MASK_SET

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	2075	1

Port:

INT_MASK_CLEAR

	From	To	Count	Threshold
Bin	0	1	465	1
Bin	1	0	2075	1

Port:

INT_ENA_SET

	From	To	Count	Threshold
Bin	0	1	15	1
Bin	1	0	2142	1

Port:

INT_ENA_CLEAR

	From	To	Count	Threshold
Bin	0	1	527	1
Bin	1	0	2142	1

Port:

INT_STATUS

	From	To	Count	Threshold
Bin	0	1	3303	1
Bin	1	0	4893	1

Port:

INT_MASK

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

INT_ENA

	From	To	Count	Threshold
Bin	0	1	15	1
Bin	1	0	1615	1

Signal:

INT_MASK_I

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

INT_ENA_I

	From	To	Count	Threshold
Bin	0	1	15	1
Bin	1	0	1615	1

Signal:

INT_MASK_LOAD

	From	To	Count	Threshold
Bin	0	1	475	1
Bin	1	0	2550	1

Signal:

INT_MASK_NEXT

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	1610	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

159: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1055111287	1
Bin	True	67326	1

"=" expression

165: if (int_status_set = '1' and int_mask_i = '0') then

	Evaluated to	Count	Threshold
Bin	False	527541151	1
Bin	True	7841	1

"=" expression

165: if (int_status_set = '1' and int_mask_i = '0') then

	Evaluated to	Count	Threshold
Bin	False	1690	1
Bin	True	527547302	1

"and" expression

165:            if (int_status_set = '1' and int_mask_i = '0') then 
                    <-------LHS-------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	527539466	1
Bin	True	False	5	1
Bin	True	True	7836	1

"=" expression

169: elsif (int_status_clear = '1') then

	Evaluated to	Count	Threshold
Bin	False	527541076	1
Bin	True	80	1

"=" expression

183: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1055111287	1
Bin	True	67326	1

"=" expression

189: if (int_mask_load = '1') then

	Evaluated to	Count	Threshold
Bin	False	527548517	1
Bin	True	475	1

"or" expression

196:    int_mask_load <= int_mask_set or int_mask_clear; 
                         <---LHS---->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	2550	1
Bin	'0'	'1'	465	1
Bin	'1'	'0'	10	1

"=" expression

197: int_mask_next <= '1' when (int_mask_set = '1')

	Evaluated to	Count	Threshold
Bin	False	4150	1
Bin	True	10	1

"=" expression

206: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1055111287	1
Bin	True	67326	1

"=" expression

212: if (int_ena_set = '1') then

	Evaluated to	Count	Threshold
Bin	False	527548977	1
Bin	True	15	1

"=" expression

216: elsif (int_ena_clear = '1') then

	Evaluated to	Count	Threshold
Bin	False	527548450	1
Bin	True	527	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.INT_MANAGER_INST.INT_MODULE_GEN(4).INT_MODULE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_module.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"=" expression

"or" expression

"=" expression

"=" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage: