File: /__w/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_module.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Single Interrupt module.
71: --
72: -- Purpose:
73: -- Contains Interrupt enable, Interrupt mask and Interrupt status.
74: --
75: -- Interrupt status can be set by "int_set" and cleared by "int_clear".
76: -- Preference is selected by "clear_priority". If "clear_priority = true",
77: -- clear has priority over set, otherwise set has priority over clear.
78: --
79: -- Interrupt mask is set by "int_mask_set" and cleared by "int_mask_clear".
80: -- Simulteneous set/clear of interrupt mask is not allowed!
81: --
82: -- Interrupt enable is set by "int_ena_set" and cleared by "int_ena_clear".
83: -- Simulteneous set/clear of interrupt mask is not allowed!
84: --
85: --------------------------------------------------------------------------------
86:
87: Library ieee;
88: use ieee.std_logic_1164.all;
89: use ieee.numeric_std.ALL;
90:
91: Library ctu_can_fd_rtl;
92: use ctu_can_fd_rtl.can_constants_pkg.all;
93: use ctu_can_fd_rtl.can_types_pkg.all;
94:
95: use ctu_can_fd_rtl.CAN_FD_register_map.all;
96: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
97:
98: entity int_module is
99: port (
100: -------------------------------------------------------------------------------------------
101: -- Clock and Asynchronous reset
102: -------------------------------------------------------------------------------------------
103: clk_sys :in std_logic;
104: res_n :in std_logic;
105:
106: -------------------------------------------------------------------------------------------
107: -- Control control signals
108: -------------------------------------------------------------------------------------------
109: -- Interrupt Status Set
110: int_status_set :in std_logic;
111:
112: -- Interrupt Status Clear
113: int_status_clear :in std_logic;
114:
115: -- Interrupt Mask Set
116: int_mask_set :in std_logic;
117:
118: -- Interrupt Mask Clear
119: int_mask_clear :in std_logic;
120:
121: -- Interrupt Enable Set
122: int_ena_set :in std_logic;
123:
124: -- Interrupt Enable Clear
125: int_ena_clear :in std_logic;
126:
127: -------------------------------------------------------------------------------------------
128: -- Interrupt output signals
129: -------------------------------------------------------------------------------------------
130: -- Interrupt status (Interrupt vector)
131: int_status :out std_logic;
132:
133: -- Interrupt mask
134: int_mask :out std_logic;
135:
136: -- Interrupt enable
137: int_ena :out std_logic
138: );
139: end entity;
140:
141: architecture rtl of int_module is
142:
143: -- Internal values
144: signal int_mask_i : std_logic;
145: signal int_ena_i : std_logic;
146:
147: -- Interrupt mask handling signals
148: signal int_mask_load : std_logic;
149: signal int_mask_next : std_logic;
150:
151: begin
152:
153: -----------------------------------------------------------------------------------------------
154: -- Interrupt status - Set priority
155: -----------------------------------------------------------------------------------------------
156: int_stat_proc : process(res_n, clk_sys)
157: begin
158: if (res_n = '0') then
159: int_status <= '0';
160:
161: elsif rising_edge(clk_sys) then
162:
163: -- Setting Interrupt
164: if (int_status_set = '1' and int_mask_i = '0') then
165: int_status <= '1';
166:
167: -- Clearing Interrupt
168: elsif (int_status_clear = '1') then
169: int_status <= '0';
170:
171: end if;
172: end if;
173: end process;
174:
175:
176: -----------------------------------------------------------------------------------------------
177: -- Interrupt mask
178: -----------------------------------------------------------------------------------------------
179:
180: int_mask_proc : process(res_n, clk_sys)
181: begin
182: if (res_n = '0') then
183: int_mask_i <= '0';
184:
185: elsif rising_edge(clk_sys) then
186:
187: -- Setting / Clearing Interrupt Mask
188: if (int_mask_load = '1') then
189: int_mask_i <= int_mask_next;
190: end if;
191:
192: end if;
193: end process;
194:
195: int_mask_load <= int_mask_set or int_mask_clear;
196: int_mask_next <= '1' when (int_mask_set = '1')
197: else
198: '0';
199:
200: -----------------------------------------------------------------------------------------------
201: -- Interrupt Enable
202: -----------------------------------------------------------------------------------------------
203: int_ena_proc : process(res_n, clk_sys)
204: begin
205: if (res_n = '0') then
206: int_ena_i <= '0';
207:
208: elsif rising_edge(clk_sys) then
209:
210: -- Setting Interrupt Mask
211: if (int_ena_set = '1') then
212: int_ena_i <= '1';
213:
214: -- Clearing Interrupt Mask
215: elsif (int_ena_clear = '1') then
216: int_ena_i <= '0';
217:
218: end if;
219: end if;
220: end process;
221:
222: -- Propagation to outputs
223: int_mask <= int_mask_i;
224: int_ena <= int_ena_i;
225:
226: end architecture;