NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXTB_PARITY_TRUE_GEN.TXTB_PORT_A_PARITY_CALCULATOR_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 1579020
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 1579020
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 50528640
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 1579020
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	26356	1
Bin	1	0	762824	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	28657	1
Bin	1	0	760523	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	27152	1
Bin	1	0	762028	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	44044	1
Bin	1	0	745136	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	37637	1
Bin	1	0	751543	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	35980	1
Bin	1	0	753200	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	49211	1
Bin	1	0	739969	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	36691	1
Bin	1	0	752489	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	35471	1
Bin	1	0	753709	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	44528	1
Bin	1	0	744652	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	38824	1
Bin	1	0	750356	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	37253	1
Bin	1	0	751927	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	64725	1
Bin	1	0	724455	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	84831	1
Bin	1	0	704349	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	79950	1
Bin	1	0	709230	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	141786	1
Bin	1	0	647394	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	33296	1
Bin	1	0	755884	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	41814	1
Bin	1	0	747366	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	36216	1
Bin	1	0	752964	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	40217	1
Bin	1	0	748963	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	58401	1
Bin	1	0	730779	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	61314	1
Bin	1	0	727866	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	79096	1
Bin	1	0	710084	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	80705	1
Bin	1	0	708475	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	68788	1
Bin	1	0	720392	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	65064	1
Bin	1	0	724116	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	65949	1
Bin	1	0	723231	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	83106	1
Bin	1	0	706074	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	90500	1
Bin	1	0	698680	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	100212	1
Bin	1	0	688968	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	165652	1
Bin	1	0	623528	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	141015	1
Bin	1	0	648165	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	640015	1
Bin	1	0	149165	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	3762251	1
Bin	'0'	'1'	937638	1
Bin	'1'	'0'	19467068	1
Bin	'1'	'1'	1086803	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXTB_PARITY_TRUE_GEN.TXTB_PORT_A_PARITY_CALCULATOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

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Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

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Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: