Hierarchy: CTU_CAN_FD_TB
TB_TOP_CTU_CAN_FD
DUT
RX_BUFFER_INST
RX_BUFFER_FSM_INST
Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_FSM_INST
Sub-instances:
Instance
Statement
Branch
Toggle
Expression
FSM state
Functional
Average
ASSERTIONS_BLOCK 100.0 % (1/1)
N.A.
100.0 % (8/8)
N.A.
N.A.
100.0 % (3/3)
100.0 % (12/12)
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Statement
Branch
Toggle
Expression
FSM state
Functional
Covered statements:
Signal assignment statement: 164: next_state <= curr_state; Count: 331324
Threshold: 1
Sequential statement: 166: case curr_state is Count: 331324
Threshold: 1
If statement: 172: if (store_metadata_f = '1') then Count: 106105
Threshold: 1
Signal assignment statement: 173: next_state <= s_rxb_store_frame_format; Count: 26358
Threshold: 1
Signal assignment statement: 175: next_state <= s_rxb_store_err_frame_format; Count: 317
Threshold: 1
If statement: 182: if (rec_abort_f = '1') then Count: 52716
Threshold: 1
If statement: 183: if (mr_mode_erfm = ERFM_ENABLED) then Count: 7
Threshold: 1
Signal assignment statement: 184: next_state <= s_rxb_store_err_frame_format; Count: 5
Threshold: 1
Signal assignment statement: 186: next_state <= s_rxb_idle; Count: 2
Threshold: 1
Signal assignment statement: 189: next_state <= s_rxb_store_identifier; Count: 52709
Threshold: 1
Signal assignment statement: 199: next_state <= s_rxb_skip_ts_low; Count: 26351
Threshold: 1
Signal assignment statement: 205: next_state <= s_rxb_skip_ts_high; Count: 26351
Threshold: 1
Signal assignment statement: 211: next_state <= s_rxb_store_data; Count: 26351
Threshold: 1
If statement: 219: if (rec_abort_f = '1') then Count: 52702
Threshold: 1
If statement: 220: if (mr_mode_erfm = ERFM_ENABLED) then Count: 13330
Threshold: 1
Signal assignment statement: 221: next_state <= s_rxb_store_err_frame_format; Count: 15
Threshold: 1
Signal assignment statement: 223: next_state <= s_rxb_idle; Count: 13315
Threshold: 1
Signal assignment statement: 227: next_state <= s_rxb_store_end_ts_low; Count: 13021
Threshold: 1
Signal assignment statement: 234: next_state <= s_rxb_store_end_ts_high; Count: 26042
Threshold: 1
Signal assignment statement: 240: next_state <= s_rxb_idle; Count: 13021
Threshold: 1
Signal assignment statement: 246: next_state <= s_rxb_store_err_identifier; Count: 674
Threshold: 1
Signal assignment statement: 252: next_state <= s_rxb_store_err_ts_low; Count: 337
Threshold: 1
Signal assignment statement: 258: next_state <= s_rxb_store_err_ts_high; Count: 337
Threshold: 1
Signal assignment statement: 264: next_state <= s_rxb_idle; Count: 337
Threshold: 1
Signal assignment statement: 275: write_raw_intent <= '0'; Count: 423334
Threshold: 1
Signal assignment statement: 276: select_ts_wptr <= '0'; Count: 423334
Threshold: 1
Signal assignment statement: 277: data_selector <= (others => '0'); Count: 423334
Threshold: 1
Signal assignment statement: 278: commit_intent <= '0'; Count: 423334
Threshold: 1
Signal assignment statement: 279: store_ts_wr_ptr <= '0'; Count: 423334
Threshold: 1
Signal assignment statement: 280: inc_ts_wr_ptr <= '0'; Count: 423334
Threshold: 1
Signal assignment statement: 281: reset_overrun_flag <= '0'; Count: 423334
Threshold: 1
Signal assignment statement: 282: rec_erf <= '0'; Count: 423334
Threshold: 1
Sequential statement: 284: case curr_state is Count: 423334
Threshold: 1
Signal assignment statement: 286: reset_overrun_flag <= '1'; Count: 77841
Threshold: 1
If statement: 289: if (rec_abort_f = '0') then Count: 26365
Threshold: 1
Signal assignment statement: 290: write_raw_intent <= '1'; Count: 26358
Threshold: 1
Signal assignment statement: 292: data_selector <= "00001"; Count: 26365
Threshold: 1
Signal assignment statement: 295: write_raw_intent <= '1'; Count: 26351
Threshold: 1
Signal assignment statement: 296: data_selector <= "00010"; Count: 26351
Threshold: 1
Signal assignment statement: 299: write_raw_intent <= '1'; Count: 26351
Threshold: 1
Signal assignment statement: 303: store_ts_wr_ptr <= '1'; Count: 26351
Threshold: 1
Signal assignment statement: 306: write_raw_intent <= '1'; Count: 26351
Threshold: 1
Signal assignment statement: 309: data_selector <= "00100"; Count: 212348
Threshold: 1
If statement: 311: if (store_data_f = '1') then Count: 212348
Threshold: 1
Signal assignment statement: 312: write_raw_intent <= '1'; Count: 86336
Threshold: 1
Signal assignment statement: 316: data_selector <= "01000"; Count: 13021
Threshold: 1
Signal assignment statement: 321: select_ts_wptr <= '1'; Count: 13021
Threshold: 1
Signal assignment statement: 325: inc_ts_wr_ptr <= '1'; Count: 13021
Threshold: 1
Signal assignment statement: 328: data_selector <= "10000"; Count: 13021
Threshold: 1
Signal assignment statement: 333: select_ts_wptr <= '1'; Count: 13021
Threshold: 1
Signal assignment statement: 335: commit_intent <= '1'; Count: 13021
Threshold: 1
Signal assignment statement: 338: write_raw_intent <= '1'; Count: 674
Threshold: 1
Signal assignment statement: 339: data_selector <= "00001"; Count: 674
Threshold: 1
Signal assignment statement: 340: rec_erf <= '1'; Count: 674
Threshold: 1
Signal assignment statement: 343: write_raw_intent <= '1'; Count: 337
Threshold: 1
Signal assignment statement: 344: data_selector <= "00010"; Count: 337
Threshold: 1
Signal assignment statement: 347: write_raw_intent <= '1'; Count: 337
Threshold: 1
Signal assignment statement: 348: data_selector <= "01000"; Count: 337
Threshold: 1
Signal assignment statement: 351: write_raw_intent <= '1'; Count: 337
Threshold: 1
Signal assignment statement: 352: data_selector <= "10000"; Count: 337
Threshold: 1
Signal assignment statement: 354: commit_intent <= '1'; Count: 337
Threshold: 1
If statement: 365: if (res_n = '0') then Count: 1055177083
Threshold: 1
Signal assignment statement: 366: curr_state <= s_rxb_idle; Count: 2418499
Threshold: 1
If statement: 368: if (rx_fsm_ce = '1') then Count: 526374300
Threshold: 1
Signal assignment statement: 369: curr_state <= next_state; Count: 185827
Threshold: 1
If statement: 375: rx_fsm_ce <= '1' when (next_state /= curr_state) else Count: 373261
Threshold: 1
Signal assignment statement: 375: rx_fsm_ce <= '1' when (next_state /= curr_state) else Count: 185834
Threshold: 1
Signal assignment statement: 376: '0'; Count: 187427
Threshold: 1
Covered branches:
"case" / "with" / "select" choice: 171: when s_rxb_idle => Choice of Count Threshold Bin s_rxb_idle106105 1
"if" / "when" / "else" condition: 172: if (store_metadata_f = '1') then Evaluated to Count Threshold Bin True 26358 1 Bin False 79747 1
"if" / "when" / "else" condition: 174: elsif (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1') then Evaluated to Count Threshold Bin True 317 1 Bin False 79430 1
"case" / "with" / "select" choice: 181: when s_rxb_store_frame_format => Choice of Count Threshold Bin s_rxb_store_frame_format52716 1
"if" / "when" / "else" condition: 182: if (rec_abort_f = '1') then Evaluated to Count Threshold Bin True 7 1 Bin False 52709 1
"if" / "when" / "else" condition: 183: if (mr_mode_erfm = ERFM_ENABLED) then Evaluated to Count Threshold Bin True 5 1 Bin False 2 1
"case" / "with" / "select" choice: 198: when s_rxb_store_identifier => Choice of Count Threshold Bin s_rxb_store_identifier26351 1
"case" / "with" / "select" choice: 204: when s_rxb_skip_ts_low => Choice of Count Threshold Bin s_rxb_skip_ts_low26351 1
"case" / "with" / "select" choice: 210: when s_rxb_skip_ts_high => Choice of Count Threshold Bin s_rxb_skip_ts_high26351 1
"case" / "with" / "select" choice: 218: when s_rxb_store_data => Choice of Count Threshold Bin s_rxb_store_data52702 1
"if" / "when" / "else" condition: 219: if (rec_abort_f = '1') then Evaluated to Count Threshold Bin True 13330 1 Bin False 39372 1
"if" / "when" / "else" condition: 220: if (mr_mode_erfm = ERFM_ENABLED) then Evaluated to Count Threshold Bin True 15 1 Bin False 13315 1
"if" / "when" / "else" condition: 226: elsif (rec_valid_f = '1') then Evaluated to Count Threshold Bin True 13021 1 Bin False 26351 1
"case" / "with" / "select" choice: 233: when s_rxb_store_end_ts_low => Choice of Count Threshold Bin s_rxb_store_end_ts_low26042 1
"case" / "with" / "select" choice: 239: when s_rxb_store_end_ts_high => Choice of Count Threshold Bin s_rxb_store_end_ts_high13021 1
"case" / "with" / "select" choice: 245: when s_rxb_store_err_frame_format => Choice of Count Threshold Bin s_rxb_store_err_frame_format674 1
"case" / "with" / "select" choice: 251: when s_rxb_store_err_identifier => Choice of Count Threshold Bin s_rxb_store_err_identifier337 1
"case" / "with" / "select" choice: 257: when s_rxb_store_err_ts_low => Choice of Count Threshold Bin s_rxb_store_err_ts_low337 1
"case" / "with" / "select" choice: 263: when s_rxb_store_err_ts_high => Choice of Count Threshold Bin s_rxb_store_err_ts_high337 1
"case" / "with" / "select" choice: 285: when s_rxb_idle => Choice of Count Threshold Bin s_rxb_idle77841 1
"case" / "with" / "select" choice: 288: when s_rxb_store_frame_format => Choice of Count Threshold Bin s_rxb_store_frame_format26365 1
"if" / "when" / "else" condition: 289: if (rec_abort_f = '0') then Evaluated to Count Threshold Bin True 26358 1 Bin False 7 1
"case" / "with" / "select" choice: 294: when s_rxb_store_identifier => Choice of Count Threshold Bin s_rxb_store_identifier26351 1
"case" / "with" / "select" choice: 298: when s_rxb_skip_ts_low => Choice of Count Threshold Bin s_rxb_skip_ts_low26351 1
"case" / "with" / "select" choice: 305: when s_rxb_skip_ts_high => Choice of Count Threshold Bin s_rxb_skip_ts_high26351 1
"case" / "with" / "select" choice: 308: when s_rxb_store_data => Choice of Count Threshold Bin s_rxb_store_data212348 1
"if" / "when" / "else" condition: 311: if (store_data_f = '1') then Evaluated to Count Threshold Bin True 86336 1 Bin False 126012 1
"case" / "with" / "select" choice: 315: when s_rxb_store_end_ts_low => Choice of Count Threshold Bin s_rxb_store_end_ts_low13021 1
"case" / "with" / "select" choice: 327: when s_rxb_store_end_ts_high => Choice of Count Threshold Bin s_rxb_store_end_ts_high13021 1
"case" / "with" / "select" choice: 337: when s_rxb_store_err_frame_format => Choice of Count Threshold Bin s_rxb_store_err_frame_format674 1
"case" / "with" / "select" choice: 342: when s_rxb_store_err_identifier => Choice of Count Threshold Bin s_rxb_store_err_identifier337 1
"case" / "with" / "select" choice: 346: when s_rxb_store_err_ts_low => Choice of Count Threshold Bin s_rxb_store_err_ts_low337 1
"case" / "with" / "select" choice: 350: when s_rxb_store_err_ts_high => Choice of Count Threshold Bin s_rxb_store_err_ts_high337 1
"if" / "when" / "else" condition: 365: if (res_n = '0') then Evaluated to Count Threshold Bin True 2418499 1 Bin False 1052758584 1
"if" / "when" / "else" condition: 367: elsif (rising_edge(clk_sys)) then Evaluated to Count Threshold Bin True 526374300 1 Bin False 526384284 1
"if" / "when" / "else" condition: 368: if (rx_fsm_ce = '1') then Evaluated to Count Threshold Bin True 185827 1 Bin False 526188473 1
"if" / "when" / "else" condition: 375: rx_fsm_ce <= '1' when (next_state /= curr_state) else Evaluated to Count Threshold Bin True 185834 1 Bin False 187427 1
Covered toggles:
Port: CLK_SYSFrom To Count Threshold Bin 0 1 527578869 1 Bin 1 0 527580460 1
Port: RES_NFrom To Count Threshold Bin 0 1 8082 1 Bin 1 0 8072 1
Port: MR_MODE_ERFMFrom To Count Threshold Bin 0 1 153 1 Bin 1 0 1753 1
Port: STORE_METADATA_FFrom To Count Threshold Bin 0 1 26358 1 Bin 1 0 27958 1
Port: STORE_DATA_FFrom To Count Threshold Bin 0 1 86336 1 Bin 1 0 87936 1
Port: REC_VALID_FFrom To Count Threshold Bin 0 1 13021 1 Bin 1 0 14621 1
Port: REC_ABORT_FFrom To Count Threshold Bin 0 1 30820 1 Bin 1 0 32420 1
Port: WRITE_RAW_INTENTFrom To Count Threshold Bin 0 1 113031 1 Bin 1 0 114631 1
Port: SELECT_TS_WPTRFrom To Count Threshold Bin 0 1 13021 1 Bin 1 0 14621 1
Port: COMMIT_INTENTFrom To Count Threshold Bin 0 1 13358 1 Bin 1 0 14958 1
Port: DATA_SELECTOR(4)From To Count Threshold Bin 0 1 13358 1 Bin 1 0 14958 1
Port: DATA_SELECTOR(3)From To Count Threshold Bin 0 1 13358 1 Bin 1 0 14958 1
Port: DATA_SELECTOR(2)From To Count Threshold Bin 0 1 26351 1 Bin 1 0 27951 1
Port: DATA_SELECTOR(1)From To Count Threshold Bin 0 1 26688 1 Bin 1 0 28288 1
Port: DATA_SELECTOR(0)From To Count Threshold Bin 0 1 26690 1 Bin 1 0 28290 1
Port: STORE_TS_WR_PTRFrom To Count Threshold Bin 0 1 26351 1 Bin 1 0 27951 1
Port: INC_TS_WR_PTRFrom To Count Threshold Bin 0 1 13021 1 Bin 1 0 14621 1
Port: REC_ERFFrom To Count Threshold Bin 0 1 337 1 Bin 1 0 1937 1
Port: RESET_OVERRUN_FLAGFrom To Count Threshold Bin 0 1 28275 1 Bin 1 0 26675 1
Signal: RX_FSM_CEFrom To Count Threshold Bin 0 1 185827 1 Bin 1 0 187427 1
Covered expressions:
"=" expression 172: if (store_metadata_f = '1') then Evaluated to Count Threshold Bin False 79747 1 Bin True 26358 1
"=" expression 174: elsif (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1') then Evaluated to Count Threshold Bin False 78920 1 Bin True 827 1
"=" expression 174: elsif (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1') then Evaluated to Count Threshold Bin False 48947 1 Bin True 30800 1
"and" expression 174: elsif (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1') then LHS RHS Count Threshold Bin False True 30483 1 Bin True False 510 1 Bin True True 317 1
"=" expression 182: if (rec_abort_f = '1') then Evaluated to Count Threshold Bin False 52709 1 Bin True 7 1
"=" expression 183: if (mr_mode_erfm = ERFM_ENABLED) then Evaluated to Count Threshold Bin False 2 1 Bin True 5 1
"=" expression 219: if (rec_abort_f = '1') then Evaluated to Count Threshold Bin False 39372 1 Bin True 13330 1
"=" expression 220: if (mr_mode_erfm = ERFM_ENABLED) then Evaluated to Count Threshold Bin False 13315 1 Bin True 15 1
"=" expression 226: elsif (rec_valid_f = '1') then Evaluated to Count Threshold Bin False 26351 1 Bin True 13021 1
"=" expression 289: if (rec_abort_f = '0') then Evaluated to Count Threshold Bin False 7 1 Bin True 26358 1
"=" expression 311: if (store_data_f = '1') then Evaluated to Count Threshold Bin False 126012 1 Bin True 86336 1
"=" expression 365: if (res_n = '0') then Evaluated to Count Threshold Bin False 1052758584 1 Bin True 2418499 1
"=" expression 368: if (rx_fsm_ce = '1') then Evaluated to Count Threshold Bin False 526188473 1 Bin True 185827 1
"/=" expression 375: rx_fsm_ce <= '1' when (next_state /= curr_state) else Evaluated to Count Threshold Bin False 187427 1 Bin True 185834 1
Covered FSM states:
"T_RX_BUF_STATE" FSM 151: signal curr_state : t_rx_buf_state; State Count Threshold Bin S_RXB_IDLE 28275 1 Bin S_RXB_STORE_FRAME_FORMAT 26358 1 Bin S_RXB_STORE_IDENTIFIER 26351 1 Bin S_RXB_SKIP_TS_LOW 26351 1 Bin S_RXB_SKIP_TS_HIGH 26351 1 Bin S_RXB_STORE_END_TS_LOW 13021 1 Bin S_RXB_STORE_END_TS_HIGH 13021 1 Bin S_RXB_STORE_DATA 26351 1 Bin S_RXB_STORE_ERR_FRAME_FORMAT 337 1 Bin S_RXB_STORE_ERR_IDENTIFIER 337 1 Bin S_RXB_STORE_ERR_TS_LOW 337 1 Bin S_RXB_STORE_ERR_TS_HIGH 337 1
"T_RX_BUF_STATE" FSM 152: signal next_state : t_rx_buf_state; State Count Threshold Bin S_RXB_IDLE 28275 1 Bin S_RXB_STORE_FRAME_FORMAT 26358 1 Bin S_RXB_STORE_IDENTIFIER 26358 1 Bin S_RXB_SKIP_TS_LOW 26351 1 Bin S_RXB_SKIP_TS_HIGH 26351 1 Bin S_RXB_STORE_END_TS_LOW 13021 1 Bin S_RXB_STORE_END_TS_HIGH 13021 1 Bin S_RXB_STORE_DATA 26351 1 Bin S_RXB_STORE_ERR_FRAME_FORMAT 337 1 Bin S_RXB_STORE_ERR_IDENTIFIER 337 1 Bin S_RXB_STORE_ERR_TS_LOW 337 1 Bin S_RXB_STORE_ERR_TS_HIGH 337 1
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: