NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ASSERTIONS_BLOCK	100.0 % (1/1)	N.A.	100.0 % (8/8)	N.A.	N.A.	100.0 % (3/3)	100.0 % (12/12)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_FSM_INST	100.0 % (68/68)	100.0 % (50/50)	100.0 % (40/40)	100.0 % (29/29)	100.0 % (24/24)	N.A.	100.0 % (211/211)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement	Branch	Toggle	Expression	FSM state	Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 164:

164: next_state <= curr_state;
Count: 332930
Threshold: 1

Sequential statement on lines 166 to 266:

166:        case curr_state is 
167: 
...
265: 
266:        end case;

Count: 332930
Threshold: 1

If statement on lines 172 to 176:

172:            if (store_metadata_f = '1') then 
173:                next_state <= s_rxb_store_frame_format; 
174:            elsif (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1') then 
175:                next_state <= s_rxb_store_err_frame_format; 
176:            end if;

Count: 107166
Threshold: 1

Signal assignment statement on line 173:

173: next_state <= s_rxb_store_frame_format;
Count: 26419
Threshold: 1

Signal assignment statement on line 175:

175: next_state <= s_rxb_store_err_frame_format;
Count: 317
Threshold: 1

If statement on lines 182 to 190:

182:            if (rec_abort_f = '1') then 
183:                if (mr_mode_erfm = ERFM_ENABLED) then 
...
189:                next_state <= s_rxb_store_identifier; 
190:            end if;

Count: 52838
Threshold: 1

If statement on lines 183 to 187:

183:                if (mr_mode_erfm = ERFM_ENABLED) then 
184:                    next_state <= s_rxb_store_err_frame_format; 
185:                else 
186:                    next_state <= s_rxb_idle; 
187:                end if;

Count: 8
Threshold: 1

Signal assignment statement on line 184:

184: next_state <= s_rxb_store_err_frame_format;
Count: 5
Threshold: 1

Signal assignment statement on line 186:

186: next_state <= s_rxb_idle;
Count: 3
Threshold: 1

Signal assignment statement on line 189:

189: next_state <= s_rxb_store_identifier;
Count: 52830
Threshold: 1

Signal assignment statement on line 199:

199: next_state <= s_rxb_skip_ts_low;
Count: 26411
Threshold: 1

Signal assignment statement on line 205:

205: next_state <= s_rxb_skip_ts_high;
Count: 26411
Threshold: 1

Signal assignment statement on line 211:

211: next_state <= s_rxb_store_data;
Count: 26411
Threshold: 1

If statement on lines 219 to 228:

219:            if (rec_abort_f = '1') then 
220:                if (mr_mode_erfm = ERFM_ENABLED) then 
...
227:                next_state <= s_rxb_store_end_ts_low; 
228:            end if;

Count: 52822
Threshold: 1

If statement on lines 220 to 224:

220:                if (mr_mode_erfm = ERFM_ENABLED) then 
221:                    next_state <= s_rxb_store_err_frame_format; 
222:                else 
223:                    next_state <= s_rxb_idle; 
224:                end if;

Count: 13349
Threshold: 1

Signal assignment statement on line 221:

221: next_state <= s_rxb_store_err_frame_format;
Count: 15
Threshold: 1

Signal assignment statement on line 223:

223: next_state <= s_rxb_idle;
Count: 13334
Threshold: 1

Signal assignment statement on line 227:

227: next_state <= s_rxb_store_end_ts_low;
Count: 13062
Threshold: 1

Signal assignment statement on line 234:

234: next_state <= s_rxb_store_end_ts_high;
Count: 26124
Threshold: 1

Signal assignment statement on line 240:

240: next_state <= s_rxb_idle;
Count: 13062
Threshold: 1

Signal assignment statement on line 246:

246: next_state <= s_rxb_store_err_identifier;
Count: 674
Threshold: 1

Signal assignment statement on line 252:

252: next_state <= s_rxb_store_err_ts_low;
Count: 337
Threshold: 1

Signal assignment statement on line 258:

258: next_state <= s_rxb_store_err_ts_high;
Count: 337
Threshold: 1

Signal assignment statement on line 264:

264: next_state <= s_rxb_idle;
Count: 337
Threshold: 1

Signal assignment statement on line 275:

275: write_raw_intent <= '0';
Count: 424259
Threshold: 1

Signal assignment statement on line 276:

276: select_ts_wptr <= '0';
Count: 424259
Threshold: 1

Signal assignment statement on line 277:

277: data_selector <= (others => '0');
Count: 424259
Threshold: 1

Signal assignment statement on line 278:

278: commit_intent <= '0';
Count: 424259
Threshold: 1

Signal assignment statement on line 279:

279: store_ts_wr_ptr <= '0';
Count: 424259
Threshold: 1

Signal assignment statement on line 280:

280: inc_ts_wr_ptr <= '0';
Count: 424259
Threshold: 1

Signal assignment statement on line 281:

281: reset_overrun_flag <= '0';
Count: 424259
Threshold: 1

Signal assignment statement on line 282:

282: rec_erf <= '0';
Count: 424259
Threshold: 1

Sequential statement on lines 284 to 355:

284:        case curr_state is 
285:        when s_rxb_idle => 
...
354:            commit_intent <= '1'; 
355:        end case;

Count: 424259
Threshold: 1

Signal assignment statement on line 286:

286: reset_overrun_flag <= '1';
Count: 78840
Threshold: 1

If statement on lines 289 to 291:

289:            if (rec_abort_f = '0') then 
290:                write_raw_intent <= '1'; 
291:            end if;

Count: 26427
Threshold: 1

Signal assignment statement on line 290:

290: write_raw_intent <= '1';
Count: 26419
Threshold: 1

Signal assignment statement on line 292:

292: data_selector <= "00001";
Count: 26427
Threshold: 1

Signal assignment statement on line 295:

295: write_raw_intent <= '1';
Count: 26411
Threshold: 1

Signal assignment statement on line 296:

296: data_selector <= "00010";
Count: 26411
Threshold: 1

Signal assignment statement on line 299:

299: write_raw_intent <= '1';
Count: 26411
Threshold: 1

Signal assignment statement on line 303:

303: store_ts_wr_ptr <= '1';
Count: 26411
Threshold: 1

Signal assignment statement on line 306:

306: write_raw_intent <= '1';
Count: 26411
Threshold: 1

Signal assignment statement on line 309:

309: data_selector <= "00100";
Count: 211950
Threshold: 1

If statement on lines 311 to 313:

311:            if (store_data_f = '1') then 
312:                write_raw_intent <= '1'; 
313:            end if;

Count: 211950
Threshold: 1

Signal assignment statement on line 312:

312: write_raw_intent <= '1';
Count: 86097
Threshold: 1

Signal assignment statement on line 316:

316: data_selector <= "01000";
Count: 13062
Threshold: 1

Signal assignment statement on line 321:

321: select_ts_wptr <= '1';
Count: 13062
Threshold: 1

Signal assignment statement on line 325:

325: inc_ts_wr_ptr <= '1';
Count: 13062
Threshold: 1

Signal assignment statement on line 328:

328: data_selector <= "10000";
Count: 13062
Threshold: 1

Signal assignment statement on line 333:

333: select_ts_wptr <= '1';
Count: 13062
Threshold: 1

Signal assignment statement on line 335:

335: commit_intent <= '1';
Count: 13062
Threshold: 1

Signal assignment statement on line 338:

338: write_raw_intent <= '1';
Count: 674
Threshold: 1

Signal assignment statement on line 339:

339: data_selector <= "00001";
Count: 674
Threshold: 1

Signal assignment statement on line 340:

340: rec_erf <= '1';
Count: 674
Threshold: 1

Signal assignment statement on line 343:

343: write_raw_intent <= '1';
Count: 337
Threshold: 1

Signal assignment statement on line 344:

344: data_selector <= "00010";
Count: 337
Threshold: 1

Signal assignment statement on line 347:

347: write_raw_intent <= '1';
Count: 337
Threshold: 1

Signal assignment statement on line 348:

348: data_selector <= "01000";
Count: 337
Threshold: 1

Signal assignment statement on line 351:

351: write_raw_intent <= '1';
Count: 337
Threshold: 1

Signal assignment statement on line 352:

352: data_selector <= "10000";
Count: 337
Threshold: 1

Signal assignment statement on line 354:

354: commit_intent <= '1';
Count: 337
Threshold: 1

If statement on lines 365 to 371:

365:        if (res_n = '0') then 
366:            curr_state <= s_rxb_idle; 
...
370:            end if; 
371:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 366:

366: curr_state <= s_rxb_idle;
Count: 2424883
Threshold: 1

If statement on lines 368 to 370:

368:            if (rx_fsm_ce = '1') then 
369:                curr_state <= next_state; 
370:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 369:

369: curr_state <= next_state;
Count: 186271
Threshold: 1

If statement on lines 375 to 376:

375:    rx_fsm_ce <= '1' when (next_state /= curr_state) else 
376:                 '0';

Count: 374151
Threshold: 1

Signal assignment statement on line 375:

375: rx_fsm_ce <= '1' when (next_state /= curr_state) else
Count: 186279
Threshold: 1

Signal assignment statement on line 376:

376: '0';
Count: 187872
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice on line 171:

171: when s_rxb_idle =>

	Choice of	Count	Threshold
Bin	`s_rxb_idle`	107166	1

"if" / "when" / "else" condition on line 172:

172: if (store_metadata_f = '1') then

	Evaluated to	Count	Threshold
Bin	True	26419	1
Bin	False	80747	1

"if" / "when" / "else" condition on line 174:

174: elsif (mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1') then

	Evaluated to	Count	Threshold
Bin	True	317	1
Bin	False	80430	1

"case" / "with" / "select" choice on line 181:

181: when s_rxb_store_frame_format =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_frame_format`	52838	1

"if" / "when" / "else" condition on line 182:

182: if (rec_abort_f = '1') then

	Evaluated to	Count	Threshold
Bin	True	8	1
Bin	False	52830	1

"if" / "when" / "else" condition on line 183:

183: if (mr_mode_erfm = ERFM_ENABLED) then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	3	1

"case" / "with" / "select" choice on line 198:

198: when s_rxb_store_identifier =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_identifier`	26411	1

"case" / "with" / "select" choice on line 204:

204: when s_rxb_skip_ts_low =>

	Choice of	Count	Threshold
Bin	`s_rxb_skip_ts_low`	26411	1

"case" / "with" / "select" choice on line 210:

210: when s_rxb_skip_ts_high =>

	Choice of	Count	Threshold
Bin	`s_rxb_skip_ts_high`	26411	1

"case" / "with" / "select" choice on line 218:

218: when s_rxb_store_data =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_data`	52822	1

"if" / "when" / "else" condition on line 219:

219: if (rec_abort_f = '1') then

	Evaluated to	Count	Threshold
Bin	True	13349	1
Bin	False	39473	1

"if" / "when" / "else" condition on line 220:

220: if (mr_mode_erfm = ERFM_ENABLED) then

	Evaluated to	Count	Threshold
Bin	True	15	1
Bin	False	13334	1

"if" / "when" / "else" condition on line 226:

226: elsif (rec_valid_f = '1') then

	Evaluated to	Count	Threshold
Bin	True	13062	1
Bin	False	26411	1

"case" / "with" / "select" choice on line 233:

233: when s_rxb_store_end_ts_low =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_end_ts_low`	26124	1

"case" / "with" / "select" choice on line 239:

239: when s_rxb_store_end_ts_high =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_end_ts_high`	13062	1

"case" / "with" / "select" choice on line 245:

245: when s_rxb_store_err_frame_format =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_frame_format`	674	1

"case" / "with" / "select" choice on line 251:

251: when s_rxb_store_err_identifier =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_identifier`	337	1

"case" / "with" / "select" choice on line 257:

257: when s_rxb_store_err_ts_low =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_ts_low`	337	1

"case" / "with" / "select" choice on line 263:

263: when s_rxb_store_err_ts_high =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_ts_high`	337	1

"case" / "with" / "select" choice on line 285:

285: when s_rxb_idle =>

	Choice of	Count	Threshold
Bin	`s_rxb_idle`	78840	1

"case" / "with" / "select" choice on line 288:

288: when s_rxb_store_frame_format =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_frame_format`	26427	1

"if" / "when" / "else" condition on line 289:

289: if (rec_abort_f = '0') then

	Evaluated to	Count	Threshold
Bin	True	26419	1
Bin	False	8	1

"case" / "with" / "select" choice on line 294:

294: when s_rxb_store_identifier =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_identifier`	26411	1

"case" / "with" / "select" choice on line 298:

298: when s_rxb_skip_ts_low =>

	Choice of	Count	Threshold
Bin	`s_rxb_skip_ts_low`	26411	1

"case" / "with" / "select" choice on line 305:

305: when s_rxb_skip_ts_high =>

	Choice of	Count	Threshold
Bin	`s_rxb_skip_ts_high`	26411	1

"case" / "with" / "select" choice on line 308:

308: when s_rxb_store_data =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_data`	211950	1

"if" / "when" / "else" condition on line 311:

311: if (store_data_f = '1') then

	Evaluated to	Count	Threshold
Bin	True	86097	1
Bin	False	125853	1

"case" / "with" / "select" choice on line 315:

315: when s_rxb_store_end_ts_low =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_end_ts_low`	13062	1

"case" / "with" / "select" choice on line 327:

327: when s_rxb_store_end_ts_high =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_end_ts_high`	13062	1

"case" / "with" / "select" choice on line 337:

337: when s_rxb_store_err_frame_format =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_frame_format`	674	1

"case" / "with" / "select" choice on line 342:

342: when s_rxb_store_err_identifier =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_identifier`	337	1

"case" / "with" / "select" choice on line 346:

346: when s_rxb_store_err_ts_low =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_ts_low`	337	1

"case" / "with" / "select" choice on line 350:

350: when s_rxb_store_err_ts_high =>

	Choice of	Count	Threshold
Bin	`s_rxb_store_err_ts_high`	337	1

"if" / "when" / "else" condition on line 365:

365: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 367:

367: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 368:

368: if (rx_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	186271	1
Bin	False	543605407	1

"if" / "when" / "else" condition on line 375:

375: rx_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	True	186279	1
Bin	False	187872	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ERFM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_METADATA_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

STORE_DATA_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_VALID_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_ABORT_F

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

WRITE_RAW_INTENT

	From	To	Count	Threshold
Bin	0	1	112853	1
Bin	1	0	114454	1

Port:

SELECT_TS_WPTR

	From	To	Count	Threshold
Bin	0	1	13062	1
Bin	1	0	14663	1

Port:

COMMIT_INTENT

	From	To	Count	Threshold
Bin	0	1	13399	1
Bin	1	0	15000	1

Port:

DATA_SELECTOR

	Element	From	To	Count	Threshold
Bin	(4)	0	1	13399	1
Bin	(4)	1	0	15000	1
Bin	(3)	0	1	13399	1
Bin	(3)	1	0	15000	1
Bin	(2)	0	1	26411	1
Bin	(2)	1	0	28012	1
Bin	(1)	0	1	26748	1
Bin	(1)	1	0	28349	1
Bin	(0)	0	1	26751	1
Bin	(0)	1	0	28352	1

Port:

STORE_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	26411	1
Bin	1	0	28012	1

Port:

INC_TS_WR_PTR

	From	To	Count	Threshold
Bin	0	1	13062	1
Bin	1	0	14663	1

Port:

REC_ERF

	From	To	Count	Threshold
Bin	0	1	337	1
Bin	1	0	1938	1

Port:

RESET_OVERRUN_FLAG

	From	To	Count	Threshold
Bin	0	1	28337	1
Bin	1	0	26736	1

Signal:

RX_FSM_CE

	From	To	Count	Threshold
Bin	0	1	186271	1
Bin	1	0	187872	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 172:

store_metadata_f = '1'

	Evaluated to	Count	Threshold
Bin	False	80747	1
Bin	True	26419	1

"and" expression on line 174:

 mr_mode_erfm = ERFM_ENABLED and rec_abort_f = '1' 
 <-----------LHS----------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	30961	1
Bin	True	False	510	1
Bin	True	True	317	1

"=" expression on line 174:

mr_mode_erfm = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	79920	1
Bin	True	827	1

"=" expression on line 174:

rec_abort_f = '1'

	Evaluated to	Count	Threshold
Bin	False	49469	1
Bin	True	31278	1

"=" expression on line 182:

rec_abort_f = '1'

	Evaluated to	Count	Threshold
Bin	False	52830	1
Bin	True	8	1

"=" expression on line 183:

mr_mode_erfm = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	3	1
Bin	True	5	1

"=" expression on line 219:

rec_abort_f = '1'

	Evaluated to	Count	Threshold
Bin	False	39473	1
Bin	True	13349	1

"=" expression on line 220:

mr_mode_erfm = ERFM_ENABLED

	Evaluated to	Count	Threshold
Bin	False	13334	1
Bin	True	15	1

"=" expression on line 226:

rec_valid_f = '1'

	Evaluated to	Count	Threshold
Bin	False	26411	1
Bin	True	13062	1

"=" expression on line 289:

rec_abort_f = '0'

	Evaluated to	Count	Threshold
Bin	False	8	1
Bin	True	26419	1

"=" expression on line 311:

store_data_f = '1'

	Evaluated to	Count	Threshold
Bin	False	125853	1
Bin	True	86097	1

"=" expression on line 365:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 368:

rx_fsm_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543605407	1
Bin	True	186271	1

"/=" expression on line 375:

next_state /= curr_state

	Evaluated to	Count	Threshold
Bin	False	187872	1
Bin	True	186279	1

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

"T_RX_BUF_STATE" FSM on line 151:

151: signal curr_state : t_rx_buf_state;

	State	Count	Threshold
Bin	S_RXB_IDLE	28337	1
Bin	S_RXB_STORE_FRAME_FORMAT	26419	1
Bin	S_RXB_STORE_IDENTIFIER	26411	1
Bin	S_RXB_SKIP_TS_LOW	26411	1
Bin	S_RXB_SKIP_TS_HIGH	26411	1
Bin	S_RXB_STORE_END_TS_LOW	13062	1
Bin	S_RXB_STORE_END_TS_HIGH	13062	1
Bin	S_RXB_STORE_DATA	26411	1
Bin	S_RXB_STORE_ERR_FRAME_FORMAT	337	1
Bin	S_RXB_STORE_ERR_IDENTIFIER	337	1
Bin	S_RXB_STORE_ERR_TS_LOW	337	1
Bin	S_RXB_STORE_ERR_TS_HIGH	337	1

"T_RX_BUF_STATE" FSM on line 152:

152: signal next_state : t_rx_buf_state;

	State	Count	Threshold
Bin	S_RXB_IDLE	28337	1
Bin	S_RXB_STORE_FRAME_FORMAT	26419	1
Bin	S_RXB_STORE_IDENTIFIER	26419	1
Bin	S_RXB_SKIP_TS_LOW	26411	1
Bin	S_RXB_SKIP_TS_HIGH	26411	1
Bin	S_RXB_STORE_END_TS_LOW	13062	1
Bin	S_RXB_STORE_END_TS_HIGH	13062	1
Bin	S_RXB_STORE_DATA	26411	1
Bin	S_RXB_STORE_ERR_FRAME_FORMAT	337	1
Bin	S_RXB_STORE_ERR_IDENTIFIER	337	1
Bin	S_RXB_STORE_ERR_TS_LOW	337	1
Bin	S_RXB_STORE_ERR_TS_HIGH	337	1