NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_SEGMENT_METER_NBT_INST	100.0 % (66/66)	100.0 % (48/48)	100.0 % (96/96)	100.0 % (161/161)	N.A.	N.A.	100.0 % (371/371)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

273:        if (a > b) then 
274:            return a; 
275:        else 
276:            return b; 
277:        end if;

Count: 16000
Threshold: 1

Sequential statement:

274: return a;
Count: 12800
Threshold: 1

Sequential statement:

276: return b;
Count: 3200
Threshold: 1

If statement:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 
354:                 '0';

Count: 66380730
Threshold: 1

Signal assignment statement:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

Count: 33252389
Threshold: 1

Signal assignment statement:

354: '0';
Count: 33128341
Threshold: 1

If statement:

356:    basic_segm_length <= 
357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
358:        resize(unsigned(tseg_2), C_BS_WIDTH);

Count: 66269543
Threshold: 1

Signal assignment statement:

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else
Count: 33126454
Threshold: 1

Signal assignment statement:

358: resize(unsigned(tseg_2), C_BS_WIDTH);
Count: 33143089
Threshold: 1

If statement:

360:    segm_extension <= 
361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 
363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
364:        resize(unsigned(segm_counter), C_EXT_WIDTH);

Count: 327944342
Threshold: 1

Signal assignment statement:

361: to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or
Count: 104441
Threshold: 1

Signal assignment statement:

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else
Count: 198013909
Threshold: 1

Signal assignment statement:

364: resize(unsigned(segm_counter), C_EXT_WIDTH);
Count: 129825992
Threshold: 1

Signal assignment statement:

366:    segm_ext_add <= resize(basic_segm_length, C_EXP_WIDTH) + 
367:                    resize(segm_extension, C_EXP_WIDTH);

Count: 204990415
Threshold: 1

Signal assignment statement:

369:    segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) - 
370:                    resize(segm_extension, C_EXP_WIDTH);

Count: 204990415
Threshold: 1

If statement:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 
374:                                     else 
375:                        segm_ext_add;

Count: 227191995
Threshold: 1

Signal assignment statement:

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or
Count: 97181935
Threshold: 1

Signal assignment statement:

375: segm_ext_add;
Count: 130010060
Threshold: 1

If statement:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 
387:                                 else 
388:                             '0';

Count: 44303976
Threshold: 1

Signal assignment statement:

384: use_basic_segm_length <= '1' when (start_edge = '1') or
Count: 22085587
Threshold: 1

Signal assignment statement:

388: '0';
Count: 22218389
Threshold: 1

If statement:

395:    exp_seg_length_d <= 
396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
397:                                               else 
398:        resize(sync_segm_length, C_EXP_WIDTH);

Count: 333459485
Threshold: 1

Signal assignment statement:

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')
Count: 146069696
Threshold: 1

Signal assignment statement:

398: resize(sync_segm_length, C_EXP_WIDTH);
Count: 187389789
Threshold: 1

If statement:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 
402:                             else 
403:                         '0';

Count: 45877697
Threshold: 1

Signal assignment statement:

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or
Count: 23445037
Threshold: 1

Signal assignment statement:

403: '0';
Count: 22432660
Threshold: 1

If statement:

407:        if (res_n = '0') then 
408:            exp_seg_length_q <= (others => '1'); 
...
412:            end if; 
413:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

408: exp_seg_length_q <= (others => '1');
Count: 2418499
Threshold: 1

If statement:

410:            if (exp_seg_length_ce = '1') then 
411:                exp_seg_length_q <= exp_seg_length_d; 
412:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

411: exp_seg_length_q <= exp_seg_length_d;
Count: 22820611
Threshold: 1

Signal assignment statement:

425:    neg_phase_err  <= resize(unsigned(tseg_2), C_E_WIDTH) - 
426:                      resize(unsigned(segm_counter), C_E_WIDTH);

Count: 305661269
Threshold: 1

If statement:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
429:                 resize(unsigned(segm_counter), C_E_WIDTH);

Count: 611316423
Threshold: 1

Signal assignment statement:

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else
Count: 190531693
Threshold: 1

Signal assignment statement:

429: resize(unsigned(segm_counter), C_E_WIDTH);
Count: 420784730
Threshold: 1

If statement:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
433:                            else 
434:                        '0';

Count: 316685330
Threshold: 1

Signal assignment statement:

431: phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) >
Count: 194457672
Threshold: 1

Signal assignment statement:

434: '0';
Count: 122227658
Threshold: 1

If statement:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
438:                            else 
439:                        '0';

Count: 316685330
Threshold: 1

Signal assignment statement:

436: phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
Count: 18071126
Threshold: 1

Signal assignment statement:

439: '0';
Count: 298614204
Threshold: 1

If statement:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 
444:                                else 
445:                            '0';

Count: 316685330
Threshold: 1

Signal assignment statement:

441: phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
Count: 13547484
Threshold: 1

Signal assignment statement:

445: '0';
Count: 303137846
Threshold: 1

If statement:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
448:                   '0';

Count: 10045
Threshold: 1

Signal assignment statement:

447: sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else
Count: 8246
Threshold: 1

Signal assignment statement:

448: '0';
Count: 1799
Threshold: 1

If statement:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 
460:                              else 
461:                          '0';

Count: 57815750
Threshold: 1

Signal assignment statement:

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and
Count: 13179
Threshold: 1

Signal assignment statement:

461: '0';
Count: 57802571
Threshold: 1

If statement:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
469:                                     else 
470:                                 '0';

Count: 27124483
Threshold: 1

Signal assignment statement:

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')
Count: 12855
Threshold: 1

Signal assignment statement:

470: '0';
Count: 27111628
Threshold: 1

If statement:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 
477:                             else 
478:                         '0';

Count: 327777715
Threshold: 1

Signal assignment statement:

475: exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >=
Count: 24688304
Threshold: 1

Signal assignment statement:

478: '0';
Count: 303089411
Threshold: 1

If statement:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 
488:                                    else 
489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
490:                                    else 
491:                                '0';

Count: 45634330
Threshold: 1

Signal assignment statement:

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and
Count: 619987
Threshold: 1

Signal assignment statement:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

Count: 6322207
Threshold: 1

Signal assignment statement:

491: '0';
Count: 38692136
Threshold: 1

If statement:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
497:                                   else 
498:                               '0';

Count: 44050316
Threshold: 1

Signal assignment statement:

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')
Count: 15634412
Threshold: 1

Signal assignment statement:

498: '0';
Count: 28415904
Threshold: 1

If statement:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
509:                         else 
510:                     '0';

Count: 37738026
Threshold: 1

Signal assignment statement:

507: exit_segm_req <= '1' when (exit_ph2_immediate = '1') or
Count: 21973257
Threshold: 1

Signal assignment statement:

510: '0';
Count: 15764769
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

273: if (a > b) then

	Evaluated to	Count	Threshold
Bin	True	12800	1
Bin	False	3200	1

"if" / "when" / "else" condition:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	True	33252389	1
Bin	False	33128341	1

"if" / "when" / "else" condition:

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	True	33126454	1
Bin	False	33143089	1

"if" / "when" / "else" condition:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	True	104441	1
Bin	False	327839901	1

"if" / "when" / "else" condition:

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else

	Evaluated to	Count	Threshold
Bin	True	198013909	1
Bin	False	129825992	1

"if" / "when" / "else" condition:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1')

	Evaluated to	Count	Threshold
Bin	True	97181935	1
Bin	False	130010060	1

"if" / "when" / "else" condition:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	Evaluated to	Count	Threshold
Bin	True	22085587	1
Bin	False	22218389	1

"if" / "when" / "else" condition:

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')

	Evaluated to	Count	Threshold
Bin	True	146069696	1
Bin	False	187389789	1

"if" / "when" / "else" condition:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	True	23445037	1
Bin	False	22432660	1

"if" / "when" / "else" condition:

407: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

409: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

410: if (exp_seg_length_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	22820611	1
Bin	False	503553689	1

"if" / "when" / "else" condition:

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	True	190531693	1
Bin	False	420784730	1

"if" / "when" / "else" condition:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	194457672	1
Bin	False	122227658	1

"if" / "when" / "else" condition:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	18071126	1
Bin	False	298614204	1

"if" / "when" / "else" condition:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH)))

	Evaluated to	Count	Threshold
Bin	True	13547484	1
Bin	False	303137846	1

"if" / "when" / "else" condition:

447: sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else

	Evaluated to	Count	Threshold
Bin	True	8246	1
Bin	False	1799	1

"if" / "when" / "else" condition:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	13179	1
Bin	False	57802571	1

"if" / "when" / "else" condition:

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	True	12855	1
Bin	False	27111628	1

"if" / "when" / "else" condition:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	24688304	1
Bin	False	303089411	1

"if" / "when" / "else" condition:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1')

	Evaluated to	Count	Threshold
Bin	True	619987	1
Bin	False	45014343	1

"if" / "when" / "else" condition:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	True	6322207	1
Bin	False	38692136	1

"if" / "when" / "else" condition:

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	True	15634412	1
Bin	False	28415904	1

"if" / "when" / "else" condition:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	True	21973257	1
Bin	False	15764769	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

RESYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	795345	1
Bin	1	0	796945	1

Port:

IS_TSEG1

	From	To	Count	Threshold
Bin	0	1	11041544	1
Bin	1	0	11041536	1

Port:

IS_TSEG2

	From	To	Count	Threshold
Bin	0	1	11035219	1
Bin	1	0	11036818	1

Port:

TSEG_1(7)

	From	To	Count	Threshold
Bin	0	1	456	1
Bin	1	0	2054	1

Port:

TSEG_1(6)

	From	To	Count	Threshold
Bin	0	1	1689	1
Bin	1	0	3289	1

Port:

TSEG_1(5)

	From	To	Count	Threshold
Bin	0	1	806	1
Bin	1	0	2404	1

Port:

TSEG_1(4)

	From	To	Count	Threshold
Bin	0	1	935	1
Bin	1	0	2533	1

Port:

TSEG_1(3)

	From	To	Count	Threshold
Bin	0	1	5981	1
Bin	1	0	4382	1

Port:

TSEG_1(2)

	From	To	Count	Threshold
Bin	0	1	4192	1
Bin	1	0	5784	1

Port:

TSEG_1(1)

	From	To	Count	Threshold
Bin	0	1	1067	1
Bin	1	0	2664	1

Port:

TSEG_1(0)

	From	To	Count	Threshold
Bin	0	1	3759	1
Bin	1	0	2159	1

Port:

TSEG_2(5)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	1802	1

Port:

TSEG_2(4)

	From	To	Count	Threshold
Bin	0	1	347	1
Bin	1	0	1944	1

Port:

TSEG_2(3)

	From	To	Count	Threshold
Bin	0	1	314	1
Bin	1	0	1912	1

Port:

TSEG_2(2)

	From	To	Count	Threshold
Bin	0	1	3872	1
Bin	1	0	2274	1

Port:

TSEG_2(1)

	From	To	Count	Threshold
Bin	0	1	3411	1
Bin	1	0	5003	1

Port:

TSEG_2(0)

	From	To	Count	Threshold
Bin	0	1	2161	1
Bin	1	0	561	1

Port:

SJW(4)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	1802	1

Port:

SJW(3)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	1866	1

Port:

SJW(2)

	From	To	Count	Threshold
Bin	0	1	966	1
Bin	1	0	2563	1

Port:

SJW(1)

	From	To	Count	Threshold
Bin	0	1	2625	1
Bin	1	0	1032	1

Port:

SJW(0)

	From	To	Count	Threshold
Bin	0	1	3116	1
Bin	1	0	4713	1

Port:

START_EDGE

	From	To	Count	Threshold
Bin	0	1	6481	1
Bin	1	0	8081	1

Port:

SEGM_COUNTER(7)

	From	To	Count	Threshold
Bin	0	1	539581	1
Bin	1	0	541181	1

Port:

SEGM_COUNTER(6)

	From	To	Count	Threshold
Bin	0	1	891264	1
Bin	1	0	892863	1

Port:

SEGM_COUNTER(5)

	From	To	Count	Threshold
Bin	0	1	3071222	1
Bin	1	0	3072822	1

Port:

SEGM_COUNTER(4)

	From	To	Count	Threshold
Bin	0	1	6644766	1
Bin	1	0	6646365	1

Port:

SEGM_COUNTER(3)

	From	To	Count	Threshold
Bin	0	1	14781650	1
Bin	1	0	14783248	1

Port:

SEGM_COUNTER(2)

	From	To	Count	Threshold
Bin	0	1	36114069	1
Bin	1	0	36115669	1

Port:

SEGM_COUNTER(1)

	From	To	Count	Threshold
Bin	0	1	75947170	1
Bin	1	0	75948767	1

Port:

SEGM_COUNTER(0)

	From	To	Count	Threshold
Bin	0	1	145561048	1
Bin	1	0	145562645	1

Port:

SEGM_END

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Port:

H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	55365	1
Bin	1	0	56965	1

Port:

EXIT_SEGM_REQ

	From	To	Count	Threshold
Bin	0	1	15761570	1
Bin	1	0	15763169	1

Signal:

SEL_TSEG1

	From	To	Count	Threshold
Bin	0	1	33122794	1
Bin	1	0	33124386	1

Signal:

EXP_SEG_LENGTH_CE

	From	To	Count	Threshold
Bin	0	1	22427860	1
Bin	1	0	22429460	1

Signal:

PHASE_ERR_MT_SJW

	From	To	Count	Threshold
Bin	0	1	11077778	1
Bin	1	0	11079371	1

Signal:

PHASE_ERR_EQ_SJW

	From	To	Count	Threshold
Bin	0	1	18071126	1
Bin	1	0	18072725	1

Signal:

EXIT_PH2_IMMEDIATE

	From	To	Count	Threshold
Bin	0	1	13166	1
Bin	1	0	14766	1

Signal:

EXIT_SEGM_REGULAR

	From	To	Count	Threshold
Bin	0	1	15760750	1
Bin	1	0	15762349	1

Signal:

EXIT_SEGM_REGULAR_TSEG1

	From	To	Count	Threshold
Bin	0	1	6322205	1
Bin	1	0	6323805	1

Signal:

EXIT_SEGM_REGULAR_TSEG2

	From	To	Count	Threshold
Bin	0	1	15634412	1
Bin	1	0	15636011	1

Signal:

SJW_MT_ZERO

	From	To	Count	Threshold
Bin	0	1	1792	1
Bin	1	0	1799	1

Signal:

USE_BASIC_SEGM_LENGTH

	From	To	Count	Threshold
Bin	0	1	22085587	1
Bin	1	0	22087187	1

Signal:

PHASE_ERR_SJW_BY_ONE

	From	To	Count	Threshold
Bin	0	1	13547484	1
Bin	1	0	13549080	1

Signal:

SHORTEN_TSEG1_AFTER_TSEG2

	From	To	Count	Threshold
Bin	0	1	12855	1
Bin	1	0	14455	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

">" expression

273: if (a > b) then

	Evaluated to	Count	Threshold
Bin	False	3200	1
Bin	True	12800	1

"=" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	66301214	1
Bin	True	79516	1

"=" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	66374249	1
Bin	True	6481	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
                               <------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	66294733	1
Bin	False	True	6481	1
Bin	True	False	79516	1

"=" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	66357994	1
Bin	True	22736	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
                               <----------------LHS----------------->    <-------------RHS------------->

	LHS	RHS	Count	Threshold
Bin	False	False	66271997	1
Bin	False	True	22736	1
Bin	True	False	85997	1

"=" expression

352: (segm_end = '1' and is_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	22202068	1
Bin	True	44178662	1

"=" expression

352: (segm_end = '1' and is_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	33261200	1
Bin	True	33119530	1

"and" expression

352:                          (segm_end = '1' and is_tseg2 = '1') or 
                               <----LHS----->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	11049292	1
Bin	True	False	22108424	1
Bin	True	True	22070238	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or

	LHS	RHS	Count	Threshold
Bin	False	False	44218739	1
Bin	False	True	22053258	1
Bin	True	False	91753	1

"=" expression

353: (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	False	44181862	1
Bin	True	22198868	1

"=" expression

353: (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	False	33129912	1
Bin	True	33250818	1

"and" expression

353:                          (segm_end = '0' and is_tseg1 = '1') else 
                               <----LHS----->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	22109314	1
Bin	True	False	11057364	1
Bin	True	True	11141504	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else

	LHS	RHS	Count	Threshold
Bin	False	False	33128341	1
Bin	False	True	11090398	1
Bin	True	False	22110885	1

"=" expression

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	False	33143089	1
Bin	True	33126454	1

"=" expression

361: to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	327862006	1
Bin	True	82336	1

"=" expression

362:                                                 shorten_tseg1_after_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	False	327922237	1
Bin	True	22105	1

"or" expression

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else

	LHS	RHS	Count	Threshold
Bin	False	False	327839901	1
Bin	False	True	22105	1
Bin	True	False	82336	1

"=" expression

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else

	Evaluated to	Count	Threshold
Bin	False	129825992	1
Bin	True	198013909	1

"=" expression

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	130123408	1
Bin	True	97068587	1

"=" expression

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	227065445	1
Bin	True	126550	1

"or" expression

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
                                               <----LHS----->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	130019596	1
Bin	False	True	103812	1
Bin	True	False	97045849	1

"=" expression

373: exit_ph2_immediate = '1')

	Evaluated to	Count	Threshold
Bin	False	227147012	1
Bin	True	44983	1

"or" expression

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	130010060	1
Bin	False	True	9536	1
Bin	True	False	97136952	1

"=" expression

384: use_basic_segm_length <= '1' when (start_edge = '1') or

	Evaluated to	Count	Threshold
Bin	False	44297495	1
Bin	True	6481	1

"=" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and

	Evaluated to	Count	Threshold
Bin	False	22194706	1
Bin	True	22109270	1

"=" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and

	Evaluated to	Count	Threshold
Bin	False	75219	1
Bin	True	44228757	1

"and" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and 
                                           <----LHS----->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	22140335	1
Bin	True	False	20848	1
Bin	True	True	22088422	1

"=" expression

386: shorten_tseg1_after_tseg2 = '0')

	Evaluated to	Count	Threshold
Bin	False	15030	1
Bin	True	44288946	1

"and" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	LHS	RHS	Count	Threshold
Bin	False	True	22209840	1
Bin	True	False	9316	1
Bin	True	True	22079106	1

"or" expression

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	LHS	RHS	Count	Threshold
Bin	False	False	22218389	1
Bin	False	True	22079106	1
Bin	True	False	6481	1

"=" expression

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')

	Evaluated to	Count	Threshold
Bin	False	187389789	1
Bin	True	146069696	1

"=" expression

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	23217527	1
Bin	True	22660170	1

"=" expression

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	44658396	1
Bin	True	1219301	1

"or" expression

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
                                       <----LHS----->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	22490312	1
Bin	False	True	727215	1
Bin	True	False	22168084	1

"=" expression

401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	False	45805678	1
Bin	True	72019	1

"or" expression

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	22439141	1
Bin	False	True	51171	1
Bin	True	False	23366537	1

"=" expression

401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	False	45871216	1
Bin	True	6481	1

"or" expression

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	22432660	1
Bin	False	True	6481	1
Bin	True	False	23438556	1

"=" expression

407: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

410: if (exp_seg_length_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	503553689	1
Bin	True	22820611	1

"=" expression

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	False	420784730	1
Bin	True	190531693	1

"=" expression

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and

	Evaluated to	Count	Threshold
Bin	False	34648251	1
Bin	True	23167499	1

"=" expression

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and

	Evaluated to	Count	Threshold
Bin	False	38869446	1
Bin	True	18946304	1

"or" expression

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
                                         <--------LHS--------->    <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	15701947	1
Bin	False	True	18946304	1
Bin	True	False	23167499	1

"=" expression

459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	28499559	1
Bin	True	29316191	1

"and" expression

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	9598580	1
Bin	True	False	22396192	1
Bin	True	True	19717611	1

"=" expression

459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	57020305	1
Bin	True	795445	1

"and" expression

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	782266	1
Bin	True	False	19704432	1
Bin	True	True	13179	1

"=" expression

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	False	27111317	1
Bin	True	13166	1

"=" expression

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	False	13549706	1
Bin	True	13574777	1

"and" expression

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
                                               <---------LHS---------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	13561922	1
Bin	True	False	311	1
Bin	True	True	12855	1

"=" expression

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and

	Evaluated to	Count	Threshold
Bin	False	26705678	1
Bin	True	18928652	1

"=" expression

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and

	Evaluated to	Count	Threshold
Bin	False	44838985	1
Bin	True	795345	1

"and" expression

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
                                              <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	20407	1
Bin	True	False	18153714	1
Bin	True	True	774938	1

"=" expression

487: sjw_mt_zero = '1')

	Evaluated to	Count	Threshold
Bin	False	6145741	1
Bin	True	39488589	1

"and" expression

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	38868602	1
Bin	True	False	154951	1
Bin	True	True	619987	1

"=" expression

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	26705678	1
Bin	True	18308665	1

"=" expression

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	23041883	1
Bin	True	21972460	1

"and" expression

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
                                              <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	15650253	1
Bin	True	False	11986458	1
Bin	True	True	6322207	1

"=" expression

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	17380098	1
Bin	True	26670218	1

"=" expression

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	22093620	1
Bin	True	21956696	1

"and" expression

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
                                             <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	6322284	1
Bin	True	False	11035806	1
Bin	True	True	15634412	1

"=" expression

507: exit_segm_req <= '1' when (exit_ph2_immediate = '1') or

	Evaluated to	Count	Threshold
Bin	False	37724860	1
Bin	True	13166	1

"=" expression

508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	False	31415821	1
Bin	True	6322205	1

"=" expression

508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	False	22087870	1
Bin	True	15650156	1

"or" expression

508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
                                   <------------LHS------------>    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	False	15765665	1
Bin	False	True	15650156	1
Bin	True	False	6322205	1

"or" expression

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	15764769	1
Bin	False	True	21960091	1
Bin	True	False	896	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_SEGMENT_METER_NBT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd

Sub-instances:

Current Instance:

Details:

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Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition: