NVC code coverage report

If statement on lines 273 to 277:

273:        if (a > b) then 
274:            return a; 
275:        else 
276:            return b; 
277:        end if; 
Count: 8005
Threshold: 1

---

Sequential statement on line 274:

274:            return a; 
Count: 6404
Threshold: 1

---

Sequential statement on line 276:

276:            return b; 
Count: 1601
Threshold: 1

---

If statement on lines 351 to 354:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 
354:                 '0'; 
Count: 68466029
Threshold: 1

---

Signal assignment statement on line 351:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
Count: 34296120
Threshold: 1

---

Signal assignment statement on line 354:

354:                 '0'; 
Count: 34169909
Threshold: 1

---

If statement on lines 356 to 358:

356:    basic_segm_length <= 
357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
358:        resize(unsigned(tseg_2), C_BS_WIDTH); 
Count: 68352622
Threshold: 1

---

Signal assignment statement on line 357:

357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
Count: 34167973
Threshold: 1

---

Signal assignment statement on line 358:

358:        resize(unsigned(tseg_2), C_BS_WIDTH); 
Count: 34184649
Threshold: 1

---

If statement on lines 360 to 364:

360:    segm_extension <= 
361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 
363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
364:        resize(unsigned(segm_counter), C_EXT_WIDTH); 
Count: 340583847
Threshold: 1

---

Signal assignment statement on line 361:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
Count: 105893
Threshold: 1

---

Signal assignment statement on line 363:

363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
Count: 205528635
Threshold: 1

---

Signal assignment statement on line 364:

364:        resize(unsigned(segm_counter), C_EXT_WIDTH); 
Count: 134949319
Threshold: 1

---

Signal assignment statement on lines 366 to 367:

366:    segm_ext_add <= resize(basic_segm_length, C_EXP_WIDTH) + 
367:                    resize(segm_extension, C_EXP_WIDTH); 
Count: 212545599
Threshold: 1

---

Signal assignment statement on lines 369 to 370:

369:    segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) - 
370:                    resize(segm_extension, C_EXP_WIDTH); 
Count: 212545599
Threshold: 1

---

If statement on lines 372 to 375:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 
374:                                     else 
375:                        segm_ext_add; 
Count: 235443402
Threshold: 1

---

Signal assignment statement on line 372:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
Count: 100809610
Threshold: 1

---

Signal assignment statement on line 375:

375:                        segm_ext_add; 
Count: 134633792
Threshold: 1

---

If statement on lines 384 to 388:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 
387:                                 else 
388:                             '0'; 
Count: 45695292
Threshold: 1

---

Signal assignment statement on line 384:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
Count: 22779886
Threshold: 1

---

Signal assignment statement on line 388:

388:                             '0'; 
Count: 22915406
Threshold: 1

---

If statement on lines 395 to 398:

395:    exp_seg_length_d <= 
396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
397:                                               else 
398:        resize(sync_segm_length, C_EXP_WIDTH); 
Count: 345136946
Threshold: 1

---

Signal assignment statement on line 396:

396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
Count: 150780305
Threshold: 1

---

Signal assignment statement on line 398:

398:        resize(sync_segm_length, C_EXP_WIDTH); 
Count: 194356641
Threshold: 1

---

If statement on lines 400 to 403:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 
402:                             else 
403:                         '0'; 
Count: 47278920
Threshold: 1

---

Signal assignment statement on line 400:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
Count: 24152305
Threshold: 1

---

Signal assignment statement on line 403:

403:                         '0'; 
Count: 23126615
Threshold: 1

---

If statement on lines 407 to 413:

407:        if (res_n = '0') then 
408:            exp_seg_length_q <= (others => '1'); 
...
412:            end if; 
413:        end if; 
Count: 1090018206
Threshold: 1

---

Signal assignment statement on line 408:

408:            exp_seg_length_q <= (others => '1'); 
Count: 2424883
Threshold: 1

---

If statement on lines 410 to 412:

410:            if (exp_seg_length_ce = '1') then 
411:                exp_seg_length_q <= exp_seg_length_d; 
412:            end if; 
Count: 543791678
Threshold: 1

---

Signal assignment statement on line 411:

411:                exp_seg_length_q <= exp_seg_length_d; 
Count: 23517458
Threshold: 1

---

Signal assignment statement on lines 425 to 426:

425:    neg_phase_err  <= resize(unsigned(tseg_2), C_E_WIDTH) - 
426:                      resize(unsigned(segm_counter), C_E_WIDTH); 
Count: 317556631
Threshold: 1

---

If statement on lines 428 to 429:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
429:                 resize(unsigned(segm_counter), C_E_WIDTH); 
Count: 635106815
Threshold: 1

---

Signal assignment statement on line 428:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
Count: 197866265
Threshold: 1

---

Signal assignment statement on line 429:

429:                 resize(unsigned(segm_counter), C_E_WIDTH); 
Count: 437240550
Threshold: 1

---

If statement on lines 431 to 434:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
433:                            else 
434:                        '0'; 
Count: 328919755
Threshold: 1

---

Signal assignment statement on line 431:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
Count: 201962334
Threshold: 1

---

Signal assignment statement on line 434:

434:                        '0'; 
Count: 126957421
Threshold: 1

---

If statement on lines 436 to 439:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
438:                            else 
439:                        '0'; 
Count: 328919755
Threshold: 1

---

Signal assignment statement on line 436:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
Count: 18748721
Threshold: 1

---

Signal assignment statement on line 439:

439:                        '0'; 
Count: 310171034
Threshold: 1

---

If statement on lines 441 to 445:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 
444:                                else 
445:                            '0'; 
Count: 328919755
Threshold: 1

---

Signal assignment statement on line 441:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
Count: 14000163
Threshold: 1

---

Signal assignment statement on line 445:

445:                            '0'; 
Count: 314919592
Threshold: 1

---

If statement on lines 447 to 448:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
448:                   '0'; 
Count: 10049
Threshold: 1

---

Signal assignment statement on line 447:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
Count: 8248
Threshold: 1

---

Signal assignment statement on line 448:

448:                   '0'; 
Count: 1801
Threshold: 1

---

If statement on lines 458 to 461:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 
460:                              else 
461:                          '0'; 
Count: 59729620
Threshold: 1

---

Signal assignment statement on line 458:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
Count: 13196
Threshold: 1

---

Signal assignment statement on line 461:

461:                          '0'; 
Count: 59716424
Threshold: 1

---

If statement on lines 468 to 470:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
469:                                     else 
470:                                 '0'; 
Count: 28029877
Threshold: 1

---

Signal assignment statement on line 468:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
Count: 12832
Threshold: 1

---

Signal assignment statement on line 470:

470:                                 '0'; 
Count: 28017045
Threshold: 1

---

If statement on lines 475 to 478:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 
477:                             else 
478:                         '0'; 
Count: 340366932
Threshold: 1

---

Signal assignment statement on line 475:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
Count: 25716686
Threshold: 1

---

Signal assignment statement on line 478:

478:                         '0'; 
Count: 314650246
Threshold: 1

---

If statement on lines 486 to 491:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 
488:                                    else 
489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
490:                                    else 
491:                                '0'; 
Count: 47419804
Threshold: 1

---

Signal assignment statement on line 486:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
Count: 623215
Threshold: 1

---

Signal assignment statement on line 489:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
Count: 6700930
Threshold: 1

---

Signal assignment statement on line 491:

491:                                '0'; 
Count: 40095659
Threshold: 1

---

If statement on lines 496 to 498:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
497:                                   else 
498:                               '0'; 
Count: 45826293
Threshold: 1

---

Signal assignment statement on line 496:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
Count: 16337588
Threshold: 1

---

Signal assignment statement on line 498:

498:                               '0'; 
Count: 29488705
Threshold: 1

---

If statement on lines 507 to 510:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
509:                         else 
510:                     '0'; 
Count: 39529108
Threshold: 1

---

Signal assignment statement on line 507:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
Count: 23055314
Threshold: 1

---

Signal assignment statement on line 510:

510:                     '0'; 
Count: 16473794
Threshold: 1

"if" / "when" / "else" condition on line 273:

273:        if (a > b) then 

	Evaluated to	Count	Threshold
Bin	True	6404	1
Bin	False	1601	1

---

"if" / "when" / "else" condition on lines 351 to 353:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	34296120	1
Bin	False	34169909	1

---

"if" / "when" / "else" condition on line 357:

357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	34167973	1
Bin	False	34184649	1

---

"if" / "when" / "else" condition on lines 361 to 362:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	105893	1
Bin	False	340477954	1

---

"if" / "when" / "else" condition on line 363:

363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 

	Evaluated to	Count	Threshold
Bin	True	205528635	1
Bin	False	134949319	1

---

"if" / "when" / "else" condition on lines 372 to 373:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 

	Evaluated to	Count	Threshold
Bin	True	100809610	1
Bin	False	134633792	1

---

"if" / "when" / "else" condition on lines 384 to 386:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 

	Evaluated to	Count	Threshold
Bin	True	22779886	1
Bin	False	22915406	1

---

"if" / "when" / "else" condition on line 396:

396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 

	Evaluated to	Count	Threshold
Bin	True	150780305	1
Bin	False	194356641	1

---

"if" / "when" / "else" condition on lines 400 to 401:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 

	Evaluated to	Count	Threshold
Bin	True	24152305	1
Bin	False	23126615	1

---

"if" / "when" / "else" condition on line 407:

407:        if (res_n = '0') then 

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

---

"if" / "when" / "else" condition on line 409:

409:        elsif (rising_edge(clk_sys)) then 

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

---

"if" / "when" / "else" condition on line 410:

410:            if (exp_seg_length_ce = '1') then 

	Evaluated to	Count	Threshold
Bin	True	23517458	1
Bin	False	520274220	1

---

"if" / "when" / "else" condition on line 428:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	197866265	1
Bin	False	437240550	1

---

"if" / "when" / "else" condition on lines 431 to 432:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 

	Evaluated to	Count	Threshold
Bin	True	201962334	1
Bin	False	126957421	1

---

"if" / "when" / "else" condition on lines 436 to 437:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 

	Evaluated to	Count	Threshold
Bin	True	18748721	1
Bin	False	310171034	1

---

"if" / "when" / "else" condition on lines 441 to 443:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 

	Evaluated to	Count	Threshold
Bin	True	14000163	1
Bin	False	314919592	1

---

"if" / "when" / "else" condition on line 447:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 

	Evaluated to	Count	Threshold
Bin	True	8248	1
Bin	False	1801	1

---

"if" / "when" / "else" condition on lines 458 to 459:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 

	Evaluated to	Count	Threshold
Bin	True	13196	1
Bin	False	59716424	1

---

"if" / "when" / "else" condition on line 468:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 

	Evaluated to	Count	Threshold
Bin	True	12832	1
Bin	False	28017045	1

---

"if" / "when" / "else" condition on lines 475 to 476:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 

	Evaluated to	Count	Threshold
Bin	True	25716686	1
Bin	False	314650246	1

---

"if" / "when" / "else" condition on lines 486 to 487:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 

	Evaluated to	Count	Threshold
Bin	True	623215	1
Bin	False	46796589	1

---

"if" / "when" / "else" condition on line 489:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 

	Evaluated to	Count	Threshold
Bin	True	6700930	1
Bin	False	40095659	1

---

"if" / "when" / "else" condition on line 496:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 

	Evaluated to	Count	Threshold
Bin	True	16337588	1
Bin	False	29488705	1

---

"if" / "when" / "else" condition on lines 507 to 508:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 

	Evaluated to	Count	Threshold
Bin	True	23055314	1
Bin	False	16473794	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RESYNC_EDGE_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TSEG_1

	Element	From	To	Count	Threshold	Excluded due to
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TSEG_2

	Element	From	To	Count	Threshold	Excluded due to
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 SJW

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 START_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SEGM_COUNTER

	Element	From	To	Count	Threshold	Excluded due to
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 SEGM_END

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 H_SYNC_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

 EXIT_SEGM_REQ

	From	To	Count	Threshold
Bin	0	1	16470592	1
Bin	1	0	16472193	1

---

Signal:

 SEL_TSEG1

	From	To	Count	Threshold
Bin	0	1	34164331	1
Bin	1	0	34165922	1

---

Signal:

 EXP_SEG_LENGTH_CE

	From	To	Count	Threshold
Bin	0	1	23121812	1
Bin	1	0	23123413	1

---

Signal:

 PHASE_ERR_MT_SJW

	From	To	Count	Threshold
Bin	0	1	11448607	1
Bin	1	0	11450200	1

---

Signal:

 PHASE_ERR_EQ_SJW

	From	To	Count	Threshold
Bin	0	1	18748721	1
Bin	1	0	18750320	1

---

Signal:

 EXIT_PH2_IMMEDIATE

	From	To	Count	Threshold
Bin	0	1	13183	1
Bin	1	0	14784	1

---

Signal:

 EXIT_SEGM_REGULAR

	From	To	Count	Threshold
Bin	0	1	16469743	1
Bin	1	0	16471344	1

---

Signal:

 EXIT_SEGM_REGULAR_TSEG1

	From	To	Count	Threshold
Bin	0	1	6700928	1
Bin	1	0	6702529	1

---

Signal:

 EXIT_SEGM_REGULAR_TSEG2

	From	To	Count	Threshold
Bin	0	1	16337588	1
Bin	1	0	16339189	1

---

Signal:

 SJW_MT_ZERO

	From	To	Count	Threshold
Bin	0	1	1793	1
Bin	1	0	1801	1

---

Signal:

 USE_BASIC_SEGM_LENGTH

	From	To	Count	Threshold
Bin	0	1	22779886	1
Bin	1	0	22781487	1

---

Signal:

 PHASE_ERR_SJW_BY_ONE

	From	To	Count	Threshold
Bin	0	1	14000163	1
Bin	1	0	14001760	1

---

Signal:

 SHORTEN_TSEG1_AFTER_TSEG2

	From	To	Count	Threshold
Bin	0	1	12832	1
Bin	1	0	14433	1

">" expression on line 273:

 a > b 

	Evaluated to	Count	Threshold
Bin	False	1601	1
Bin	True	6404	1

---

"or" expression on lines 351 to 353:

 (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or (segm_end = '1' and is_tseg2 = '1') or (segm_end = '0' and is_tseg1 = '1') 
 <------------------------------------------------------LHS------------------------------------------------------->     <--------------RHS-------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	34169909	1
Bin	False	True	11438127	1
Bin	True	False	22805980	1

---

"or" expression on lines 351 to 352:

 (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or (segm_end = '1' and is_tseg2 = '1') 
  <----------------------------------LHS---------------------------------->      <--------------RHS-------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	45608036	1
Bin	False	True	22747322	1
Bin	True	False	93783	1

---

"or" expression on line 351:

 h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1' 
 <----------------LHS----------------->    <-------------RHS-------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	68355358	1
Bin	False	True	22517	1
Bin	True	False	88154	1

---

"or" expression on line 351:

 h_sync_valid = '1' or start_edge = '1' 
 <------LHS------->    <-----RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	False	68377875	1
Bin	False	True	6482	1
Bin	True	False	81672	1

---

"=" expression on line 351:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	68384357	1
Bin	True	81672	1

---

"=" expression on line 351:

 start_edge = '1' 

	Evaluated to	Count	Threshold
Bin	False	68459547	1
Bin	True	6482	1

---

"=" expression on line 351:

 shorten_tseg1_after_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	68443512	1
Bin	True	22517	1

---

"and" expression on line 352:

 segm_end = '1' and is_tseg2 = '1' 
 <----LHS----->     <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	11397091	1
Bin	True	False	22803314	1
Bin	True	True	22764210	1

---

"=" expression on line 352:

 segm_end = '1' 

	Evaluated to	Count	Threshold
Bin	False	22898505	1
Bin	True	45567524	1

---

"=" expression on line 352:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34304728	1
Bin	True	34161301	1

---

"and" expression on line 353:

 segm_end = '0' and is_tseg1 = '1' 
 <----LHS----->     <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	22804196	1
Bin	True	False	11405163	1
Bin	True	True	11490140	1

---

"=" expression on line 353:

 segm_end = '0' 

	Evaluated to	Count	Threshold
Bin	False	45570726	1
Bin	True	22895303	1

---

"=" expression on line 353:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34171693	1
Bin	True	34294336	1

---

"=" expression on line 357:

 sel_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34184649	1
Bin	True	34167973	1

---

"or" expression on lines 361 to 362:

 h_sync_valid = '1' or shorten_tseg1_after_tseg2 = '1' 
 <------LHS------->    <-------------RHS-------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	340477954	1
Bin	False	True	21906	1
Bin	True	False	83987	1

---

"=" expression on line 361:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	340499860	1
Bin	True	83987	1

---

"=" expression on line 362:

 shorten_tseg1_after_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	340561941	1
Bin	True	21906	1

---

"=" expression on line 363:

 phase_err_mt_sjw = '1' 

	Evaluated to	Count	Threshold
Bin	False	134949319	1
Bin	True	205528635	1

---

"or" expression on lines 372 to 373:

 is_tseg2 = '1' or h_sync_valid = '1' or exit_ph2_immediate = '1' 
 <---------------LHS---------------->    <---------RHS----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	134633792	1
Bin	False	True	9384	1
Bin	True	False	100764908	1

---

"or" expression on line 372:

 is_tseg2 = '1' or h_sync_valid = '1' 
 <----LHS----->    <------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	False	134643176	1
Bin	False	True	106559	1
Bin	True	False	100670379	1

---

"=" expression on line 372:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	134749735	1
Bin	True	100693667	1

---

"=" expression on line 372:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	235313555	1
Bin	True	129847	1

---

"=" expression on line 373:

 exit_ph2_immediate = '1' 

	Evaluated to	Count	Threshold
Bin	False	235398700	1
Bin	True	44702	1

---

"or" expression on lines 384 to 386:

 (start_edge = '1') or (segm_end = '1' and h_sync_valid = '0' and shorten_tseg1_after_tseg2 = '0') 
  <-----LHS------>      <----------------------------------RHS---------------------------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	22915406	1
Bin	False	True	22773404	1
Bin	True	False	6482	1

---

"=" expression on line 384:

 start_edge = '1' 

	Evaluated to	Count	Threshold
Bin	False	45688810	1
Bin	True	6482	1

---

"and" expression on lines 385 to 386:

 segm_end = '1' and h_sync_valid = '0' and shorten_tseg1_after_tseg2 = '0' 
 <----------------LHS---------------->     <-------------RHS-------------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22906895	1
Bin	True	False	9132	1
Bin	True	True	22773404	1

---

"and" expression on line 385:

 segm_end = '1' and h_sync_valid = '0' 
 <----LHS----->     <------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22835525	1
Bin	True	False	21604	1
Bin	True	True	22782536	1

---

"=" expression on line 385:

 segm_end = '1' 

	Evaluated to	Count	Threshold
Bin	False	22891152	1
Bin	True	22804140	1

---

"=" expression on line 385:

 h_sync_valid = '0' 

	Evaluated to	Count	Threshold
Bin	False	77231	1
Bin	True	45618061	1

---

"=" expression on line 386:

 shorten_tseg1_after_tseg2 = '0' 

	Evaluated to	Count	Threshold
Bin	False	14993	1
Bin	True	45680299	1

---

"=" expression on line 396:

 use_basic_segm_length = '1' 

	Evaluated to	Count	Threshold
Bin	False	194356641	1
Bin	True	150780305	1

---

"or" expression on lines 400 to 401:

 segm_end = '1' or resync_edge_valid = '1' or h_sync_valid = '1' or start_edge = '1' 
 <-----------------------------LHS----------------------------->    <-----RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	False	23126615	1
Bin	False	True	6482	1
Bin	True	False	24145823	1

---

"or" expression on lines 400 to 401:

 segm_end = '1' or resync_edge_valid = '1' or h_sync_valid = '1' 
 <------------------LHS------------------>    <------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	False	23133097	1
Bin	False	True	52425	1
Bin	True	False	24071794	1

---

"or" expression on line 400:

 segm_end = '1' or resync_edge_valid = '1' 
 <----LHS----->    <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	False	23185522	1
Bin	False	True	729814	1
Bin	True	False	22865553	1

---

"=" expression on line 400:

 segm_end = '1' 

	Evaluated to	Count	Threshold
Bin	False	23915336	1
Bin	True	23363584	1

---

"=" expression on line 400:

 resync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	46051075	1
Bin	True	1227845	1

---

"=" expression on line 401:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	47204891	1
Bin	True	74029	1

---

"=" expression on line 401:

 start_edge = '1' 

	Evaluated to	Count	Threshold
Bin	False	47272438	1
Bin	True	6482	1

---

"=" expression on line 407:

 res_n = '0' 

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

---

"=" expression on line 410:

 exp_seg_length_ce = '1' 

	Evaluated to	Count	Threshold
Bin	False	520274220	1
Bin	True	23517458	1

---

"=" expression on line 428:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	437240550	1
Bin	True	197866265	1

---

"and" expression on lines 458 to 459:

 (phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and is_tseg2 = '1' and resync_edge_valid = '1' 
 <----------------------------------LHS---------------------------------->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	787271	1
Bin	True	False	20371492	1
Bin	True	True	13196	1

---

"and" expression on lines 458 to 459:

 (phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and is_tseg2 = '1' 
  <-----------------------LHS------------------------>      <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	9987613	1
Bin	True	False	23148713	1
Bin	True	True	20384688	1

---

"or" expression on line 458:

 phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1' 
 <--------LHS--------->    <----------RHS-----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	16196219	1
Bin	False	True	19698737	1
Bin	True	False	23834664	1

---

"=" expression on line 458:

 phase_err_mt_sjw = '0' 

	Evaluated to	Count	Threshold
Bin	False	35894956	1
Bin	True	23834664	1

---

"=" expression on line 458:

 phase_err_sjw_by_one = '1' 

	Evaluated to	Count	Threshold
Bin	False	40030883	1
Bin	True	19698737	1

---

"=" expression on line 459:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	29357319	1
Bin	True	30372301	1

---

"=" expression on line 459:

 resync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	58929153	1
Bin	True	800467	1

---

"and" expression on line 468:

 exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0' 
 <---------LHS---------->     <----------RHS-----------> 

	LHS	RHS	Count	Threshold
Bin	False	True	14014579	1
Bin	True	False	351	1
Bin	True	True	12832	1

---

"=" expression on line 468:

 exit_ph2_immediate = '1' 

	Evaluated to	Count	Threshold
Bin	False	28016694	1
Bin	True	13183	1

---

"=" expression on line 468:

 phase_err_sjw_by_one = '0' 

	Evaluated to	Count	Threshold
Bin	False	14002466	1
Bin	True	14027411	1

---

"and" expression on lines 486 to 487:

 is_tseg1 = '1' and resync_edge_valid = '1' and sjw_mt_zero = '1' 
 <------------------LHS------------------->     <------RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	True	40545825	1
Bin	True	False	156272	1
Bin	True	True	623215	1

---

"and" expression on line 486:

 is_tseg1 = '1' and resync_edge_valid = '1' 
 <----LHS----->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	20874	1
Bin	True	False	18883879	1
Bin	True	True	779487	1

---

"=" expression on line 486:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	27756438	1
Bin	True	19663366	1

---

"=" expression on line 486:

 resync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	46619443	1
Bin	True	800361	1

---

"=" expression on line 487:

 sjw_mt_zero = '1' 

	Evaluated to	Count	Threshold
Bin	False	6250764	1
Bin	True	41169040	1

---

"and" expression on line 489:

 is_tseg1 = '1' and exit_segm_regular = '1' 
 <----LHS----->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	16353563	1
Bin	True	False	12339221	1
Bin	True	True	6700930	1

---

"=" expression on line 489:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	27756438	1
Bin	True	19040151	1

---

"=" expression on line 489:

 exit_segm_regular = '1' 

	Evaluated to	Count	Threshold
Bin	False	23742096	1
Bin	True	23054493	1

---

"and" expression on line 496:

 is_tseg2 = '1' and exit_segm_regular = '1' 
 <----LHS----->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	6701010	1
Bin	True	False	11382739	1
Bin	True	True	16337588	1

---

"=" expression on line 496:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	18105966	1
Bin	True	27720327	1

---

"=" expression on line 496:

 exit_segm_regular = '1' 

	Evaluated to	Count	Threshold
Bin	False	22787695	1
Bin	True	23038598	1

---

"or" expression on lines 507 to 508:

 (exit_ph2_immediate = '1') or (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
  <---------LHS---------->      <----------------------------RHS----------------------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	16473794	1
Bin	False	True	23042131	1
Bin	True	False	926	1

---

"=" expression on line 507:

 exit_ph2_immediate = '1' 

	Evaluated to	Count	Threshold
Bin	False	39515925	1
Bin	True	13183	1

---

"or" expression on line 508:

 exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1' 
 <------------LHS------------>    <------------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	16474720	1
Bin	False	True	16353460	1
Bin	True	False	6700928	1

---

"=" expression on line 508:

 exit_segm_regular_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	32828180	1
Bin	True	6700928	1

---

"=" expression on line 508:

 exit_segm_regular_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	23175648	1
Bin	True	16353460	1