File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Prescaler circuit.
71: --
72: -- Sub-modules:
73: -- 1. Bit time config capture
74: -- 2. Synchronisation checker
75: -- 3. Bit time counters (Nominal)
76: -- 4. Bit segment meter (Nominal)
77: -- 5. Bit time counters (Data)
78: -- 6. Bit segment meter (Data)
79: -- 7. Segment end detector
80: -- 8. Bit time FSM.
81: -- 9. Trigger generator.
82: --------------------------------------------------------------------------------
83:
84: Library ieee;
85: use ieee.std_logic_1164.all;
86: use ieee.numeric_std.ALL;
87:
88: Library ctu_can_fd_rtl;
89: use ctu_can_fd_rtl.can_constants_pkg.all;
90: use ctu_can_fd_rtl.can_types_pkg.all;
91:
92: use ctu_can_fd_rtl.CAN_FD_register_map.all;
93: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
94:
95: entity prescaler is
96: generic (
97: -- TSEG1 Width - Nominal Bit Time
98: G_TSEG1_NBT_WIDTH : natural;
99:
100: -- TSEG2 Width - Nominal Bit Time
101: G_TSEG2_NBT_WIDTH : natural;
102:
103: -- Baud rate prescaler Width - Nominal Bit Time
104: G_BRP_NBT_WIDTH : natural;
105:
106: -- Synchronisation Jump width Width - Nominal Bit Time
107: G_SJW_NBT_WIDTH : natural;
108:
109: -- TSEG1 Width - Data Bit Time
110: G_TSEG1_DBT_WIDTH : natural;
111:
112: -- TSEG2 Width - Data Bit Time
113: G_TSEG2_DBT_WIDTH : natural;
114:
115: -- Baud rate prescaler width - Data Bit Time
116: G_BRP_DBT_WIDTH : natural;
117:
118: -- Synchronisation Jump Width width - Data Bit Time
119: G_SJW_DBT_WIDTH : natural;
120:
121: -- Number of signals in Sample trigger
122: G_SAMPLE_TRIGGER_COUNT : natural range 2 to 8
123: );
124: port(
125: -------------------------------------------------------------------------------------------
126: -- Clock and Asynchronous reset
127: -------------------------------------------------------------------------------------------
128: clk_sys : in std_logic;
129: res_n : in std_logic;
130:
131: -------------------------------------------------------------------------------------------
132: -- Memory registers interface
133: -------------------------------------------------------------------------------------------
134: mr_settings_ena : in std_logic;
135:
136: mr_btr_prop : in std_logic_vector(6 downto 0);
137: mr_btr_ph1 : in std_logic_vector(5 downto 0);
138: mr_btr_ph2 : in std_logic_vector(5 downto 0);
139: mr_btr_brp : in std_logic_vector(7 downto 0);
140: mr_btr_sjw : in std_logic_vector(4 downto 0);
141:
142: mr_btr_fd_prop_fd : in std_logic_vector(5 downto 0);
143: mr_btr_fd_ph1_fd : in std_logic_vector(4 downto 0);
144: mr_btr_fd_ph2_fd : in std_logic_vector(4 downto 0);
145: mr_btr_fd_brp_fd : in std_logic_vector(7 downto 0);
146: mr_btr_fd_sjw_fd : in std_logic_vector(4 downto 0);
147:
148: -------------------------------------------------------------------------------------------
149: -- Control Interface
150: -------------------------------------------------------------------------------------------
151: -- Synchronisation edge (from Bus sampling)
152: sync_edge : in std_logic;
153:
154: -- Sample control (Nominal, Data, Secondary)
155: sp_control : in std_logic_vector(1 downto 0);
156:
157: -- Synchronisation control (No synchronisation, Hard Synchronisation,
158: -- Resynchronisation
159: sync_control : in std_logic_vector(1 downto 0);
160:
161: -- No re-synchronisation should be executed due to positive phase
162: -- error
163: no_pos_resync : in std_logic;
164:
165: -- Enable Nominal Bit time counters.
166: nbt_ctrs_en : in std_logic;
167:
168: -- Enable Data Bit time counters.
169: dbt_ctrs_en : in std_logic;
170:
171: -------------------------------------------------------------------------------------------
172: -- Trigger signals
173: -------------------------------------------------------------------------------------------
174: -- RX Triggers
175: rx_triggers : out std_logic_vector(G_SAMPLE_TRIGGER_COUNT - 1 downto 0);
176:
177: -- TX Trigger
178: tx_trigger : out std_logic;
179:
180: -------------------------------------------------------------------------------------------
181: -- Status outputs
182: -------------------------------------------------------------------------------------------
183: -- Time quanta edge
184: tq_edge : out std_logic
185: );
186: end entity;
187:
188: architecture rtl of prescaler is
189:
190: -----------------------------------------------------------------------------------------------
191: -- Segment lengths
192: -----------------------------------------------------------------------------------------------
193: -- Nominal Bit-rate
194: signal tseg1_nbt : std_logic_vector(G_TSEG1_NBT_WIDTH - 1 downto 0);
195: signal tseg2_nbt : std_logic_vector(G_TSEG2_NBT_WIDTH - 1 downto 0);
196: signal brp_nbt : std_logic_vector(G_BRP_NBT_WIDTH - 1 downto 0);
197: signal sjw_nbt : std_logic_vector(G_SJW_NBT_WIDTH - 1 downto 0);
198:
199: -- Data Bit-rate
200: signal tseg1_dbt : std_logic_vector(G_TSEG1_DBT_WIDTH - 1 downto 0);
201: signal tseg2_dbt : std_logic_vector(G_TSEG2_DBT_WIDTH - 1 downto 0);
202: signal brp_dbt : std_logic_vector(G_BRP_DBT_WIDTH - 1 downto 0);
203: signal sjw_dbt : std_logic_vector(G_SJW_DBT_WIDTH - 1 downto 0);
204:
205: -- End of segment is detected (by segment end detector)
206: signal segment_end : std_logic;
207:
208: -- Valid hard synchronisation occurred
209: signal h_sync_valid : std_logic;
210:
211: -- Signalling of each segment (by Bit Time FSM)
212: signal is_tseg1 : std_logic;
213: signal is_tseg2 : std_logic;
214:
215: -- Hard/Re-Synchronisation edges are valid. This only signals that sync. edge is there, sync
216: -- control is set accordingly and there was no previous synchronisation from sample point
217: -- till now!
218: signal resync_edge_valid : std_logic;
219: signal h_sync_edge_valid : std_logic;
220:
221: -- Size of internal Bit time counters.
222: -- Should cover largest segment that can be counted in the given bit-rate also with synchronisation!
223: -- Nominal: SYNC (1) + PROP_NBT (127) + PH1_NBT (63) + SJW_NBT (31) = 222 -> Fits into 8 bits
224: -- Data: SYNC (1) + PROP_DBT (63) + PH1_DBT (31) + SJW_DBT (31) = 126 -> Fits into 7 bits
225: constant C_BT_NBT_WIDTH : natural := 8;
226: constant C_BT_DBT_WIDTH : natural := 7;
227:
228: -- Bit time counter values.
229: signal segm_counter_nbt : std_logic_vector(C_BT_NBT_WIDTH - 1 downto 0);
230: signal segm_counter_dbt : std_logic_vector(C_BT_DBT_WIDTH - 1 downto 0);
231:
232: -- Exit segment requests from re-synchronisation circuits
233: signal exit_segm_req_nbt : std_logic;
234: signal exit_segm_req_dbt : std_logic;
235:
236: -- Time quanta edges
237: signal tq_edge_nbt : std_logic;
238: signal tq_edge_dbt : std_logic;
239:
240: -- Sample trigger request (in sample point)
241: signal rx_trig_req : std_logic;
242:
243: -- Sync trigger request (in beginning of SYNC segment)
244: signal tx_trig_req : std_logic;
245:
246: -- Signal that expected semgent length should be loaded after restart!
247: signal start_edge : std_logic;
248:
249: -- Bit time counter clear
250: signal bt_ctr_clear : std_logic;
251:
252: -- Constants defined for PSL assertions only.
253: constant C_NBT_ONES : std_logic_vector(C_BT_NBT_WIDTH - 1 downto 0) := (others => '1');
254: constant C_DBT_ONES : std_logic_vector(C_BT_DBT_WIDTH - 1 downto 0) := (others => '1');
255:
256: begin
257:
258: -----------------------------------------------------------------------------------------------
259: -- Bit time config capture
260: -----------------------------------------------------------------------------------------------
261: bit_time_cfg_capture_inst : entity ctu_can_fd_rtl.bit_time_cfg_capture
262: generic map (
263: G_TSEG1_NBT_WIDTH => G_TSEG1_NBT_WIDTH,
264: G_TSEG2_NBT_WIDTH => G_TSEG2_NBT_WIDTH,
265: G_BRP_NBT_WIDTH => G_BRP_NBT_WIDTH,
266: G_SJW_NBT_WIDTH => G_SJW_NBT_WIDTH,
267: G_TSEG1_DBT_WIDTH => G_TSEG1_DBT_WIDTH,
268: G_TSEG2_DBT_WIDTH => G_TSEG2_DBT_WIDTH,
269: G_BRP_DBT_WIDTH => G_BRP_DBT_WIDTH,
270: G_SJW_DBT_WIDTH => G_SJW_DBT_WIDTH
271: )
272: port map (
273: clk_sys => clk_sys, -- IN
274: res_n => res_n, -- IN
275:
276: -- Direct configuration from Memory registers
277: mr_settings_ena => mr_settings_ena, -- IN
278: mr_btr_prop => mr_btr_prop, -- IN
279: mr_btr_ph1 => mr_btr_ph1, -- IN
280: mr_btr_ph2 => mr_btr_ph2, -- IN
281: mr_btr_brp => mr_btr_brp, -- IN
282: mr_btr_sjw => mr_btr_sjw, -- IN
283: mr_btr_fd_prop_fd => mr_btr_fd_prop_fd, -- IN
284: mr_btr_fd_ph1_fd => mr_btr_fd_ph1_fd, -- IN
285: mr_btr_fd_ph2_fd => mr_btr_fd_ph2_fd, -- IN
286: mr_btr_fd_brp_fd => mr_btr_fd_brp_fd, -- IN
287: mr_btr_fd_sjw_fd => mr_btr_fd_sjw_fd, -- IN
288:
289: -- Captured / converted values
290: tseg1_nbt => tseg1_nbt, -- OUT
291: tseg2_nbt => tseg2_nbt, -- OUT
292: brp_nbt => brp_nbt, -- OUT
293: sjw_nbt => sjw_nbt, -- OUT
294: tseg1_dbt => tseg1_dbt, -- OUT
295: tseg2_dbt => tseg2_dbt, -- OUT
296: brp_dbt => brp_dbt, -- OUT
297: sjw_dbt => sjw_dbt, -- OUT
298: start_edge => start_edge -- OUT
299: );
300:
301: -----------------------------------------------------------------------------------------------
302: -- Synchronisation checker
303: -----------------------------------------------------------------------------------------------
304: synchronisation_checker_inst : entity ctu_can_fd_rtl.synchronisation_checker
305: port map (
306: clk_sys => clk_sys, -- IN
307: res_n => res_n, -- IN
308: sync_control => sync_control, -- IN
309: sync_edge => sync_edge, -- IN
310: no_pos_resync => no_pos_resync, -- IN
311: segment_end => segment_end, -- IN
312: is_tseg1 => is_tseg1, -- IN
313: is_tseg2 => is_tseg2, -- IN
314:
315: resync_edge_valid => resync_edge_valid, -- OUT
316: h_sync_edge_valid => h_sync_edge_valid -- OUT
317: );
318:
319:
320: -----------------------------------------------------------------------------------------------
321: -- Bit segment meter (Nominal Bit Time)
322: -----------------------------------------------------------------------------------------------
323: bit_segment_meter_nbt_inst : entity ctu_can_fd_rtl.bit_segment_meter
324: generic map (
325: G_SJW_WIDTH => G_SJW_NBT_WIDTH,
326: G_TSEG1_WIDTH => G_TSEG1_NBT_WIDTH,
327: G_TSEG2_WIDTH => G_TSEG2_NBT_WIDTH,
328: G_BT_WIDTH => C_BT_NBT_WIDTH
329: )
330: port map (
331: clk_sys => clk_sys, -- IN
332: res_n => res_n, -- IN
333: resync_edge_valid => resync_edge_valid, -- IN
334: is_tseg1 => is_tseg1, -- IN
335: is_tseg2 => is_tseg2, -- IN
336: tseg_1 => tseg1_nbt, -- IN
337: tseg_2 => tseg2_nbt, -- IN
338: sjw => sjw_nbt, -- IN
339: start_edge => start_edge, -- IN
340: segm_counter => segm_counter_nbt, -- IN
341: segm_end => segment_end, -- IN
342: h_sync_valid => h_sync_valid, -- IN
343:
344: exit_segm_req => exit_segm_req_nbt -- OUT
345: );
346:
347:
348: -----------------------------------------------------------------------------------------------
349: -- Bit Time counter (Nominal Bit Time)
350: -----------------------------------------------------------------------------------------------
351: bit_time_counters_nbt_inst : entity ctu_can_fd_rtl.bit_time_counters
352: generic map (
353: G_BT_WIDTH => C_BT_NBT_WIDTH,
354: G_BRP_WIDTH => G_BRP_NBT_WIDTH
355: )
356: port map (
357: clk_sys => clk_sys, -- IN
358: res_n => res_n, -- IN
359: brp => brp_nbt, -- IN
360: tq_reset => bt_ctr_clear, -- IN
361: bt_reset => bt_ctr_clear, -- IN
362: ctrs_en => nbt_ctrs_en, -- IN
363:
364: tq_edge => tq_edge_nbt, -- OUT
365: segm_counter => segm_counter_nbt -- OUT
366: );
367:
368:
369: -----------------------------------------------------------------------------------------------
370: -- Bit segment meter (Data Bit Time)
371: -----------------------------------------------------------------------------------------------
372: bit_segment_meter_dbt_inst : entity ctu_can_fd_rtl.bit_segment_meter
373: generic map (
374: G_SJW_WIDTH => G_SJW_DBT_WIDTH,
375: G_TSEG1_WIDTH => G_TSEG1_DBT_WIDTH,
376: G_TSEG2_WIDTH => G_TSEG2_DBT_WIDTH,
377: G_BT_WIDTH => C_BT_DBT_WIDTH
378: )
379: port map (
380: clk_sys => clk_sys, -- IN
381: res_n => res_n, -- IN
382: resync_edge_valid => resync_edge_valid, -- IN
383: is_tseg1 => is_tseg1, -- IN
384: is_tseg2 => is_tseg2, -- IN
385: tseg_1 => tseg1_dbt, -- IN
386: tseg_2 => tseg2_dbt, -- IN
387: sjw => sjw_dbt, -- IN
388: start_edge => start_edge, -- IN
389: segm_counter => segm_counter_dbt, -- IN
390: segm_end => segment_end, -- IN
391: h_sync_valid => h_sync_valid, -- IN
392:
393: exit_segm_req => exit_segm_req_dbt -- OUT
394: );
395:
396:
397: -----------------------------------------------------------------------------------------------
398: -- Bit Time counter (Data Bit Time)
399: -----------------------------------------------------------------------------------------------
400: bit_time_counters_dbt_inst : entity ctu_can_fd_rtl.bit_time_counters
401: generic map (
402: G_BT_WIDTH => C_BT_DBT_WIDTH,
403: G_BRP_WIDTH => G_BRP_DBT_WIDTH
404: )
405: port map (
406: clk_sys => clk_sys, -- IN
407: res_n => res_n, -- IN
408: brp => brp_dbt, -- IN
409: tq_reset => bt_ctr_clear, -- IN
410: bt_reset => bt_ctr_clear, -- IN
411: ctrs_en => dbt_ctrs_en, -- IN
412:
413: tq_edge => tq_edge_dbt, -- OUT
414: segm_counter => segm_counter_dbt -- OUT
415: );
416:
417: -----------------------------------------------------------------------------------------------
418: -- End of Segment detector
419: -----------------------------------------------------------------------------------------------
420: segment_end_detector_inst : entity ctu_can_fd_rtl.segment_end_detector
421: port map (
422: clk_sys => clk_sys, -- IN
423: res_n => res_n, -- IN
424: sp_control => sp_control, -- IN
425: h_sync_edge_valid => h_sync_edge_valid, -- IN
426: exit_segm_req_nbt => exit_segm_req_nbt, -- IN
427: exit_segm_req_dbt => exit_segm_req_dbt, -- IN
428: is_tseg1 => is_tseg1, -- IN
429: is_tseg2 => is_tseg2, -- IN
430: tq_edge_nbt => tq_edge_nbt, -- IN
431: tq_edge_dbt => tq_edge_dbt, -- IN
432:
433: segm_end => segment_end, -- OUT
434: h_sync_valid => h_sync_valid, -- OUT
435: bt_ctr_clear => bt_ctr_clear -- OUT
436: );
437:
438:
439: -----------------------------------------------------------------------------------------------
440: -- Bit time FSM
441: -----------------------------------------------------------------------------------------------
442: bit_time_fsm_inst : entity ctu_can_fd_rtl.bit_time_fsm
443: port map (
444: clk_sys => clk_sys, -- IN
445: res_n => res_n, -- IN
446: segm_end => segment_end, -- IN
447: mr_settings_ena => mr_settings_ena, -- IN
448:
449: is_tseg1 => is_tseg1, -- OUT
450: is_tseg2 => is_tseg2, -- OUT
451:
452: rx_trig_req => rx_trig_req, -- IN
453: tx_trig_req => tx_trig_req -- IN
454: );
455:
456: -----------------------------------------------------------------------------------------------
457: -- Trigger generator
458: -----------------------------------------------------------------------------------------------
459: trigger_generator_inst : entity ctu_can_fd_rtl.trigger_generator
460: generic map (
461: G_SAMPLE_TRIGGER_COUNT => G_SAMPLE_TRIGGER_COUNT
462: )
463: port map (
464: clk_sys => clk_sys, -- IN
465: res_n => res_n, -- IN
466: rx_trig_req => rx_trig_req, -- IN
467: tx_trig_req => tx_trig_req, -- IN
468:
469: rx_triggers => rx_triggers, -- OUT
470: tx_trigger => tx_trigger -- OUT
471: );
472:
473: tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else
474: tq_edge_dbt;
475:
476:
477: -----------------------------------------------------------------------------------------------
478: -----------------------------------------------------------------------------------------------
479: -- Assertions
480: -----------------------------------------------------------------------------------------------
481: -----------------------------------------------------------------------------------------------
482:
483: -- psl default clock is rising_edge(clk_sys);
484:
485: -- psl min_lenght_ph1_nbt_asrt : assert always
486: -- {mr_settings_ena = '1'} |=>
487: -- {to_integer(unsigned(tseg1_nbt)) * to_integer(unsigned(brp_nbt)) > 2}
488: -- report "Lenght of TSEG1(NBT) must be more than 2 clock cycles!";
489:
490: -- psl min_lenght_ph2_nbt_asrt : assert always
491: -- {mr_settings_ena = '1'} |=>
492: -- {to_integer(unsigned(tseg2_nbt)) * to_integer(unsigned(brp_nbt)) > 1}
493: -- report "Lenght of TSEG2(NBT) must be more than 1 clock cycle!";
494:
495: -- psl min_lenght_ph1_dbt_asrt : assert always
496: -- {mr_settings_ena = '1'} |=>
497: -- {to_integer(unsigned(tseg1_dbt)) * to_integer(unsigned(brp_dbt)) > 2}
498: -- report "Lenght of TSEG1(DBT) must be more than 2 clock cycles!";
499:
500: -- psl min_lenght_ph2_dbt_asrt : assert always
501: -- {mr_settings_ena = '1'} |=>
502: -- {to_integer(unsigned(tseg2_dbt)) * to_integer(unsigned(brp_dbt)) > 1}
503: -- report "Lenght of TSEG2(DBT) must be more than 1 clock cycle!";
504:
505: end architecture;