NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SSP_GENERATOR_INST	100.0 % (55/55)	100.0 % (56/56)	100.0 % (262/262)	100.0 % (65/65)	N.A.	N.A.	100.0 % (438/438)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SSP_GENERATOR_INST

100.0 % (55/55)

100.0 % (56/56)

100.0 % (262/262)

100.0 % (65/65)

N.A.

100.0 % (438/438)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 172 to 175:

172:    btmc_meas_running_d <= '0' when (btmc_reset = '1') else 
173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else 
174:                           '0' when (tx_trigger = '1') else 
175:                           btmc_meas_running_q;

Count: 22851684
Threshold: 1

Signal assignment statement on line 172:

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else
Count: 85725
Threshold: 1

Signal assignment statement on line 173:

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

Count: 3986
Threshold: 1

Signal assignment statement on line 174:

174: '0' when (tx_trigger = '1') else
Count: 11362502
Threshold: 1

Signal assignment statement on line 175:

175: btmc_meas_running_q;
Count: 11399471
Threshold: 1

If statement on lines 179 to 183:

179:        if (res_n = '0') then 
180:            btmc_meas_running_q <= '0'; 
181:        elsif (rising_edge(clk_sys)) then 
182:            btmc_meas_running_q <= btmc_meas_running_d; 
183:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 180:

180: btmc_meas_running_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 182:

182: btmc_meas_running_q <= btmc_meas_running_d;
Count: 543791678
Threshold: 1

If statement on lines 192 to 194:

192:    btmc_d <= (others => '0') when (btmc_reset = '1') else 
193:                     btmc_add when (btmc_meas_running_q = '1') else 
194:                       btmc_q;

Count: 500723
Threshold: 1

Signal assignment statement on line 192:

192: btmc_d <= (others => '0') when (btmc_reset = '1') else
Count: 31555
Threshold: 1

Signal assignment statement on line 193:

193: btmc_add when (btmc_meas_running_q = '1') else
Count: 429197
Threshold: 1

Signal assignment statement on line 194:

194: btmc_q;
Count: 39971
Threshold: 1

Signal assignment statement on line 196:

196: btmc_add <= std_logic_vector(unsigned(btmc_q) + 1);
Count: 220790
Threshold: 1

If statement on lines 198 to 199:

198:    btmc_ce <= '1' when (btmc_d /= btmc_q) else 
199:               '0';

Count: 439979
Threshold: 1

Signal assignment statement on line 198:

198: btmc_ce <= '1' when (btmc_d /= btmc_q) else
Count: 219189
Threshold: 1

Signal assignment statement on line 199:

199: '0';
Count: 220790
Threshold: 1

If statement on lines 203 to 209:

203:        if (res_n = '0') then 
204:            btmc_q <= (others => '0'); 
...
208:            end if; 
209:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 204:

204: btmc_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 206 to 208:

206:            if (btmc_ce = '1') then 
207:                btmc_q <= btmc_d; 
208:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 207:

207: btmc_q <= btmc_d;
Count: 217085
Threshold: 1

If statement on lines 217 to 219:

217:    first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else 
218:                   '0' when (sspc_expired = '1') else 
219:                   first_ssp_q;

Count: 23117787
Threshold: 1

Signal assignment statement on line 217:

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else
Count: 5979
Threshold: 1

Signal assignment statement on line 218:

218: '0' when (sspc_expired = '1') else
Count: 22451459
Threshold: 1

Signal assignment statement on line 219:

219: first_ssp_q;
Count: 660349
Threshold: 1

If statement on lines 223 to 227:

223:        if (res_n = '0') then 
224:            first_ssp_q <= '0'; 
225:        elsif (rising_edge(clk_sys)) then 
226:            first_ssp_q <= first_ssp_d; 
227:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 224:

224: first_ssp_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 226:

226: first_ssp_q <= first_ssp_d;
Count: 543791678
Threshold: 1

If statement on lines 236 to 238:

236:    sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else 
237:                  '0' when (ssp_enable = '0') else 
238:                  sspc_ena_q;

Count: 22803397
Threshold: 1

Signal assignment statement on line 236:

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else
Count: 3986
Threshold: 1

Signal assignment statement on line 237:

237: '0' when (ssp_enable = '0') else
Count: 22473587
Threshold: 1

Signal assignment statement on line 238:

238: sspc_ena_q;
Count: 325824
Threshold: 1

If statement on lines 242 to 246:

242:        if (res_n = '0') then 
243:            sspc_ena_q <= '0'; 
244:        elsif (rising_edge(clk_sys)) then 
245:            sspc_ena_q <= sspc_ena_d; 
246:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 243:

243: sspc_ena_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 245:

245: sspc_ena_q <= sspc_ena_d;
Count: 543791678
Threshold: 1

If statement on lines 260 to 262:

260:    sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1') 
261:                                                                    else 
262:                      unsigned(btmc_q);

Count: 224354
Threshold: 1

Signal assignment statement on line 260:

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')
Count: 24154
Threshold: 1

Signal assignment statement on line 262:

262: unsigned(btmc_q);
Count: 200200
Threshold: 1

If statement on lines 264 to 265:

264:    sspc_expired <= '1' when (sspc_q >= sspc_threshold) else 
265:                    '0';

Count: 8769888
Threshold: 1

Signal assignment statement on line 264:

264: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else
Count: 162753
Threshold: 1

Signal assignment statement on line 265:

265: '0';
Count: 8607135
Threshold: 1

Signal assignment statement on line 267:

267: sspc_add <= sspc_q + 1;
Count: 8572668
Threshold: 1

If statement on lines 274 to 276:

274:    sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else 
275:                    sspc_add when (sspc_ena_q = '1') else 
276:                      sspc_q;

Count: 17211667
Threshold: 1

Signal assignment statement on line 274:

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else
Count: 382539
Threshold: 1

Signal assignment statement on line 275:

275: sspc_add when (sspc_ena_q = '1') else
Count: 16816841
Threshold: 1

Signal assignment statement on line 276:

276: sspc_q;
Count: 12287
Threshold: 1

If statement on lines 278 to 279:

278:    sspc_ce <= '1' when (sspc_d /= sspc_q) else 
279:               '0';

Count: 17143735
Threshold: 1

Signal assignment statement on line 278:

278: sspc_ce <= '1' when (sspc_d /= sspc_q) else
Count: 8572668
Threshold: 1

Signal assignment statement on line 279:

279: '0';
Count: 8571067
Threshold: 1

If statement on lines 283 to 289:

283:        if (res_n = '0') then 
284:            sspc_q <= C_SSPC_RST_VAL; 
...
288:            end if; 
289:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 284:

284: sspc_q <= C_SSPC_RST_VAL;
Count: 2424883
Threshold: 1

If statement on lines 286 to 288:

286:            if (sspc_ce = '1') then 
287:                sspc_q <= sspc_d; 
288:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 287:

287: sspc_q <= sspc_d;
Count: 8570875
Threshold: 1

If statement on lines 295 to 296:

295:    sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else 
296:                  '0';

Count: 332694
Threshold: 1

Signal assignment statement on line 295:

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else
Count: 160181
Threshold: 1

Signal assignment statement on line 296:

296: '0';
Count: 172513
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 172:

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	85725	1
Bin	False	22765959	1

"if" / "when" / "else" condition on line 173:

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	3986	1
Bin	False	22761973	1

"if" / "when" / "else" condition on line 174:

174: '0' when (tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	11362502	1
Bin	False	11399471	1

"if" / "when" / "else" condition on line 179:

179: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 181:

181: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 192:

192: btmc_d <= (others => '0') when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	31555	1
Bin	False	469168	1

"if" / "when" / "else" condition on line 193:

193: btmc_add when (btmc_meas_running_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	429197	1
Bin	False	39971	1

"if" / "when" / "else" condition on line 198:

198: btmc_ce <= '1' when (btmc_d /= btmc_q) else

	Evaluated to	Count	Threshold
Bin	True	219189	1
Bin	False	220790	1

"if" / "when" / "else" condition on line 203:

203: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 205:

205: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 206:

206: if (btmc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	217085	1
Bin	False	543574593	1

"if" / "when" / "else" condition on line 217:

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	5979	1
Bin	False	23111808	1

"if" / "when" / "else" condition on line 218:

218: '0' when (sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	True	22451459	1
Bin	False	660349	1

"if" / "when" / "else" condition on line 223:

223: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 225:

225: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 236:

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	3986	1
Bin	False	22799411	1

"if" / "when" / "else" condition on line 237:

237: '0' when (ssp_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	22473587	1
Bin	False	325824	1

"if" / "when" / "else" condition on line 242:

242: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 244:

244: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 260:

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')

	Evaluated to	Count	Threshold
Bin	True	24154	1
Bin	False	200200	1

"if" / "when" / "else" condition on line 264:

264: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else

	Evaluated to	Count	Threshold
Bin	True	162753	1
Bin	False	8607135	1

"if" / "when" / "else" condition on line 274:

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	True	382539	1
Bin	False	16829128	1

"if" / "when" / "else" condition on line 275:

275: sspc_add when (sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	16816841	1
Bin	False	12287	1

"if" / "when" / "else" condition on line 278:

278: sspc_ce <= '1' when (sspc_d /= sspc_q) else

	Evaluated to	Count	Threshold
Bin	True	8572668	1
Bin	False	8571067	1

"if" / "when" / "else" condition on line 283:

283: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 285:

285: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 286:

286: if (sspc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	8570875	1
Bin	False	535220803	1

"if" / "when" / "else" condition on line 295:

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	160181	1
Bin	False	172513	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BTMC_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DBT_MEASURE_START

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

GEN_FIRST_SSP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SSP_DELAY

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SSP_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	160181	1
Bin	1	0	161782	1

Signal:

BTMC_D

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	86	1
Bin	(10)	1	0	1687	1
Bin	(9)	0	1	163	1
Bin	(9)	1	0	1764	1
Bin	(8)	0	1	339	1
Bin	(8)	1	0	1940	1
Bin	(7)	0	1	680	1
Bin	(7)	1	0	2281	1
Bin	(6)	0	1	1388	1
Bin	(6)	1	0	2989	1
Bin	(5)	0	1	3552	1
Bin	(5)	1	0	5153	1
Bin	(4)	0	1	6417	1
Bin	(4)	1	0	8018	1
Bin	(3)	0	1	13505	1
Bin	(3)	1	0	15106	1
Bin	(2)	0	1	27382	1
Bin	(2)	1	0	28983	1
Bin	(1)	0	1	53649	1
Bin	(1)	1	0	55250	1
Bin	(0)	0	1	108359	1
Bin	(0)	1	0	109960	1

Signal:

BTMC_Q

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	86	1
Bin	(10)	1	0	1687	1
Bin	(9)	0	1	163	1
Bin	(9)	1	0	1764	1
Bin	(8)	0	1	339	1
Bin	(8)	1	0	1940	1
Bin	(7)	0	1	680	1
Bin	(7)	1	0	2281	1
Bin	(6)	0	1	1388	1
Bin	(6)	1	0	2989	1
Bin	(5)	0	1	3552	1
Bin	(5)	1	0	5153	1
Bin	(4)	0	1	6417	1
Bin	(4)	1	0	8018	1
Bin	(3)	0	1	13505	1
Bin	(3)	1	0	15106	1
Bin	(2)	0	1	27382	1
Bin	(2)	1	0	28983	1
Bin	(1)	0	1	53649	1
Bin	(1)	1	0	55250	1
Bin	(0)	0	1	108359	1
Bin	(0)	1	0	109960	1

Signal:

BTMC_ADD

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	86	1
Bin	(10)	1	0	1687	1
Bin	(9)	0	1	163	1
Bin	(9)	1	0	1764	1
Bin	(8)	0	1	339	1
Bin	(8)	1	0	1940	1
Bin	(7)	0	1	680	1
Bin	(7)	1	0	2281	1
Bin	(6)	0	1	1388	1
Bin	(6)	1	0	2989	1
Bin	(5)	0	1	3552	1
Bin	(5)	1	0	5153	1
Bin	(4)	0	1	6425	1
Bin	(4)	1	0	8026	1
Bin	(3)	0	1	13510	1
Bin	(3)	1	0	15111	1
Bin	(2)	0	1	27389	1
Bin	(2)	1	0	28990	1
Bin	(1)	0	1	54752	1
Bin	(1)	1	0	56353	1
Bin	(0)	0	1	109960	1
Bin	(0)	1	0	108359	1

Signal:

BTMC_CE

	From	To	Count	Threshold
Bin	0	1	219189	1
Bin	1	0	220790	1

Signal:

BTMC_MEAS_RUNNING_D

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

Signal:

BTMC_MEAS_RUNNING_Q

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

Signal:

SSPC_D

	Element	From	To	Count	Threshold
Bin	(14)	0	1	165	1
Bin	(14)	1	0	1766	1
Bin	(13)	0	1	325	1
Bin	(13)	1	0	1926	1
Bin	(12)	0	1	655	1
Bin	(12)	1	0	2256	1
Bin	(11)	0	1	1310	1
Bin	(11)	1	0	2911	1
Bin	(10)	0	1	2820	1
Bin	(10)	1	0	4421	1
Bin	(9)	0	1	5366	1
Bin	(9)	1	0	6967	1
Bin	(8)	0	1	11367	1
Bin	(8)	1	0	12968	1
Bin	(7)	0	1	22476	1
Bin	(7)	1	0	24077	1
Bin	(6)	0	1	46123	1
Bin	(6)	1	0	47724	1
Bin	(5)	0	1	143243	1
Bin	(5)	1	0	144844	1
Bin	(4)	0	1	241494	1
Bin	(4)	1	0	243095	1
Bin	(3)	0	1	528281	1
Bin	(3)	1	0	529882	1
Bin	(2)	0	1	1110735	1
Bin	(2)	1	0	1112336	1
Bin	(1)	0	1	2117804	1
Bin	(1)	1	0	2119405	1
Bin	(0)	0	1	4233765	1
Bin	(0)	1	0	4232164	1

Signal:

SSPC_Q

	Element	From	To	Count	Threshold
Bin	(14)	0	1	165	1
Bin	(14)	1	0	1766	1
Bin	(13)	0	1	325	1
Bin	(13)	1	0	1926	1
Bin	(12)	0	1	655	1
Bin	(12)	1	0	2256	1
Bin	(11)	0	1	1310	1
Bin	(11)	1	0	2911	1
Bin	(10)	0	1	2820	1
Bin	(10)	1	0	4421	1
Bin	(9)	0	1	5366	1
Bin	(9)	1	0	6967	1
Bin	(8)	0	1	11367	1
Bin	(8)	1	0	12968	1
Bin	(7)	0	1	22476	1
Bin	(7)	1	0	24077	1
Bin	(6)	0	1	46123	1
Bin	(6)	1	0	47724	1
Bin	(5)	0	1	143243	1
Bin	(5)	1	0	144844	1
Bin	(4)	0	1	241494	1
Bin	(4)	1	0	243095	1
Bin	(3)	0	1	528281	1
Bin	(3)	1	0	529882	1
Bin	(2)	0	1	1110735	1
Bin	(2)	1	0	1112336	1
Bin	(1)	0	1	2117804	1
Bin	(1)	1	0	2119405	1
Bin	(0)	0	1	4233765	1
Bin	(0)	1	0	4232164	1

Signal:

SSPC_CE

	From	To	Count	Threshold
Bin	0	1	8571067	1
Bin	1	0	8571067	1

Signal:

SSPC_EXPIRED

	From	To	Count	Threshold
Bin	0	1	162753	1
Bin	1	0	162753	1

Signal:

SSPC_THRESHOLD

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	86	1
Bin	(10)	1	0	1687	1
Bin	(9)	0	1	163	1
Bin	(9)	1	0	1764	1
Bin	(8)	0	1	349	1
Bin	(8)	1	0	1950	1
Bin	(7)	0	1	699	1
Bin	(7)	1	0	2300	1
Bin	(6)	0	1	1383	1
Bin	(6)	1	0	2984	1
Bin	(5)	0	1	3518	1
Bin	(5)	1	0	5119	1
Bin	(4)	0	1	6240	1
Bin	(4)	1	0	7841	1
Bin	(3)	0	1	13066	1
Bin	(3)	1	0	14667	1
Bin	(2)	0	1	25658	1
Bin	(2)	1	0	27259	1
Bin	(1)	0	1	48240	1
Bin	(1)	1	0	49841	1
Bin	(0)	0	1	97114	1
Bin	(0)	1	0	98715	1

Signal:

SSPC_ADD

	Element	From	To	Count	Threshold
Bin	(14)	0	1	165	1
Bin	(14)	1	0	1766	1
Bin	(13)	0	1	325	1
Bin	(13)	1	0	1926	1
Bin	(12)	0	1	655	1
Bin	(12)	1	0	2256	1
Bin	(11)	0	1	1310	1
Bin	(11)	1	0	2911	1
Bin	(10)	0	1	2820	1
Bin	(10)	1	0	4421	1
Bin	(9)	0	1	5366	1
Bin	(9)	1	0	6967	1
Bin	(8)	0	1	11368	1
Bin	(8)	1	0	12969	1
Bin	(7)	0	1	22477	1
Bin	(7)	1	0	24078	1
Bin	(6)	0	1	46124	1
Bin	(6)	1	0	47725	1
Bin	(5)	0	1	143249	1
Bin	(5)	1	0	144850	1
Bin	(4)	0	1	242165	1
Bin	(4)	1	0	243766	1
Bin	(3)	0	1	528525	1
Bin	(3)	1	0	530126	1
Bin	(2)	0	1	1111383	1
Bin	(2)	1	0	1112984	1
Bin	(1)	0	1	2117533	1
Bin	(1)	1	0	2115932	1
Bin	(0)	0	1	4232164	1
Bin	(0)	1	0	4233765	1

Signal:

FIRST_SSP_D

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

Signal:

FIRST_SSP_Q

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

Signal:

SSPC_ENA_D

	From	To	Count	Threshold
Bin	0	1	3409	1
Bin	1	0	5010	1

Signal:

SSPC_ENA_Q

	From	To	Count	Threshold
Bin	0	1	1993	1
Bin	1	0	3594	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 172:

btmc_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	22765959	1
Bin	True	85725	1

"and" expression on line 173:

 dbt_measure_start = '1' and tx_trigger = '1' 
 <---------LHS--------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11362502	1
Bin	True	False	3986	1
Bin	True	True	3986	1

"=" expression on line 173:

dbt_measure_start = '1'

	Evaluated to	Count	Threshold
Bin	False	22757987	1
Bin	True	7972	1

"=" expression on line 173:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11399471	1
Bin	True	11366488	1

"=" expression on line 174:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11399471	1
Bin	True	11362502	1

"=" expression on line 179:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 192:

btmc_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	469168	1
Bin	True	31555	1

"=" expression on line 193:

btmc_meas_running_q = '1'

	Evaluated to	Count	Threshold
Bin	False	39971	1
Bin	True	429197	1

"=" expression on line 203:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 206:

btmc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543574593	1
Bin	True	217085	1

"and" expression on line 217:

 gen_first_ssp = '1'and tx_trigger = '1' 
 <-------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11488197	1
Bin	True	False	6503	1
Bin	True	True	5979	1

"=" expression on line 217:

gen_first_ssp = '1'

	Evaluated to	Count	Threshold
Bin	False	23105305	1
Bin	True	12482	1

"=" expression on line 217:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11623611	1
Bin	True	11494176	1

"=" expression on line 218:

sspc_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	660349	1
Bin	True	22451459	1

"=" expression on line 223:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"and" expression on line 236:

 gen_first_ssp = '1' and tx_trigger = '1' 
 <-------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11389084	1
Bin	True	False	3986	1
Bin	True	True	3986	1

"=" expression on line 236:

gen_first_ssp = '1'

	Evaluated to	Count	Threshold
Bin	False	22795425	1
Bin	True	7972	1

"=" expression on line 236:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11410327	1
Bin	True	11393070	1

"=" expression on line 237:

ssp_enable = '0'

	Evaluated to	Count	Threshold
Bin	False	325824	1
Bin	True	22473587	1

"=" expression on line 242:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 260:

first_ssp_q = '1'

	Evaluated to	Count	Threshold
Bin	False	200200	1
Bin	True	24154	1

"or" expression on line 274:

 btmc_reset = '1' or sspc_expired = '1' 
 <-----LHS------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	16829128	1
Bin	False	True	350990	1
Bin	True	False	2974	1

"=" expression on line 274:

btmc_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	17180118	1
Bin	True	31549	1

"=" expression on line 274:

sspc_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	16832102	1
Bin	True	379565	1

"=" expression on line 275:

sspc_ena_q = '1'

	Evaluated to	Count	Threshold
Bin	False	12287	1
Bin	True	16816841	1

"=" expression on line 283:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 286:

sspc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	535220803	1
Bin	True	8570875	1

"and" expression on line 295:

 sspc_expired = '1' and sspc_ena_q = '1' 
 <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	160093	1
Bin	True	False	4653	1
Bin	True	True	160181	1

"=" expression on line 295:

sspc_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	167860	1
Bin	True	164834	1

"=" expression on line 295:

sspc_ena_q = '1'

	Evaluated to	Count	Threshold
Bin	False	12420	1
Bin	True	320274	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SSP_GENERATOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 172 to 175:

Signal assignment statement on line 172:

Signal assignment statement on line 173:

Signal assignment statement on line 174:

Signal assignment statement on line 175:

If statement on lines 179 to 183:

Signal assignment statement on line 180:

Signal assignment statement on line 182:

If statement on lines 192 to 194:

Signal assignment statement on line 192:

Signal assignment statement on line 193:

Signal assignment statement on line 194:

Signal assignment statement on line 196:

If statement on lines 198 to 199:

Signal assignment statement on line 198:

Signal assignment statement on line 199:

If statement on lines 203 to 209:

Signal assignment statement on line 204:

If statement on lines 206 to 208:

Signal assignment statement on line 207:

If statement on lines 217 to 219:

Signal assignment statement on line 217:

Signal assignment statement on line 218:

Signal assignment statement on line 219:

If statement on lines 223 to 227:

Signal assignment statement on line 224:

Signal assignment statement on line 226:

If statement on lines 236 to 238:

Signal assignment statement on line 236:

Signal assignment statement on line 237:

Signal assignment statement on line 238:

If statement on lines 242 to 246:

Signal assignment statement on line 243:

Signal assignment statement on line 245:

If statement on lines 260 to 262:

Signal assignment statement on line 260:

Signal assignment statement on line 262:

If statement on lines 264 to 265:

Signal assignment statement on line 264:

Signal assignment statement on line 265:

Signal assignment statement on line 267:

If statement on lines 274 to 276:

Signal assignment statement on line 274:

Signal assignment statement on line 275:

Signal assignment statement on line 276:

If statement on lines 278 to 279:

Signal assignment statement on line 278:

Signal assignment statement on line 279:

If statement on lines 283 to 289:

Signal assignment statement on line 284:

If statement on lines 286 to 288:

Signal assignment statement on line 287:

If statement on lines 295 to 296:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 172:

"if" / "when" / "else" condition on line 173:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 179:

"if" / "when" / "else" condition on line 181:

"if" / "when" / "else" condition on line 192:

"if" / "when" / "else" condition on line 193:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 203:

"if" / "when" / "else" condition on line 205:

"if" / "when" / "else" condition on line 206:

"if" / "when" / "else" condition on line 217:

"if" / "when" / "else" condition on line 218:

"if" / "when" / "else" condition on line 223: