NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SSP_GENERATOR_INST	100.0 % (55/55)	100.0 % (56/56)	100.0 % (262/262)	100.0 % (65/65)	N.A.	N.A.	100.0 % (438/438)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

172:    btmc_meas_running_d <= '0' when (btmc_reset = '1') else 
173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else 
174:                           '0' when (tx_trigger = '1') else 
175:                           btmc_meas_running_q;

Count: 22157630
Threshold: 1

Signal assignment statement:

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else
Count: 84387
Threshold: 1

Signal assignment statement:

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

Count: 4646
Threshold: 1

Signal assignment statement:

174: '0' when (tx_trigger = '1') else
Count: 11015873
Threshold: 1

Signal assignment statement:

175: btmc_meas_running_q;
Count: 11052724
Threshold: 1

If statement:

179:        if (res_n = '0') then 
180:            btmc_meas_running_q <= '0'; 
181:        elsif (rising_edge(clk_sys)) then 
182:            btmc_meas_running_q <= btmc_meas_running_d; 
183:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

180: btmc_meas_running_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

182: btmc_meas_running_q <= btmc_meas_running_d;
Count: 526374300
Threshold: 1

If statement:

192:    btmc_d <= (others => '0') when (btmc_reset = '1') else 
193:                     btmc_add when (btmc_meas_running_q = '1') else 
194:                       btmc_q;

Count: 503013
Threshold: 1

Signal assignment statement:

192: btmc_d <= (others => '0') when (btmc_reset = '1') else
Count: 31755
Threshold: 1

Signal assignment statement:

193: btmc_add when (btmc_meas_running_q = '1') else
Count: 431065
Threshold: 1

Signal assignment statement:

194: btmc_q;
Count: 40193
Threshold: 1

Signal assignment statement:

196: btmc_add <= std_logic_vector(unsigned(btmc_q) + 1);
Count: 222216
Threshold: 1

If statement:

198:    btmc_ce <= '1' when (btmc_d /= btmc_q) else 
199:               '0';

Count: 442832
Threshold: 1

Signal assignment statement:

198: btmc_ce <= '1' when (btmc_d /= btmc_q) else
Count: 220616
Threshold: 1

Signal assignment statement:

199: '0';
Count: 222216
Threshold: 1

If statement:

203:        if (res_n = '0') then 
204:            btmc_q <= (others => '0'); 
...
208:            end if; 
209:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

204: btmc_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

206:            if (btmc_ce = '1') then 
207:                btmc_q <= btmc_d; 
208:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

207: btmc_q <= btmc_d;
Count: 218506
Threshold: 1

If statement:

217:    first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else 
218:                   '0' when (sspc_expired = '1') else 
219:                   first_ssp_q;

Count: 22485587
Threshold: 1

Signal assignment statement:

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else
Count: 6969
Threshold: 1

Signal assignment statement:

218: '0' when (sspc_expired = '1') else
Count: 21738706
Threshold: 1

Signal assignment statement:

219: first_ssp_q;
Count: 739912
Threshold: 1

If statement:

223:        if (res_n = '0') then 
224:            first_ssp_q <= '0'; 
225:        elsif (rising_edge(clk_sys)) then 
226:            first_ssp_q <= first_ssp_d; 
227:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

224: first_ssp_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

226: first_ssp_q <= first_ssp_d;
Count: 526374300
Threshold: 1

If statement:

236:    sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else 
237:                  '0' when (ssp_enable = '0') else 
238:                  sspc_ena_q;

Count: 22112109
Threshold: 1

Signal assignment statement:

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else
Count: 4646
Threshold: 1

Signal assignment statement:

237: '0' when (ssp_enable = '0') else
Count: 21720194
Threshold: 1

Signal assignment statement:

238: sspc_ena_q;
Count: 387269
Threshold: 1

If statement:

242:        if (res_n = '0') then 
243:            sspc_ena_q <= '0'; 
244:        elsif (rising_edge(clk_sys)) then 
245:            sspc_ena_q <= sspc_ena_d; 
246:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

243: sspc_ena_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

245: sspc_ena_q <= sspc_ena_d;
Count: 526374300
Threshold: 1

If statement:

260:    sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1') 
261:                                                                    else 
262:                      unsigned(btmc_q);

Count: 226103
Threshold: 1

Signal assignment statement:

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')
Count: 25636
Threshold: 1

Signal assignment statement:

262: unsigned(btmc_q);
Count: 200467
Threshold: 1

If statement:

264:    sspc_expired <= '1' when (sspc_q >= sspc_threshold) else 
265:                    '0';

Count: 8976142
Threshold: 1

Signal assignment statement:

264: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else
Count: 193249
Threshold: 1

Signal assignment statement:

265: '0';
Count: 8782893
Threshold: 1

Signal assignment statement:

267: sspc_add <= sspc_q + 1;
Count: 8778647
Threshold: 1

If statement:

274:    sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else 
275:                    sspc_add when (sspc_ena_q = '1') else 
276:                      sspc_q;

Count: 17623721
Threshold: 1

Signal assignment statement:

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else
Count: 442612
Threshold: 1

Signal assignment statement:

275: sspc_add when (sspc_ena_q = '1') else
Count: 17168194
Threshold: 1

Signal assignment statement:

276: sspc_q;
Count: 12915
Threshold: 1

If statement:

278:    sspc_ce <= '1' when (sspc_d /= sspc_q) else 
279:               '0';

Count: 17555694
Threshold: 1

Signal assignment statement:

278: sspc_ce <= '1' when (sspc_d /= sspc_q) else
Count: 8778647
Threshold: 1

Signal assignment statement:

279: '0';
Count: 8777047
Threshold: 1

If statement:

283:        if (res_n = '0') then 
284:            sspc_q <= C_SSPC_RST_VAL; 
...
288:            end if; 
289:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

284: sspc_q <= C_SSPC_RST_VAL;
Count: 2418499
Threshold: 1

If statement:

286:            if (sspc_ce = '1') then 
287:                sspc_q <= sspc_d; 
288:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

287: sspc_q <= sspc_d;
Count: 8776864
Threshold: 1

If statement:

295:    sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else 
296:                  '0';

Count: 394344
Threshold: 1

Signal assignment statement:

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else
Count: 190334
Threshold: 1

Signal assignment statement:

296: '0';
Count: 204010
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	84387	1
Bin	False	22073243	1

"if" / "when" / "else" condition:

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	4646	1
Bin	False	22068597	1

"if" / "when" / "else" condition:

174: '0' when (tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	11015873	1
Bin	False	11052724	1

"if" / "when" / "else" condition:

179: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

181: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

192: btmc_d <= (others => '0') when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	31755	1
Bin	False	471258	1

"if" / "when" / "else" condition:

193: btmc_add when (btmc_meas_running_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	431065	1
Bin	False	40193	1

"if" / "when" / "else" condition:

198: btmc_ce <= '1' when (btmc_d /= btmc_q) else

	Evaluated to	Count	Threshold
Bin	True	220616	1
Bin	False	222216	1

"if" / "when" / "else" condition:

203: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

205: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

206: if (btmc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	218506	1
Bin	False	526155794	1

"if" / "when" / "else" condition:

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	6969	1
Bin	False	22478618	1

"if" / "when" / "else" condition:

218: '0' when (sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	True	21738706	1
Bin	False	739912	1

"if" / "when" / "else" condition:

223: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

225: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	4646	1
Bin	False	22107463	1

"if" / "when" / "else" condition:

237: '0' when (ssp_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	21720194	1
Bin	False	387269	1

"if" / "when" / "else" condition:

242: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

244: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')

	Evaluated to	Count	Threshold
Bin	True	25636	1
Bin	False	200467	1

"if" / "when" / "else" condition:

264: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else

	Evaluated to	Count	Threshold
Bin	True	193249	1
Bin	False	8782893	1

"if" / "when" / "else" condition:

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	True	442612	1
Bin	False	17181109	1

"if" / "when" / "else" condition:

275: sspc_add when (sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	17168194	1
Bin	False	12915	1

"if" / "when" / "else" condition:

278: sspc_ce <= '1' when (sspc_d /= sspc_q) else

	Evaluated to	Count	Threshold
Bin	True	8778647	1
Bin	False	8777047	1

"if" / "when" / "else" condition:

283: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

285: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

286: if (sspc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	8776864	1
Bin	False	517597436	1

"if" / "when" / "else" condition:

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	190334	1
Bin	False	204010	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

BTMC_RESET

	From	To	Count	Threshold
Bin	0	1	28129	1
Bin	1	0	29729	1

Port:

DBT_MEASURE_START

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Port:

GEN_FIRST_SSP

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Port:

SSP_DELAY(8)

	From	To	Count	Threshold
Bin	0	1	11	1
Bin	1	0	1611	1

Port:

SSP_DELAY(7)

	From	To	Count	Threshold
Bin	0	1	32	1
Bin	1	0	1632	1

Port:

SSP_DELAY(6)

	From	To	Count	Threshold
Bin	0	1	42	1
Bin	1	0	1642	1

Port:

SSP_DELAY(5)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1666	1

Port:

SSP_DELAY(4)

	From	To	Count	Threshold
Bin	0	1	57	1
Bin	1	0	1657	1

Port:

SSP_DELAY(3)

	From	To	Count	Threshold
Bin	0	1	268	1
Bin	1	0	1868	1

Port:

SSP_DELAY(2)

	From	To	Count	Threshold
Bin	0	1	931	1
Bin	1	0	2531	1

Port:

SSP_DELAY(1)

	From	To	Count	Threshold
Bin	0	1	239	1
Bin	1	0	1839	1

Port:

SSP_DELAY(0)

	From	To	Count	Threshold
Bin	0	1	908	1
Bin	1	0	2508	1

Port:

SSP_ENABLE

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	190334	1
Bin	1	0	191934	1

Signal:

BTMC_D(14)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

BTMC_D(13)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	1610	1

Signal:

BTMC_D(12)

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1620	1

Signal:

BTMC_D(11)

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	1640	1

Signal:

BTMC_D(10)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1685	1

Signal:

BTMC_D(9)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	1763	1

Signal:

BTMC_D(8)

	From	To	Count	Threshold
Bin	0	1	339	1
Bin	1	0	1939	1

Signal:

BTMC_D(7)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2286	1

Signal:

BTMC_D(6)

	From	To	Count	Threshold
Bin	0	1	1386	1
Bin	1	0	2986	1

Signal:

BTMC_D(5)

	From	To	Count	Threshold
Bin	0	1	3535	1
Bin	1	0	5135	1

Signal:

BTMC_D(4)

	From	To	Count	Threshold
Bin	0	1	6400	1
Bin	1	0	8000	1

Signal:

BTMC_D(3)

	From	To	Count	Threshold
Bin	0	1	13452	1
Bin	1	0	15052	1

Signal:

BTMC_D(2)

	From	To	Count	Threshold
Bin	0	1	27654	1
Bin	1	0	29254	1

Signal:

BTMC_D(1)

	From	To	Count	Threshold
Bin	0	1	53835	1
Bin	1	0	55435	1

Signal:

BTMC_D(0)

	From	To	Count	Threshold
Bin	0	1	109084	1
Bin	1	0	110684	1

Signal:

BTMC_Q(14)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

BTMC_Q(13)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	1610	1

Signal:

BTMC_Q(12)

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1620	1

Signal:

BTMC_Q(11)

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	1640	1

Signal:

BTMC_Q(10)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1685	1

Signal:

BTMC_Q(9)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	1763	1

Signal:

BTMC_Q(8)

	From	To	Count	Threshold
Bin	0	1	339	1
Bin	1	0	1939	1

Signal:

BTMC_Q(7)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2286	1

Signal:

BTMC_Q(6)

	From	To	Count	Threshold
Bin	0	1	1386	1
Bin	1	0	2986	1

Signal:

BTMC_Q(5)

	From	To	Count	Threshold
Bin	0	1	3535	1
Bin	1	0	5135	1

Signal:

BTMC_Q(4)

	From	To	Count	Threshold
Bin	0	1	6400	1
Bin	1	0	8000	1

Signal:

BTMC_Q(3)

	From	To	Count	Threshold
Bin	0	1	13452	1
Bin	1	0	15052	1

Signal:

BTMC_Q(2)

	From	To	Count	Threshold
Bin	0	1	27654	1
Bin	1	0	29254	1

Signal:

BTMC_Q(1)

	From	To	Count	Threshold
Bin	0	1	53835	1
Bin	1	0	55435	1

Signal:

BTMC_Q(0)

	From	To	Count	Threshold
Bin	0	1	109083	1
Bin	1	0	110683	1

Signal:

BTMC_ADD(14)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

BTMC_ADD(13)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	1610	1

Signal:

BTMC_ADD(12)

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1620	1

Signal:

BTMC_ADD(11)

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	1640	1

Signal:

BTMC_ADD(10)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1685	1

Signal:

BTMC_ADD(9)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	1763	1

Signal:

BTMC_ADD(8)

	From	To	Count	Threshold
Bin	0	1	339	1
Bin	1	0	1939	1

Signal:

BTMC_ADD(7)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2286	1

Signal:

BTMC_ADD(6)

	From	To	Count	Threshold
Bin	0	1	1386	1
Bin	1	0	2986	1

Signal:

BTMC_ADD(5)

	From	To	Count	Threshold
Bin	0	1	3535	1
Bin	1	0	5135	1

Signal:

BTMC_ADD(4)

	From	To	Count	Threshold
Bin	0	1	6408	1
Bin	1	0	8008	1

Signal:

BTMC_ADD(3)

	From	To	Count	Threshold
Bin	0	1	13457	1
Bin	1	0	15057	1

Signal:

BTMC_ADD(2)

	From	To	Count	Threshold
Bin	0	1	27661	1
Bin	1	0	29261	1

Signal:

BTMC_ADD(1)

	From	To	Count	Threshold
Bin	0	1	55288	1
Bin	1	0	56888	1

Signal:

BTMC_ADD(0)

	From	To	Count	Threshold
Bin	0	1	110683	1
Bin	1	0	109083	1

Signal:

BTMC_CE

	From	To	Count	Threshold
Bin	0	1	220616	1
Bin	1	0	222216	1

Signal:

BTMC_MEAS_RUNNING_D

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Signal:

BTMC_MEAS_RUNNING_Q

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Signal:

SSPC_D(14)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	1765	1

Signal:

SSPC_D(13)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	1925	1

Signal:

SSPC_D(12)

	From	To	Count	Threshold
Bin	0	1	655	1
Bin	1	0	2255	1

Signal:

SSPC_D(11)

	From	To	Count	Threshold
Bin	0	1	1310	1
Bin	1	0	2910	1

Signal:

SSPC_D(10)

	From	To	Count	Threshold
Bin	0	1	2780	1
Bin	1	0	4380	1

Signal:

SSPC_D(9)

	From	To	Count	Threshold
Bin	0	1	5365	1
Bin	1	0	6965	1

Signal:

SSPC_D(8)

	From	To	Count	Threshold
Bin	0	1	11118	1
Bin	1	0	12718	1

Signal:

SSPC_D(7)

	From	To	Count	Threshold
Bin	0	1	22410	1
Bin	1	0	24010	1

Signal:

SSPC_D(6)

	From	To	Count	Threshold
Bin	0	1	45498	1
Bin	1	0	47098	1

Signal:

SSPC_D(5)

	From	To	Count	Threshold
Bin	0	1	146202	1
Bin	1	0	147802	1

Signal:

SSPC_D(4)

	From	To	Count	Threshold
Bin	0	1	241977	1
Bin	1	0	243577	1

Signal:

SSPC_D(3)

	From	To	Count	Threshold
Bin	0	1	535237	1
Bin	1	0	536837	1

Signal:

SSPC_D(2)

	From	To	Count	Threshold
Bin	0	1	1146717	1
Bin	1	0	1148317	1

Signal:

SSPC_D(1)

	From	To	Count	Threshold
Bin	0	1	2162423	1
Bin	1	0	2164023	1

Signal:

SSPC_D(0)

	From	To	Count	Threshold
Bin	0	1	4323782	1
Bin	1	0	4322182	1

Signal:

SSPC_Q(14)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	1765	1

Signal:

SSPC_Q(13)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	1925	1

Signal:

SSPC_Q(12)

	From	To	Count	Threshold
Bin	0	1	655	1
Bin	1	0	2255	1

Signal:

SSPC_Q(11)

	From	To	Count	Threshold
Bin	0	1	1310	1
Bin	1	0	2910	1

Signal:

SSPC_Q(10)

	From	To	Count	Threshold
Bin	0	1	2780	1
Bin	1	0	4380	1

Signal:

SSPC_Q(9)

	From	To	Count	Threshold
Bin	0	1	5365	1
Bin	1	0	6965	1

Signal:

SSPC_Q(8)

	From	To	Count	Threshold
Bin	0	1	11118	1
Bin	1	0	12718	1

Signal:

SSPC_Q(7)

	From	To	Count	Threshold
Bin	0	1	22410	1
Bin	1	0	24010	1

Signal:

SSPC_Q(6)

	From	To	Count	Threshold
Bin	0	1	45498	1
Bin	1	0	47098	1

Signal:

SSPC_Q(5)

	From	To	Count	Threshold
Bin	0	1	146202	1
Bin	1	0	147802	1

Signal:

SSPC_Q(4)

	From	To	Count	Threshold
Bin	0	1	241977	1
Bin	1	0	243577	1

Signal:

SSPC_Q(3)

	From	To	Count	Threshold
Bin	0	1	535237	1
Bin	1	0	536837	1

Signal:

SSPC_Q(2)

	From	To	Count	Threshold
Bin	0	1	1146717	1
Bin	1	0	1148317	1

Signal:

SSPC_Q(1)

	From	To	Count	Threshold
Bin	0	1	2162423	1
Bin	1	0	2164023	1

Signal:

SSPC_Q(0)

	From	To	Count	Threshold
Bin	0	1	4323782	1
Bin	1	0	4322182	1

Signal:

SSPC_CE

	From	To	Count	Threshold
Bin	0	1	8777047	1
Bin	1	0	8777047	1

Signal:

SSPC_EXPIRED

	From	To	Count	Threshold
Bin	0	1	193249	1
Bin	1	0	193249	1

Signal:

SSPC_THRESHOLD(14)

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Signal:

SSPC_THRESHOLD(13)

	From	To	Count	Threshold
Bin	0	1	10	1
Bin	1	0	1610	1

Signal:

SSPC_THRESHOLD(12)

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1620	1

Signal:

SSPC_THRESHOLD(11)

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	1640	1

Signal:

SSPC_THRESHOLD(10)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1685	1

Signal:

SSPC_THRESHOLD(9)

	From	To	Count	Threshold
Bin	0	1	163	1
Bin	1	0	1763	1

Signal:

SSPC_THRESHOLD(8)

	From	To	Count	Threshold
Bin	0	1	349	1
Bin	1	0	1949	1

Signal:

SSPC_THRESHOLD(7)

	From	To	Count	Threshold
Bin	0	1	705	1
Bin	1	0	2305	1

Signal:

SSPC_THRESHOLD(6)

	From	To	Count	Threshold
Bin	0	1	1383	1
Bin	1	0	2983	1

Signal:

SSPC_THRESHOLD(5)

	From	To	Count	Threshold
Bin	0	1	3504	1
Bin	1	0	5104	1

Signal:

SSPC_THRESHOLD(4)

	From	To	Count	Threshold
Bin	0	1	6230	1
Bin	1	0	7830	1

Signal:

SSPC_THRESHOLD(3)

	From	To	Count	Threshold
Bin	0	1	13031	1
Bin	1	0	14631	1

Signal:

SSPC_THRESHOLD(2)

	From	To	Count	Threshold
Bin	0	1	25991	1
Bin	1	0	27591	1

Signal:

SSPC_THRESHOLD(1)

	From	To	Count	Threshold
Bin	0	1	48221	1
Bin	1	0	49821	1

Signal:

SSPC_THRESHOLD(0)

	From	To	Count	Threshold
Bin	0	1	97331	1
Bin	1	0	98931	1

Signal:

SSPC_ADD(14)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	1765	1

Signal:

SSPC_ADD(13)

	From	To	Count	Threshold
Bin	0	1	325	1
Bin	1	0	1925	1

Signal:

SSPC_ADD(12)

	From	To	Count	Threshold
Bin	0	1	655	1
Bin	1	0	2255	1

Signal:

SSPC_ADD(11)

	From	To	Count	Threshold
Bin	0	1	1310	1
Bin	1	0	2910	1

Signal:

SSPC_ADD(10)

	From	To	Count	Threshold
Bin	0	1	2780	1
Bin	1	0	4380	1

Signal:

SSPC_ADD(9)

	From	To	Count	Threshold
Bin	0	1	5365	1
Bin	1	0	6965	1

Signal:

SSPC_ADD(8)

	From	To	Count	Threshold
Bin	0	1	11118	1
Bin	1	0	12718	1

Signal:

SSPC_ADD(7)

	From	To	Count	Threshold
Bin	0	1	22411	1
Bin	1	0	24011	1

Signal:

SSPC_ADD(6)

	From	To	Count	Threshold
Bin	0	1	45498	1
Bin	1	0	47098	1

Signal:

SSPC_ADD(5)

	From	To	Count	Threshold
Bin	0	1	146207	1
Bin	1	0	147807	1

Signal:

SSPC_ADD(4)

	From	To	Count	Threshold
Bin	0	1	242749	1
Bin	1	0	244349	1

Signal:

SSPC_ADD(3)

	From	To	Count	Threshold
Bin	0	1	535466	1
Bin	1	0	537066	1

Signal:

SSPC_ADD(2)

	From	To	Count	Threshold
Bin	0	1	1147225	1
Bin	1	0	1148825	1

Signal:

SSPC_ADD(1)

	From	To	Count	Threshold
Bin	0	1	2162874	1
Bin	1	0	2161274	1

Signal:

SSPC_ADD(0)

	From	To	Count	Threshold
Bin	0	1	4322182	1
Bin	1	0	4323782	1

Signal:

FIRST_SSP_D

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Signal:

FIRST_SSP_Q

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Signal:

SSPC_ENA_D

	From	To	Count	Threshold
Bin	0	1	4181	1
Bin	1	0	5781	1

Signal:

SSPC_ENA_Q

	From	To	Count	Threshold
Bin	0	1	2323	1
Bin	1	0	3923	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	False	22073243	1
Bin	True	84387	1

"=" expression

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	22063951	1
Bin	True	9292	1

"=" expression

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	11052724	1
Bin	True	11020519	1

"and" expression

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else 
                                         <---------LHS--------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11015873	1
Bin	True	False	4646	1
Bin	True	True	4646	1

"=" expression

174: '0' when (tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	11052724	1
Bin	True	11015873	1

"=" expression

179: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

192: btmc_d <= (others => '0') when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	False	471258	1
Bin	True	31755	1

"=" expression

193: btmc_add when (btmc_meas_running_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	40193	1
Bin	True	431065	1

"=" expression

203: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

206: if (btmc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526155794	1
Bin	True	218506	1

"=" expression

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	22471539	1
Bin	True	14048	1

"=" expression

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	11310316	1
Bin	True	11175271	1

"and" expression

217:    first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else 
                                 <-------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11168302	1
Bin	True	False	7079	1
Bin	True	True	6969	1

"=" expression

218: '0' when (sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	False	739912	1
Bin	True	21738706	1

"=" expression

223: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	22102817	1
Bin	True	9292	1

"=" expression

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	11065783	1
Bin	True	11046326	1

"and" expression

236:    sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else 
                                <-------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11041680	1
Bin	True	False	4646	1
Bin	True	True	4646	1

"=" expression

237: '0' when (ssp_enable = '0') else

	Evaluated to	Count	Threshold
Bin	False	387269	1
Bin	True	21720194	1

"=" expression

242: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')

	Evaluated to	Count	Threshold
Bin	False	200467	1
Bin	True	25636	1

"=" expression

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	False	17592323	1
Bin	True	31398	1

"=" expression

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	False	17184378	1
Bin	True	439343	1

"or" expression

274:    sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else 
                                       <-----LHS------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	17181109	1
Bin	False	True	411214	1
Bin	True	False	3269	1

"=" expression

275: sspc_add when (sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	12915	1
Bin	True	17168194	1

"=" expression

283: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

286: if (sspc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	517597436	1
Bin	True	8776864	1

"=" expression

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	198675	1
Bin	True	195669	1

"=" expression

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	13773	1
Bin	True	380571	1

"and" expression

295:    sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else 
                                <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	190237	1
Bin	True	False	5335	1
Bin	True	True	190334	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SSP_GENERATOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/ssp_generator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

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Signal assignment statement:

Signal assignment statement:

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If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

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Signal assignment statement:

Signal assignment statement:

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If statement:

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Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition: