Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage:
PSL cover point on line 158:
158: -- cover {data_overrun_i = '1' and data_overrun_flg = '1'};
Count: 24256
Threshold: 1
PSL cover point on lines 161 to 162:
161: -- cover {read_increment = '1' and read_counter_q = "00001" and commit_rx_frame = '1'}
162: -- report "RX Buffer Commit and Frame read finish - Simultaneous!";
Count: 5
Threshold: 1
PSL cover point on line 165:
165: -- cover {write_raw_intent = '1' and read_increment = '1'};
Count: 54
Threshold: 1
PSL cover point on line 168:
168: -- cover {write_raw_intent = '1'; read_increment = '1'};
Count: 39
Threshold: 1
PSL cover point on line 171:
171: -- cover {read_increment = '1'; write_raw_intent = '1'};
Count: 63
Threshold: 1
PSL cover point on line 174:
174: -- cover {mr_rx_settings_rtsop = RTS_BEG and commit_rx_frame = '1'};
Count: 10
Threshold: 1
PSL cover point on line 177:
177: -- cover {mr_rx_settings_rtsop = RTS_END and commit_rx_frame = '1'};
Count: 13348
Threshold: 1
PSL cover point on line 180:
180: -- cover {(read_increment = '1')[*4]};
Count: 12068
Threshold: 1
PSL cover point on line 183:
183: -- cover {(read_increment = '1')[*16]};
Count: 1781
Threshold: 1
PSL cover point on line 193:
193: -- cover {rec_is_rtr = '1' and commit_rx_frame = '1'};
Count: 5706
Threshold: 1
PSL cover point on line 196:
196: -- cover {rec_dlc = "0000" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 1789
Threshold: 1
PSL cover point on line 199:
199: -- cover {rec_dlc = "0001" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 1225
Threshold: 1
PSL cover point on line 202:
202: -- cover {rec_dlc = "0010" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 492
Threshold: 1
PSL cover point on line 205:
205: -- cover {rec_dlc = "0011" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 568
Threshold: 1
PSL cover point on line 208:
208: -- cover {rec_dlc = "0100" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 703
Threshold: 1
PSL cover point on line 211:
211: -- cover {rec_dlc = "0101" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 280
Threshold: 1
PSL cover point on line 214:
214: -- cover {rec_dlc = "1000" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 662
Threshold: 1
PSL cover point on line 217:
217: -- cover {rec_dlc = "1111" and rec_is_rtr = '0' and commit_rx_frame = '1'};
Count: 304
Threshold: 1
PSL cover point on line 225:
225: -- cover {rx_parity_error = '1'; rx_parity_error = '0' and mr_command_crxpe = '1'};
Count: 9
Threshold: 1
PSL cover point on line 233:
233: -- cover {to_integer(unsigned(rx_mem_free_raw)) = 0};
Count: 58943
Threshold: 1
PSL cover point on line 236:
236: -- cover {to_integer(unsigned(rx_mem_free_raw)) = G_RX_BUFF_SIZE};
Count: 403335406
Threshold: 1
PSL cover point on line 239:
239: -- cover {to_integer(unsigned(rx_mem_free_i)) = 0};
Count: 39864
Threshold: 1
PSL cover point on line 242:
242: -- cover {to_integer(unsigned(rx_mem_free_i)) = G_RX_BUFF_SIZE};
Count: 507727813
Threshold: 1