NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_RX_BUFFER_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_rx_buffer.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_RX_BUFFER_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (23/23) 100.0 % (25/25)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin015275788681
Bin105275804601

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

158:    --      cover {data_overrun_i = '1' and data_overrun_flg = '1'}; 
Count: 23073
Threshold: 1

PSL cover point:

161:    --      cover {read_increment = '1' and read_counter_q = "00001" and commit_rx_frame = '1'} 
162:    --      report "RX Buffer Commit and Frame read finish - Simultaneous!"; 
Count: 7
Threshold: 1

PSL cover point:

165:    --      cover {write_raw_intent = '1' and read_increment = '1'}; 
Count: 56
Threshold: 1

PSL cover point:

168:    --      cover {write_raw_intent = '1'; read_increment = '1'}; 
Count: 42
Threshold: 1

PSL cover point:

171:    --      cover {read_increment = '1'; write_raw_intent = '1'}; 
Count: 65
Threshold: 1

PSL cover point:

174:    --      cover {mr_rx_settings_rtsop = RTS_BEG and commit_rx_frame = '1'}; 
Count: 10
Threshold: 1

PSL cover point:

177:    --      cover {mr_rx_settings_rtsop = RTS_END and commit_rx_frame = '1'}; 
Count: 13300
Threshold: 1

PSL cover point:

180:    --      cover {(read_increment = '1')[*4]}; 
Count: 12147
Threshold: 1

PSL cover point:

183:    --      cover {(read_increment = '1')[*16]}; 
Count: 1798
Threshold: 1

PSL cover point:

193:    --      cover {rec_is_rtr = '1' and commit_rx_frame = '1'}; 
Count: 5803
Threshold: 1

PSL cover point:

196:    --      cover {rec_dlc = "0000" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 1880
Threshold: 1

PSL cover point:

199:    --      cover {rec_dlc = "0001" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 1266
Threshold: 1

PSL cover point:

202:    --      cover {rec_dlc = "0010" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 475
Threshold: 1

PSL cover point:

205:    --      cover {rec_dlc = "0011" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 385
Threshold: 1

PSL cover point:

208:    --      cover {rec_dlc = "0100" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 447
Threshold: 1

PSL cover point:

211:    --      cover {rec_dlc = "0101" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 291
Threshold: 1

PSL cover point:

214:    --      cover {rec_dlc = "1000" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 840
Threshold: 1

PSL cover point:

217:    --      cover {rec_dlc = "1111" and rec_is_rtr = '0' and commit_rx_frame = '1'}; 
Count: 308
Threshold: 1

PSL cover point:

225:    --      cover {rx_parity_error = '1'; rx_parity_error = '0' and mr_command_crxpe = '1'}; 
Count: 15
Threshold: 1

PSL cover point:

233:    --      cover {to_integer(unsigned(rx_mem_free_raw)) = 0}; 
Count: 54044
Threshold: 1

PSL cover point:

236:    --      cover {to_integer(unsigned(rx_mem_free_raw)) = G_RX_BUFF_SIZE}; 
Count: 385730476
Threshold: 1

PSL cover point:

239:    --      cover {to_integer(unsigned(rx_mem_free_i)) = 0}; 
Count: 36048
Threshold: 1

PSL cover point:

242:    --      cover {to_integer(unsigned(rx_mem_free_i)) = G_RX_BUFF_SIZE}; 
Count: 490679743
Threshold: 1