NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 82114
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 82114
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 2627648
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 82114
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	23026	1
Bin	1	0	19720	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	14127	1
Bin	1	0	19724	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	18318	1
Bin	1	0	14985	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	21001	1
Bin	1	0	26617	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	21076	1
Bin	1	0	17724	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	21046	1
Bin	1	0	26684	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	25694	1
Bin	1	0	22308	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	19889	1
Bin	1	0	23946	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	25293	1
Bin	1	0	21916	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	17027	1
Bin	1	0	22558	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	21140	1
Bin	1	0	17751	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	20889	1
Bin	1	0	26437	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	22027	1
Bin	1	0	18675	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	22710	1
Bin	1	0	28198	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	26224	1
Bin	1	0	22806	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	17397	1
Bin	1	0	22840	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	25938	1
Bin	1	0	22520	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	17782	1
Bin	1	0	23268	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	23162	1
Bin	1	0	18892	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	25294	1
Bin	1	0	30035	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	26130	1
Bin	1	0	21463	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	22393	1
Bin	1	0	27912	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	27424	1
Bin	1	0	23718	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	18114	1
Bin	1	0	23588	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	28001	1
Bin	1	0	23929	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	18924	1
Bin	1	0	23771	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	24193	1
Bin	1	0	20474	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	22565	1
Bin	1	0	27902	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	23349	1
Bin	1	0	19500	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	23031	1
Bin	1	0	28206	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	27849	1
Bin	1	0	24050	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	18902	1
Bin	1	0	24021	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	15471	1
Bin	1	0	10608	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	446698	1
Bin	'0'	'1'	463708	1
Bin	'1'	'0'	1031239	1
Bin	'1'	'1'	479859	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: