NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SAMPLE_MUX_INST	100.0 % (11/11)	100.0 % (10/10)	100.0 % (24/24)	100.0 % (6/6)	N.A.	N.A.	100.0 % (51/51)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SAMPLE_MUX_INST

100.0 % (11/11)

100.0 % (10/10)

100.0 % (24/24)

100.0 % (6/6)

N.A.

100.0 % (51/51)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 139 to 140:

139:    sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else 
140:              rx_trigger;

Count: 45840611
Threshold: 1

Signal assignment statement on line 139:

139: sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else
Count: 861561
Threshold: 1

Signal assignment statement on line 140:

140: rx_trigger;
Count: 44979050
Threshold: 1

If statement on lines 145 to 146:

145:    prev_sample_d <= data_rx_synced when (sample = '1') else 
146:                     prev_sample_q;

Count: 50829236
Threshold: 1

Signal assignment statement on line 145:

145: prev_sample_d <= data_rx_synced when (sample = '1') else
Count: 25403115
Threshold: 1

Signal assignment statement on line 146:

146: prev_sample_q;
Count: 25426121
Threshold: 1

If statement on lines 150 to 156:

150:        if (res_n = '0') then 
151:            prev_sample_q <= RECESSIVE; 
...
155:            end if; 
156:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 151:

151: prev_sample_q <= RECESSIVE;
Count: 2424883
Threshold: 1

If statement on lines 153 to 155:

153:            if (mr_settings_ena = '1') then 
154:                prev_sample_q <= prev_sample_d; 
155:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 154:

154: prev_sample_q <= prev_sample_d;
Count: 543786837
Threshold: 1

Signal assignment statement on line 162:

162: prev_sample <= prev_sample_q;
Count: 2784450
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 139:

139: sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	861561	1
Bin	False	44979050	1

"if" / "when" / "else" condition on line 145:

145: prev_sample_d <= data_rx_synced when (sample = '1') else

	Evaluated to	Count	Threshold
Bin	True	25403115	1
Bin	False	25426121	1

"if" / "when" / "else" condition on line 150:

150: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 152:

152: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 153:

153: if (mr_settings_ena = '1') then

	Evaluated to	Count	Threshold
Bin	True	543786837	1
Bin	False	4841	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SAMPLE_SEC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_RX_SYNCED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

PREV_SAMPLE

	From	To	Count	Threshold
Bin	0	1	1392225	1
Bin	1	0	1390624	1

Signal:

SAMPLE

	From	To	Count	Threshold
Bin	0	1	22620865	1
Bin	1	0	22622466	1

Signal:

PREV_SAMPLE_D

	From	To	Count	Threshold
Bin	0	1	2445552	1
Bin	1	0	2443951	1

Signal:

PREV_SAMPLE_Q

	From	To	Count	Threshold
Bin	0	1	1392225	1
Bin	1	0	1390624	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 145:

sample = '1'

	Evaluated to	Count	Threshold
Bin	False	25426121	1
Bin	True	25403115	1

"=" expression on line 150:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 153:

mr_settings_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	4841	1
Bin	True	543786837	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SAMPLE_MUX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 139 to 140:

Signal assignment statement on line 139:

Signal assignment statement on line 140:

If statement on lines 145 to 146:

Signal assignment statement on line 145:

Signal assignment statement on line 146:

If statement on lines 150 to 156:

Signal assignment statement on line 151:

If statement on lines 153 to 155:

Signal assignment statement on line 154:

Signal assignment statement on line 162:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 139:

"if" / "when" / "else" condition on line 145:

"if" / "when" / "else" condition on line 150:

"if" / "when" / "else" condition on line 152:

"if" / "when" / "else" condition on line 153:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 145:

"=" expression on line 150:

"=" expression on line 153:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: