NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SAMPLE_MUX_INST	100.0 % (10/10)	100.0 % (10/10)	100.0 % (24/24)	100.0 % (6/6)	N.A.	N.A.	100.0 % (50/50)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

139:    sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else 
140:              rx_trigger;

Count: 44485134
Threshold: 1

Signal assignment statement:

139: sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else
Count: 1015649
Threshold: 1

Signal assignment statement:

140: rx_trigger;
Count: 43469485
Threshold: 1

If statement:

145:    prev_sample_d <= data_rx_synced when (sample = '1') else 
146:                     prev_sample_q;

Count: 49374293
Threshold: 1

Signal assignment statement:

145: prev_sample_d <= data_rx_synced when (sample = '1') else
Count: 24675689
Threshold: 1

Signal assignment statement:

146: prev_sample_q;
Count: 24698604
Threshold: 1

If statement:

150:        if (res_n = '0') then 
151:            prev_sample_q <= RECESSIVE; 
...
155:            end if; 
156:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

151: prev_sample_q <= RECESSIVE;
Count: 2418499
Threshold: 1

If statement:

153:            if (mr_settings_ena = '1') then 
154:                prev_sample_q <= prev_sample_d; 
155:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

154: prev_sample_q <= prev_sample_d;
Count: 526369460
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

139: sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	1015649	1
Bin	False	43469485	1

"if" / "when" / "else" condition:

145: prev_sample_d <= data_rx_synced when (sample = '1') else

	Evaluated to	Count	Threshold
Bin	True	24675689	1
Bin	False	24698604	1

"if" / "when" / "else" condition:

150: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

152: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

153: if (mr_settings_ena = '1') then

	Evaluated to	Count	Threshold
Bin	True	526369460	1
Bin	False	4840	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SP_CONTROL(1)

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

SP_CONTROL(0)

	From	To	Count	Threshold
Bin	0	1	25548	1
Bin	1	0	27148	1

Port:

RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	22084127	1
Bin	1	0	22085727	1

Port:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	190334	1
Bin	1	0	191934	1

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

DATA_RX_SYNCED

	From	To	Count	Threshold
Bin	0	1	1400896	1
Bin	1	0	1399296	1

Port:

PREV_SAMPLE

	From	To	Count	Threshold
Bin	0	1	1390558	1
Bin	1	0	1388958	1

Signal:

SAMPLE

	From	To	Count	Threshold
Bin	0	1	21896666	1
Bin	1	0	21898266	1

Signal:

PREV_SAMPLE_D

	From	To	Count	Threshold
Bin	0	1	2430639	1
Bin	1	0	2429039	1

Signal:

PREV_SAMPLE_Q

	From	To	Count	Threshold
Bin	0	1	1390558	1
Bin	1	0	1388958	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

145: prev_sample_d <= data_rx_synced when (sample = '1') else

	Evaluated to	Count	Threshold
Bin	False	24698604	1
Bin	True	24675689	1

"=" expression

150: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

153: if (mr_settings_ena = '1') then

	Evaluated to	Count	Threshold
Bin	False	4840	1
Bin	True	526369460	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.BUS_SAMPLING_INST.SAMPLE_MUX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/sample_mux.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: