NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.TX_COMMAND_TXB7_REG_COMP.BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.TX_COMMAND_TXB7_REG_COMP.BIT_GEN(0)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 149 to 155:

149:            if (res_n = '0') then 
150:                reg_value_r(i)  <= reset_value_i(i); 
...
154:                end if; 
155:            end if;

Count: 62750112
Threshold: 1

Signal assignment statement on line 150:

150: reg_value_r(i) <= reset_value_i(i);
Count: 17945
Threshold: 1

If statement on lines 152 to 154:

152:                if (wr_en = '1') then 
153:                    reg_value_r(i)  <= data_in(i); 
154:                end if;

Count: 31360647
Threshold: 1

Signal assignment statement on line 153:

153: reg_value_r(i) <= data_in(i);
Count: 23475
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 149:

149: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	17945	1
Bin	False	62732167	1

"if" / "when" / "else" condition on line 151:

151: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	31360647	1
Bin	False	31371520	1

"if" / "when" / "else" condition on line 152:

152: if (wr_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	23475	1
Bin	False	31337172	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 149:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	62732167	1
Bin	True	17945	1

"=" expression on line 152:

wr_en = '1'

	Evaluated to	Count	Threshold
Bin	False	31337172	1
Bin	True	23475	1