NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_SEGMENT_METER_DBT_INST	100.0 % (66/66)	100.0 % (48/48)	100.0 % (90/90)	100.0 % (161/161)	N.A.	N.A.	100.0 % (365/365)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

273:        if (a > b) then 
274:            return a; 
275:        else 
276:            return b; 
277:        end if;

Count: 16000
Threshold: 1

Sequential statement:

274: return a;
Count: 12800
Threshold: 1

Sequential statement:

276: return b;
Count: 3200
Threshold: 1

If statement:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 
354:                 '0';

Count: 66378703
Threshold: 1

Signal assignment statement:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

Count: 33253239
Threshold: 1

Signal assignment statement:

354: '0';
Count: 33125464
Threshold: 1

If statement:

356:    basic_segm_length <= 
357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
358:        resize(unsigned(tseg_2), C_BS_WIDTH);

Count: 66263184
Threshold: 1

Signal assignment statement:

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else
Count: 33123577
Threshold: 1

Signal assignment statement:

358: resize(unsigned(tseg_2), C_BS_WIDTH);
Count: 33139607
Threshold: 1

If statement:

360:    segm_extension <= 
361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 
363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
364:        resize(unsigned(segm_counter), C_EXT_WIDTH);

Count: 103839869
Threshold: 1

Signal assignment statement:

361: to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or
Count: 69364
Threshold: 1

Signal assignment statement:

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else
Count: 59414391
Threshold: 1

Signal assignment statement:

364: resize(unsigned(segm_counter), C_EXT_WIDTH);
Count: 44356114
Threshold: 1

Signal assignment statement:

366:    segm_ext_add <= resize(basic_segm_length, C_EXP_WIDTH) + 
367:                    resize(segm_extension, C_EXP_WIDTH);

Count: 113264757
Threshold: 1

Signal assignment statement:

369:    segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) - 
370:                    resize(segm_extension, C_EXP_WIDTH);

Count: 113264757
Threshold: 1

If statement:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 
374:                                     else 
375:                        segm_ext_add;

Count: 135457309
Threshold: 1

Signal assignment statement:

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or
Count: 62465834
Threshold: 1

Signal assignment statement:

375: segm_ext_add;
Count: 72991475
Threshold: 1

If statement:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 
387:                                 else 
388:                             '0';

Count: 44301949
Threshold: 1

Signal assignment statement:

384: use_basic_segm_length <= '1' when (start_edge = '1') or
Count: 22085587
Threshold: 1

Signal assignment statement:

388: '0';
Count: 22216362
Threshold: 1

If statement:

395:    exp_seg_length_d <= 
396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
397:                                               else 
398:        resize(sync_segm_length, C_EXP_WIDTH);

Count: 232187368
Threshold: 1

Signal assignment statement:

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')
Count: 127100972
Threshold: 1

Signal assignment statement:

398: resize(sync_segm_length, C_EXP_WIDTH);
Count: 105086396
Threshold: 1

If statement:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 
402:                             else 
403:                         '0';

Count: 45877697
Threshold: 1

Signal assignment statement:

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or
Count: 23445037
Threshold: 1

Signal assignment statement:

403: '0';
Count: 22432660
Threshold: 1

If statement:

407:        if (res_n = '0') then 
408:            exp_seg_length_q <= (others => '1'); 
...
412:            end if; 
413:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

408: exp_seg_length_q <= (others => '1');
Count: 2418499
Threshold: 1

If statement:

410:            if (exp_seg_length_ce = '1') then 
411:                exp_seg_length_q <= exp_seg_length_d; 
412:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

411: exp_seg_length_q <= exp_seg_length_d;
Count: 22820611
Threshold: 1

Signal assignment statement:

425:    neg_phase_err  <= resize(unsigned(tseg_2), C_E_WIDTH) - 
426:                      resize(unsigned(segm_counter), C_E_WIDTH);

Count: 93219169
Threshold: 1

If statement:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
429:                 resize(unsigned(segm_counter), C_E_WIDTH);

Count: 198459496
Threshold: 1

Signal assignment statement:

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else
Count: 68185836
Threshold: 1

Signal assignment statement:

429: resize(unsigned(segm_counter), C_E_WIDTH);
Count: 130273660
Threshold: 1

If statement:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
433:                            else 
434:                        '0';

Count: 110205909
Threshold: 1

Signal assignment statement:

431: phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) >
Count: 59332127
Threshold: 1

Signal assignment statement:

434: '0';
Count: 50873782
Threshold: 1

If statement:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
438:                            else 
439:                        '0';

Count: 110205909
Threshold: 1

Signal assignment statement:

436: phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
Count: 13191740
Threshold: 1

Signal assignment statement:

439: '0';
Count: 97014169
Threshold: 1

If statement:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 
444:                                else 
445:                            '0';

Count: 110205909
Threshold: 1

Signal assignment statement:

441: phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) =
Count: 6276773
Threshold: 1

Signal assignment statement:

445: '0';
Count: 103929136
Threshold: 1

If statement:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
448:                   '0';

Count: 5736
Threshold: 1

Signal assignment statement:

447: sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else
Count: 3898
Threshold: 1

Signal assignment statement:

448: '0';
Count: 1838
Threshold: 1

If statement:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 
460:                              else 
461:                          '0';

Count: 40265812
Threshold: 1

Signal assignment statement:

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and
Count: 7806
Threshold: 1

Signal assignment statement:

461: '0';
Count: 40258006
Threshold: 1

If statement:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
469:                                     else 
470:                                 '0';

Count: 12572334
Threshold: 1

Signal assignment statement:

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')
Count: 7609
Threshold: 1

Signal assignment statement:

470: '0';
Count: 12564725
Threshold: 1

If statement:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 
477:                             else 
478:                         '0';

Count: 115319946
Threshold: 1

Signal assignment statement:

475: exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >=
Count: 17330145
Threshold: 1

Signal assignment statement:

478: '0';
Count: 97989801
Threshold: 1

If statement:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 
488:                                    else 
489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
490:                                    else 
491:                                '0';

Count: 38721814
Threshold: 1

Signal assignment statement:

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and
Count: 620040
Threshold: 1

Signal assignment statement:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

Count: 5078811
Threshold: 1

Signal assignment statement:

491: '0';
Count: 33022963
Threshold: 1

If statement:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
497:                                   else 
498:                               '0';

Count: 37134620
Threshold: 1

Signal assignment statement:

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')
Count: 9991666
Threshold: 1

Signal assignment statement:

498: '0';
Count: 27142954
Threshold: 1

If statement:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
509:                         else 
510:                     '0';

Count: 25112352
Threshold: 1

Signal assignment statement:

507: exit_segm_req <= '1' when (exit_ph2_immediate = '1') or
Count: 15078254
Threshold: 1

Signal assignment statement:

510: '0';
Count: 10034098
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

273: if (a > b) then

	Evaluated to	Count	Threshold
Bin	True	12800	1
Bin	False	3200	1

"if" / "when" / "else" condition:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	True	33253239	1
Bin	False	33125464	1

"if" / "when" / "else" condition:

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	True	33123577	1
Bin	False	33139607	1

"if" / "when" / "else" condition:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	True	69364	1
Bin	False	103770505	1

"if" / "when" / "else" condition:

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else

	Evaluated to	Count	Threshold
Bin	True	59414391	1
Bin	False	44356114	1

"if" / "when" / "else" condition:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1')

	Evaluated to	Count	Threshold
Bin	True	62465834	1
Bin	False	72991475	1

"if" / "when" / "else" condition:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	Evaluated to	Count	Threshold
Bin	True	22085587	1
Bin	False	22216362	1

"if" / "when" / "else" condition:

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')

	Evaluated to	Count	Threshold
Bin	True	127100972	1
Bin	False	105086396	1

"if" / "when" / "else" condition:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	True	23445037	1
Bin	False	22432660	1

"if" / "when" / "else" condition:

407: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

409: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

410: if (exp_seg_length_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	22820611	1
Bin	False	503553689	1

"if" / "when" / "else" condition:

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	True	68185836	1
Bin	False	130273660	1

"if" / "when" / "else" condition:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	59332127	1
Bin	False	50873782	1

"if" / "when" / "else" condition:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	13191740	1
Bin	False	97014169	1

"if" / "when" / "else" condition:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH)))

	Evaluated to	Count	Threshold
Bin	True	6276773	1
Bin	False	103929136	1

"if" / "when" / "else" condition:

447: sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else

	Evaluated to	Count	Threshold
Bin	True	3898	1
Bin	False	1838	1

"if" / "when" / "else" condition:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	7806	1
Bin	False	40258006	1

"if" / "when" / "else" condition:

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	True	7609	1
Bin	False	12564725	1

"if" / "when" / "else" condition:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH))

	Evaluated to	Count	Threshold
Bin	True	17330145	1
Bin	False	97989801	1

"if" / "when" / "else" condition:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1')

	Evaluated to	Count	Threshold
Bin	True	620040	1
Bin	False	38101774	1

"if" / "when" / "else" condition:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	True	5078811	1
Bin	False	33022963	1

"if" / "when" / "else" condition:

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	True	9991666	1
Bin	False	27142954	1

"if" / "when" / "else" condition:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	True	15078254	1
Bin	False	10034098	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

RESYNC_EDGE_VALID

	From	To	Count	Threshold
Bin	0	1	795345	1
Bin	1	0	796945	1

Port:

IS_TSEG1

	From	To	Count	Threshold
Bin	0	1	11041544	1
Bin	1	0	11041536	1

Port:

IS_TSEG2

	From	To	Count	Threshold
Bin	0	1	11035219	1
Bin	1	0	11036818	1

Port:

TSEG_1(6)

	From	To	Count	Threshold
Bin	0	1	2332	1
Bin	1	0	3930	1

Port:

TSEG_1(5)

	From	To	Count	Threshold
Bin	0	1	269	1
Bin	1	0	1869	1

Port:

TSEG_1(4)

	From	To	Count	Threshold
Bin	0	1	2406	1
Bin	1	0	4004	1

Port:

TSEG_1(3)

	From	To	Count	Threshold
Bin	0	1	3646	1
Bin	1	0	5237	1

Port:

TSEG_1(2)

	From	To	Count	Threshold
Bin	0	1	4395	1
Bin	1	0	2795	1

Port:

TSEG_1(1)

	From	To	Count	Threshold
Bin	0	1	3285	1
Bin	1	0	1692	1

Port:

TSEG_1(0)

	From	To	Count	Threshold
Bin	0	1	2074	1
Bin	1	0	474	1

Port:

TSEG_2(4)

	From	To	Count	Threshold
Bin	0	1	281	1
Bin	1	0	1879	1

Port:

TSEG_2(3)

	From	To	Count	Threshold
Bin	0	1	321	1
Bin	1	0	1919	1

Port:

TSEG_2(2)

	From	To	Count	Threshold
Bin	0	1	1212	1
Bin	1	0	2803	1

Port:

TSEG_2(1)

	From	To	Count	Threshold
Bin	0	1	1732	1
Bin	1	0	133	1

Port:

TSEG_2(0)

	From	To	Count	Threshold
Bin	0	1	3871	1
Bin	1	0	2271	1

Port:

SJW(4)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	1833	1

Port:

SJW(3)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	1872	1

Port:

SJW(2)

	From	To	Count	Threshold
Bin	0	1	929	1
Bin	1	0	2526	1

Port:

SJW(1)

	From	To	Count	Threshold
Bin	0	1	2558	1
Bin	1	0	965	1

Port:

SJW(0)

	From	To	Count	Threshold
Bin	0	1	949	1
Bin	1	0	2546	1

Port:

START_EDGE

	From	To	Count	Threshold
Bin	0	1	6481	1
Bin	1	0	8081	1

Port:

SEGM_COUNTER(6)

	From	To	Count	Threshold
Bin	0	1	142554	1
Bin	1	0	144154	1

Port:

SEGM_COUNTER(5)

	From	To	Count	Threshold
Bin	0	1	246745	1
Bin	1	0	248345	1

Port:

SEGM_COUNTER(4)

	From	To	Count	Threshold
Bin	0	1	794895	1
Bin	1	0	796495	1

Port:

SEGM_COUNTER(3)

	From	To	Count	Threshold
Bin	0	1	4519840	1
Bin	1	0	4521440	1

Port:

SEGM_COUNTER(2)

	From	To	Count	Threshold
Bin	0	1	12002319	1
Bin	1	0	12003919	1

Port:

SEGM_COUNTER(1)

	From	To	Count	Threshold
Bin	0	1	22876595	1
Bin	1	0	22878195	1

Port:

SEGM_COUNTER(0)

	From	To	Count	Threshold
Bin	0	1	42573590	1
Bin	1	0	42575190	1

Port:

SEGM_END

	From	To	Count	Threshold
Bin	0	1	22084411	1
Bin	1	0	22086011	1

Port:

H_SYNC_VALID

	From	To	Count	Threshold
Bin	0	1	55365	1
Bin	1	0	56965	1

Port:

EXIT_SEGM_REQ

	From	To	Count	Threshold
Bin	0	1	10030898	1
Bin	1	0	10032498	1

Signal:

SEL_TSEG1

	From	To	Count	Threshold
Bin	0	1	33119917	1
Bin	1	0	33121509	1

Signal:

EXP_SEG_LENGTH_CE

	From	To	Count	Threshold
Bin	0	1	22427860	1
Bin	1	0	22429460	1

Signal:

PHASE_ERR_MT_SJW

	From	To	Count	Threshold
Bin	0	1	5249987	1
Bin	1	0	5251586	1

Signal:

PHASE_ERR_EQ_SJW

	From	To	Count	Threshold
Bin	0	1	13191740	1
Bin	1	0	13193334	1

Signal:

EXIT_PH2_IMMEDIATE

	From	To	Count	Threshold
Bin	0	1	7798	1
Bin	1	0	9398	1

Signal:

EXIT_SEGM_REGULAR

	From	To	Count	Threshold
Bin	0	1	10020539	1
Bin	1	0	10022139	1

Signal:

EXIT_SEGM_REGULAR_TSEG1

	From	To	Count	Threshold
Bin	0	1	5078781	1
Bin	1	0	5080381	1

Signal:

EXIT_SEGM_REGULAR_TSEG2

	From	To	Count	Threshold
Bin	0	1	9991666	1
Bin	1	0	9993266	1

Signal:

SJW_MT_ZERO

	From	To	Count	Threshold
Bin	0	1	1831	1
Bin	1	0	1838	1

Signal:

USE_BASIC_SEGM_LENGTH

	From	To	Count	Threshold
Bin	0	1	22085587	1
Bin	1	0	22087187	1

Signal:

PHASE_ERR_SJW_BY_ONE

	From	To	Count	Threshold
Bin	0	1	6276773	1
Bin	1	0	6278373	1

Signal:

SHORTEN_TSEG1_AFTER_TSEG2

	From	To	Count	Threshold
Bin	0	1	7609	1
Bin	1	0	9209	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

">" expression

273: if (a > b) then

	Evaluated to	Count	Threshold
Bin	False	3200	1
Bin	True	12800	1

"=" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	66299187	1
Bin	True	79516	1

"=" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	66372222	1
Bin	True	6481	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
                               <------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	66292706	1
Bin	False	True	6481	1
Bin	True	False	79516	1

"=" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	66357521	1
Bin	True	21182	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
                               <----------------LHS----------------->    <-------------RHS------------->

	LHS	RHS	Count	Threshold
Bin	False	False	66271524	1
Bin	False	True	21182	1
Bin	True	False	85997	1

"=" expression

352: (segm_end = '1' and is_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	22202410	1
Bin	True	44176293	1

"=" expression

352: (segm_end = '1' and is_tseg2 = '1') or

	Evaluated to	Count	Threshold
Bin	False	33258796	1
Bin	True	33119907	1

"and" expression

352:                          (segm_end = '1' and is_tseg2 = '1') or 
                               <----LHS----->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	11049634	1
Bin	True	False	22106020	1
Bin	True	True	22070273	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or

	LHS	RHS	Count	Threshold
Bin	False	False	44215862	1
Bin	False	True	22055662	1
Bin	True	False	92568	1

"=" expression

353: (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	False	44179493	1
Bin	True	22199210	1

"=" expression

353: (segm_end = '0' and is_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	False	33130289	1
Bin	True	33248414	1

"and" expression

353:                          (segm_end = '0' and is_tseg1 = '1') else 
                               <----LHS----->     <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	22106910	1
Bin	True	False	11057706	1
Bin	True	True	11141504	1

"or" expression

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else

	LHS	RHS	Count	Threshold
Bin	False	False	33125464	1
Bin	False	True	11090398	1
Bin	True	False	22111735	1

"=" expression

357: resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else

	Evaluated to	Count	Threshold
Bin	False	33139607	1
Bin	True	33123577	1

"=" expression

361: to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	103784502	1
Bin	True	55367	1

"=" expression

362:                                                 shorten_tseg1_after_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	False	103825872	1
Bin	True	13997	1

"or" expression

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else

	LHS	RHS	Count	Threshold
Bin	False	False	103770505	1
Bin	False	True	13997	1
Bin	True	False	55367	1

"=" expression

363: resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else

	Evaluated to	Count	Threshold
Bin	False	44356114	1
Bin	True	59414391	1

"=" expression

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	73106276	1
Bin	True	62351033	1

"=" expression

372: sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	135327008	1
Bin	True	130301	1

"or" expression

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
                                               <----LHS----->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	72998513	1
Bin	False	True	107763	1
Bin	True	False	62328495	1

"=" expression

373: exit_ph2_immediate = '1')

	Evaluated to	Count	Threshold
Bin	False	135427569	1
Bin	True	29740	1

"or" expression

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	72991475	1
Bin	False	True	7038	1
Bin	True	False	62436094	1

"=" expression

384: use_basic_segm_length <= '1' when (start_edge = '1') or

	Evaluated to	Count	Threshold
Bin	False	44295468	1
Bin	True	6481	1

"=" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and

	Evaluated to	Count	Threshold
Bin	False	22195048	1
Bin	True	22106901	1

"=" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and

	Evaluated to	Count	Threshold
Bin	False	75219	1
Bin	True	44226730	1

"and" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and 
                                           <----LHS----->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	22140677	1
Bin	True	False	20848	1
Bin	True	True	22086053	1

"=" expression

386: shorten_tseg1_after_tseg2 = '0')

	Evaluated to	Count	Threshold
Bin	False	15880	1
Bin	True	44286069	1

"and" expression

385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	LHS	RHS	Count	Threshold
Bin	False	True	22206963	1
Bin	True	False	6947	1
Bin	True	True	22079106	1

"or" expression

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0')

	LHS	RHS	Count	Threshold
Bin	False	False	22216362	1
Bin	False	True	22079106	1
Bin	True	False	6481	1

"=" expression

396: resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1')

	Evaluated to	Count	Threshold
Bin	False	105086396	1
Bin	True	127100972	1

"=" expression

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	23217527	1
Bin	True	22660170	1

"=" expression

400: exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or

	Evaluated to	Count	Threshold
Bin	False	44658396	1
Bin	True	1219301	1

"or" expression

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
                                       <----LHS----->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	22490312	1
Bin	False	True	727215	1
Bin	True	False	22168084	1

"=" expression

401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	False	45805678	1
Bin	True	72019	1

"or" expression

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	22439141	1
Bin	False	True	51171	1
Bin	True	False	23366537	1

"=" expression

401:                                   h_sync_valid = '1' or start_edge = '1')

	Evaluated to	Count	Threshold
Bin	False	45871216	1
Bin	True	6481	1

"or" expression

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	22432660	1
Bin	False	True	6481	1
Bin	True	False	23438556	1

"=" expression

407: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

410: if (exp_seg_length_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	503553689	1
Bin	True	22820611	1

"=" expression

428: phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else

	Evaluated to	Count	Threshold
Bin	False	130273660	1
Bin	True	68185836	1

"=" expression

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and

	Evaluated to	Count	Threshold
Bin	False	18305575	1
Bin	True	21960237	1

"=" expression

458: exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and

	Evaluated to	Count	Threshold
Bin	False	32522012	1
Bin	True	7743800	1

"or" expression

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
                                         <--------LHS--------->    <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	10561775	1
Bin	False	True	7743800	1
Bin	True	False	21960237	1

"=" expression

459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	22348759	1
Bin	True	17917053	1

"and" expression

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	5251981	1
Bin	True	False	17038965	1
Bin	True	True	12665072	1

"=" expression

459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	Evaluated to	Count	Threshold
Bin	False	39470418	1
Bin	True	795394	1

"and" expression

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	787588	1
Bin	True	False	12657266	1
Bin	True	True	7806	1

"=" expression

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	False	12564536	1
Bin	True	7798	1

"=" expression

468: shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0')

	Evaluated to	Count	Threshold
Bin	False	6278751	1
Bin	True	6293583	1

"and" expression

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
                                               <---------LHS---------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	6285974	1
Bin	True	False	189	1
Bin	True	True	7609	1

"=" expression

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and

	Evaluated to	Count	Threshold
Bin	False	21044009	1
Bin	True	17677805	1

"=" expression

486: exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and

	Evaluated to	Count	Threshold
Bin	False	37926469	1
Bin	True	795345	1

"and" expression

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
                                              <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	20407	1
Bin	True	False	16902867	1
Bin	True	True	774938	1

"=" expression

487: sjw_mt_zero = '1')

	Evaluated to	Count	Threshold
Bin	False	8693698	1
Bin	True	30028116	1

"and" expression

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	29408076	1
Bin	True	False	154898	1
Bin	True	True	620040	1

"=" expression

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	21044009	1
Bin	True	17057765	1

"=" expression

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	23031092	1
Bin	True	15070682	1

"and" expression

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
                                              <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	9991871	1
Bin	True	False	11978954	1
Bin	True	True	5078811	1

"=" expression

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	16125535	1
Bin	True	21009085	1

"=" expression

496: exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')

	Evaluated to	Count	Threshold
Bin	False	22066818	1
Bin	True	15067802	1

"and" expression

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
                                             <----LHS----->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	5076136	1
Bin	True	False	11017419	1
Bin	True	True	9991666	1

"=" expression

507: exit_segm_req <= '1' when (exit_ph2_immediate = '1') or

	Evaluated to	Count	Threshold
Bin	False	25104554	1
Bin	True	7798	1

"=" expression

508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	False	20033571	1
Bin	True	5078781	1

"=" expression

508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	Evaluated to	Count	Threshold
Bin	False	15120617	1
Bin	True	9991735	1

"or" expression

508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
                                   <------------LHS------------>    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	False	10041836	1
Bin	False	True	9991735	1
Bin	True	False	5078781	1

"or" expression

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1')

	LHS	RHS	Count	Threshold
Bin	False	False	10034098	1
Bin	False	True	15070456	1
Bin	True	False	7738	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_SEGMENT_METER_DBT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd

Sub-instances:

Current Instance:

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