NVC code coverage report

If statement on lines 273 to 277:

273:        if (a > b) then 
274:            return a; 
275:        else 
276:            return b; 
277:        end if; 
Count: 8005
Threshold: 1

---

Sequential statement on line 274:

274:            return a; 
Count: 6404
Threshold: 1

---

Sequential statement on line 276:

276:            return b; 
Count: 1601
Threshold: 1

---

If statement on lines 351 to 354:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 
354:                 '0'; 
Count: 68464685
Threshold: 1

---

Signal assignment statement on line 351:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
Count: 34297804
Threshold: 1

---

Signal assignment statement on line 354:

354:                 '0'; 
Count: 34166881
Threshold: 1

---

If statement on lines 356 to 358:

356:    basic_segm_length <= 
357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
358:        resize(unsigned(tseg_2), C_BS_WIDTH); 
Count: 68345965
Threshold: 1

---

Signal assignment statement on line 357:

357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 
Count: 34164945
Threshold: 1

---

Signal assignment statement on line 358:

358:        resize(unsigned(tseg_2), C_BS_WIDTH); 
Count: 34181020
Threshold: 1

---

If statement on lines 360 to 364:

360:    segm_extension <= 
361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 
363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
364:        resize(unsigned(segm_counter), C_EXT_WIDTH); 
Count: 103450928
Threshold: 1

---

Signal assignment statement on line 361:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
Count: 71427
Threshold: 1

---

Signal assignment statement on line 363:

363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 
Count: 59392976
Threshold: 1

---

Signal assignment statement on line 364:

364:        resize(unsigned(segm_counter), C_EXT_WIDTH); 
Count: 43986525
Threshold: 1

---

Signal assignment statement on lines 366 to 367:

366:    segm_ext_add <= resize(basic_segm_length, C_EXP_WIDTH) + 
367:                    resize(segm_extension, C_EXP_WIDTH); 
Count: 114994021
Threshold: 1

---

Signal assignment statement on lines 369 to 370:

369:    segm_ext_sub <= resize(basic_segm_length, C_EXP_WIDTH) - 
370:                    resize(segm_extension, C_EXP_WIDTH); 
Count: 114994021
Threshold: 1

---

If statement on lines 372 to 375:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 
374:                                     else 
375:                        segm_ext_add; 
Count: 137883336
Threshold: 1

---

Signal assignment statement on line 372:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
Count: 63672896
Threshold: 1

---

Signal assignment statement on line 375:

375:                        segm_ext_add; 
Count: 74210440
Threshold: 1

---

If statement on lines 384 to 388:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 
387:                                 else 
388:                             '0'; 
Count: 45693948
Threshold: 1

---

Signal assignment statement on line 384:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
Count: 22779884
Threshold: 1

---

Signal assignment statement on line 388:

388:                             '0'; 
Count: 22914064
Threshold: 1

---

If statement on lines 395 to 398:

395:    exp_seg_length_d <= 
396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
397:                                               else 
398:        resize(sync_segm_length, C_EXP_WIDTH); 
Count: 237367568
Threshold: 1

---

Signal assignment statement on line 396:

396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 
Count: 130546808
Threshold: 1

---

Signal assignment statement on line 398:

398:        resize(sync_segm_length, C_EXP_WIDTH); 
Count: 106820760
Threshold: 1

---

If statement on lines 400 to 403:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 
402:                             else 
403:                         '0'; 
Count: 47278920
Threshold: 1

---

Signal assignment statement on line 400:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
Count: 24152305
Threshold: 1

---

Signal assignment statement on line 403:

403:                         '0'; 
Count: 23126615
Threshold: 1

---

If statement on lines 407 to 413:

407:        if (res_n = '0') then 
408:            exp_seg_length_q <= (others => '1'); 
...
412:            end if; 
413:        end if; 
Count: 1090018206
Threshold: 1

---

Signal assignment statement on line 408:

408:            exp_seg_length_q <= (others => '1'); 
Count: 2424883
Threshold: 1

---

If statement on lines 410 to 412:

410:            if (exp_seg_length_ce = '1') then 
411:                exp_seg_length_q <= exp_seg_length_d; 
412:            end if; 
Count: 543791678
Threshold: 1

---

Signal assignment statement on line 411:

411:                exp_seg_length_q <= exp_seg_length_d; 
Count: 23517458
Threshold: 1

---

Signal assignment statement on lines 425 to 426:

425:    neg_phase_err  <= resize(unsigned(tseg_2), C_E_WIDTH) - 
426:                      resize(unsigned(segm_counter), C_E_WIDTH); 
Count: 92734825
Threshold: 1

---

If statement on lines 428 to 429:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
429:                 resize(unsigned(segm_counter), C_E_WIDTH); 
Count: 198237384
Threshold: 1

---

Signal assignment statement on line 428:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 
Count: 68202743
Threshold: 1

---

Signal assignment statement on line 429:

429:                 resize(unsigned(segm_counter), C_E_WIDTH); 
Count: 130034641
Threshold: 1

---

If statement on lines 431 to 434:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
433:                            else 
434:                        '0'; 
Count: 110441032
Threshold: 1

---

Signal assignment statement on line 431:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
Count: 59311623
Threshold: 1

---

Signal assignment statement on line 434:

434:                        '0'; 
Count: 51129409
Threshold: 1

---

If statement on lines 436 to 439:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 
438:                            else 
439:                        '0'; 
Count: 110441032
Threshold: 1

---

Signal assignment statement on line 436:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
Count: 13488135
Threshold: 1

---

Signal assignment statement on line 439:

439:                        '0'; 
Count: 96952897
Threshold: 1

---

If statement on lines 441 to 445:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 
444:                                else 
445:                            '0'; 
Count: 110441032
Threshold: 1

---

Signal assignment statement on line 441:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
Count: 6281443
Threshold: 1

---

Signal assignment statement on line 445:

445:                            '0'; 
Count: 104159589
Threshold: 1

---

If statement on lines 447 to 448:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
448:                   '0'; 
Count: 5738
Threshold: 1

---

Signal assignment statement on line 447:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 
Count: 3900
Threshold: 1

---

Signal assignment statement on line 448:

448:                   '0'; 
Count: 1838
Threshold: 1

---

If statement on lines 458 to 461:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 
460:                              else 
461:                          '0'; 
Count: 41069810
Threshold: 1

---

Signal assignment statement on line 458:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
Count: 8215
Threshold: 1

---

Signal assignment statement on line 461:

461:                          '0'; 
Count: 41061595
Threshold: 1

---

If statement on lines 468 to 470:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
469:                                     else 
470:                                 '0'; 
Count: 12582490
Threshold: 1

---

Signal assignment statement on line 468:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 
Count: 8014
Threshold: 1

---

Signal assignment statement on line 470:

470:                                 '0'; 
Count: 12574476
Threshold: 1

---

If statement on lines 475 to 478:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 
477:                             else 
478:                         '0'; 
Count: 115532505
Threshold: 1

---

Signal assignment statement on line 475:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
Count: 17260317
Threshold: 1

---

Signal assignment statement on line 478:

478:                         '0'; 
Count: 98272188
Threshold: 1

---

If statement on lines 486 to 491:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 
488:                                    else 
489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
490:                                    else 
491:                                '0'; 
Count: 39344403
Threshold: 1

---

Signal assignment statement on line 486:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
Count: 623276
Threshold: 1

---

Signal assignment statement on line 489:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 
Count: 5051667
Threshold: 1

---

Signal assignment statement on line 491:

491:                                '0'; 
Count: 33669460
Threshold: 1

---

If statement on lines 496 to 498:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
497:                                   else 
498:                               '0'; 
Count: 37747516
Threshold: 1

---

Signal assignment statement on line 496:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 
Count: 9938090
Threshold: 1

---

Signal assignment statement on line 498:

498:                               '0'; 
Count: 27809426
Threshold: 1

---

If statement on lines 507 to 510:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
509:                         else 
510:                     '0'; 
Count: 24979391
Threshold: 1

---

Signal assignment statement on line 507:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
Count: 14997937
Threshold: 1

---

Signal assignment statement on line 510:

510:                     '0'; 
Count: 9981454
Threshold: 1

"if" / "when" / "else" condition on line 273:

273:        if (a > b) then 

	Evaluated to	Count	Threshold
Bin	True	6404	1
Bin	False	1601	1

---

"if" / "when" / "else" condition on lines 351 to 353:

351:    sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or 
352:                          (segm_end = '1' and is_tseg2 = '1') or 
353:                          (segm_end = '0' and is_tseg1 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	34297804	1
Bin	False	34166881	1

---

"if" / "when" / "else" condition on line 357:

357:        resize(unsigned(tseg_1), C_BS_WIDTH) when (sel_tseg1 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	34164945	1
Bin	False	34181020	1

---

"if" / "when" / "else" condition on lines 361 to 362:

361:               to_unsigned(1, C_EXT_WIDTH) when (h_sync_valid = '1' or 
362:                                                 shorten_tseg1_after_tseg2 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	71427	1
Bin	False	103379501	1

---

"if" / "when" / "else" condition on line 363:

363:        resize(unsigned(sjw), C_EXT_WIDTH) when (phase_err_mt_sjw = '1') else 

	Evaluated to	Count	Threshold
Bin	True	59392976	1
Bin	False	43986525	1

---

"if" / "when" / "else" condition on lines 372 to 373:

372:    sync_segm_length <= segm_ext_sub when (is_tseg2 = '1' or h_sync_valid = '1' or 
373:                                           exit_ph2_immediate = '1') 

	Evaluated to	Count	Threshold
Bin	True	63672896	1
Bin	False	74210440	1

---

"if" / "when" / "else" condition on lines 384 to 386:

384:    use_basic_segm_length <= '1' when (start_edge = '1') or 
385:                                      (segm_end = '1' and h_sync_valid = '0' and 
386:                                       shorten_tseg1_after_tseg2 = '0') 

	Evaluated to	Count	Threshold
Bin	True	22779884	1
Bin	False	22914064	1

---

"if" / "when" / "else" condition on line 396:

396:        resize(basic_segm_length, C_EXP_WIDTH) when (use_basic_segm_length = '1') 

	Evaluated to	Count	Threshold
Bin	True	130546808	1
Bin	False	106820760	1

---

"if" / "when" / "else" condition on lines 400 to 401:

400:    exp_seg_length_ce <= '1' when (segm_end = '1' or resync_edge_valid = '1' or 
401:                                   h_sync_valid = '1' or start_edge = '1') 

	Evaluated to	Count	Threshold
Bin	True	24152305	1
Bin	False	23126615	1

---

"if" / "when" / "else" condition on line 407:

407:        if (res_n = '0') then 

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

---

"if" / "when" / "else" condition on line 409:

409:        elsif (rising_edge(clk_sys)) then 

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

---

"if" / "when" / "else" condition on line 410:

410:            if (exp_seg_length_ce = '1') then 

	Evaluated to	Count	Threshold
Bin	True	23517458	1
Bin	False	520274220	1

---

"if" / "when" / "else" condition on line 428:

428:    phase_err <= resize(neg_phase_err, C_E_WIDTH) when (is_tseg2 = '1') else 

	Evaluated to	Count	Threshold
Bin	True	68202743	1
Bin	False	130034641	1

---

"if" / "when" / "else" condition on lines 431 to 432:

431:    phase_err_mt_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) > 
432:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 

	Evaluated to	Count	Threshold
Bin	True	59311623	1
Bin	False	51129409	1

---

"if" / "when" / "else" condition on lines 436 to 437:

436:    phase_err_eq_sjw <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
437:                                  resize(unsigned(sjw), C_E_SJW_WIDTH)) 

	Evaluated to	Count	Threshold
Bin	True	13488135	1
Bin	False	96952897	1

---

"if" / "when" / "else" condition on lines 441 to 443:

441:    phase_err_sjw_by_one <= '1' when (resize(phase_err, C_E_SJW_WIDTH) = 
442:                                      (resize(unsigned(sjw), C_E_SJW_WIDTH) + 
443:                                       to_unsigned(1, C_E_SJW_WIDTH))) 

	Evaluated to	Count	Threshold
Bin	True	6281443	1
Bin	False	104159589	1

---

"if" / "when" / "else" condition on line 447:

447:    sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else 

	Evaluated to	Count	Threshold
Bin	True	3900	1
Bin	False	1838	1

---

"if" / "when" / "else" condition on lines 458 to 459:

458:    exit_ph2_immediate <= '1' when ((phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and 
459:                                    is_tseg2 = '1' and resync_edge_valid = '1') 

	Evaluated to	Count	Threshold
Bin	True	8215	1
Bin	False	41061595	1

---

"if" / "when" / "else" condition on line 468:

468:    shorten_tseg1_after_tseg2 <= '1' when (exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0') 

	Evaluated to	Count	Threshold
Bin	True	8014	1
Bin	False	12574476	1

---

"if" / "when" / "else" condition on lines 475 to 476:

475:    exit_segm_regular <= '1' when (resize(unsigned(segm_counter), C_EXP_WIDTH) >= 
476:                                   resize(unsigned(exp_seg_length_q) - 1, C_EXP_WIDTH)) 

	Evaluated to	Count	Threshold
Bin	True	17260317	1
Bin	False	98272188	1

---

"if" / "when" / "else" condition on lines 486 to 487:

486:    exit_segm_regular_tseg1 <=  '0' when (is_tseg1 = '1' and resync_edge_valid = '1' and 
487:                                          sjw_mt_zero = '1') 

	Evaluated to	Count	Threshold
Bin	True	623276	1
Bin	False	38721127	1

---

"if" / "when" / "else" condition on line 489:

489:                                '1' when (is_tseg1 = '1' and exit_segm_regular = '1') 

	Evaluated to	Count	Threshold
Bin	True	5051667	1
Bin	False	33669460	1

---

"if" / "when" / "else" condition on line 496:

496:    exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1') 

	Evaluated to	Count	Threshold
Bin	True	9938090	1
Bin	False	27809426	1

---

"if" / "when" / "else" condition on lines 507 to 508:

507:    exit_segm_req <= '1' when (exit_ph2_immediate = '1') or 
508:                              (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 

	Evaluated to	Count	Threshold
Bin	True	14997937	1
Bin	False	9981454	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RESYNC_EDGE_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 IS_TSEG2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TSEG_1

	Element	From	To	Count	Threshold	Excluded due to
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TSEG_2

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 SJW

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 START_EDGE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 SEGM_COUNTER

	Element	From	To	Count	Threshold	Excluded due to
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 SEGM_END

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 H_SYNC_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

 EXIT_SEGM_REQ

	From	To	Count	Threshold
Bin	0	1	9978252	1
Bin	1	0	9979853	1

---

Signal:

 SEL_TSEG1

	From	To	Count	Threshold
Bin	0	1	34161303	1
Bin	1	0	34162894	1

---

Signal:

 EXP_SEG_LENGTH_CE

	From	To	Count	Threshold
Bin	0	1	23121812	1
Bin	1	0	23123413	1

---

Signal:

 PHASE_ERR_MT_SJW

	From	To	Count	Threshold
Bin	0	1	5296194	1
Bin	1	0	5297794	1

---

Signal:

 PHASE_ERR_EQ_SJW

	From	To	Count	Threshold
Bin	0	1	13488135	1
Bin	1	0	13489728	1

---

Signal:

 EXIT_PH2_IMMEDIATE

	From	To	Count	Threshold
Bin	0	1	8206	1
Bin	1	0	9807	1

---

Signal:

 EXIT_SEGM_REGULAR

	From	To	Count	Threshold
Bin	0	1	9967316	1
Bin	1	0	9968917	1

---

Signal:

 EXIT_SEGM_REGULAR_TSEG1

	From	To	Count	Threshold
Bin	0	1	5051635	1
Bin	1	0	5053236	1

---

Signal:

 EXIT_SEGM_REGULAR_TSEG2

	From	To	Count	Threshold
Bin	0	1	9938090	1
Bin	1	0	9939691	1

---

Signal:

 SJW_MT_ZERO

	From	To	Count	Threshold
Bin	0	1	1830	1
Bin	1	0	1838	1

---

Signal:

 USE_BASIC_SEGM_LENGTH

	From	To	Count	Threshold
Bin	0	1	22779884	1
Bin	1	0	22781485	1

---

Signal:

 PHASE_ERR_SJW_BY_ONE

	From	To	Count	Threshold
Bin	0	1	6281443	1
Bin	1	0	6283043	1

---

Signal:

 SHORTEN_TSEG1_AFTER_TSEG2

	From	To	Count	Threshold
Bin	0	1	8014	1
Bin	1	0	9615	1

">" expression on line 273:

 a > b 

	Evaluated to	Count	Threshold
Bin	False	1601	1
Bin	True	6404	1

---

"or" expression on lines 351 to 353:

 (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or (segm_end = '1' and is_tseg2 = '1') or (segm_end = '0' and is_tseg1 = '1') 
 <------------------------------------------------------LHS------------------------------------------------------->     <--------------RHS-------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	34166881	1
Bin	False	True	11438127	1
Bin	True	False	22807664	1

---

"or" expression on lines 351 to 352:

 (h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1') or (segm_end = '1' and is_tseg2 = '1') 
  <----------------------------------LHS---------------------------------->      <--------------RHS-------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	45605008	1
Bin	False	True	22749142	1
Bin	True	False	95437	1

---

"or" expression on line 351:

 h_sync_valid = '1' or start_edge = '1' or shorten_tseg1_after_tseg2 = '1' 
 <----------------LHS----------------->    <-------------RHS-------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	68354150	1
Bin	False	True	22381	1
Bin	True	False	88154	1

---

"or" expression on line 351:

 h_sync_valid = '1' or start_edge = '1' 
 <------LHS------->    <-----RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	False	68376531	1
Bin	False	True	6482	1
Bin	True	False	81672	1

---

"=" expression on line 351:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	68383013	1
Bin	True	81672	1

---

"=" expression on line 351:

 start_edge = '1' 

	Evaluated to	Count	Threshold
Bin	False	68458203	1
Bin	True	6482	1

---

"=" expression on line 351:

 shorten_tseg1_after_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	68442304	1
Bin	True	22381	1

---

"and" expression on line 352:

 segm_end = '1' and is_tseg2 = '1' 
 <----LHS----->     <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	11397539	1
Bin	True	False	22801492	1
Bin	True	True	22764240	1

---

"=" expression on line 352:

 segm_end = '1' 

	Evaluated to	Count	Threshold
Bin	False	22898953	1
Bin	True	45565732	1

---

"=" expression on line 352:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34302906	1
Bin	True	34161779	1

---

"and" expression on line 353:

 segm_end = '0' and is_tseg1 = '1' 
 <----LHS----->     <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	22802374	1
Bin	True	False	11405611	1
Bin	True	True	11490140	1

---

"=" expression on line 353:

 segm_end = '0' 

	Evaluated to	Count	Threshold
Bin	False	45568934	1
Bin	True	22895751	1

---

"=" expression on line 353:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34172171	1
Bin	True	34292514	1

---

"=" expression on line 357:

 sel_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	34181020	1
Bin	True	34164945	1

---

"or" expression on lines 361 to 362:

 h_sync_valid = '1' or shorten_tseg1_after_tseg2 = '1' 
 <------LHS------->    <-------------RHS-------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	103379501	1
Bin	False	True	14838	1
Bin	True	False	56589	1

---

"=" expression on line 361:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	103394339	1
Bin	True	56589	1

---

"=" expression on line 362:

 shorten_tseg1_after_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	103436090	1
Bin	True	14838	1

---

"=" expression on line 363:

 phase_err_mt_sjw = '1' 

	Evaluated to	Count	Threshold
Bin	False	43986525	1
Bin	True	59392976	1

---

"or" expression on lines 372 to 373:

 is_tseg2 = '1' or h_sync_valid = '1' or exit_ph2_immediate = '1' 
 <---------------LHS---------------->    <---------RHS----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	74210440	1
Bin	False	True	7441	1
Bin	True	False	63641527	1

---

"or" expression on line 372:

 is_tseg2 = '1' or h_sync_valid = '1' 
 <----LHS----->    <------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	False	74217881	1
Bin	False	True	110507	1
Bin	True	False	63531885	1

---

"=" expression on line 372:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	74328388	1
Bin	True	63554948	1

---

"=" expression on line 372:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	137749766	1
Bin	True	133570	1

---

"=" expression on line 373:

 exit_ph2_immediate = '1' 

	Evaluated to	Count	Threshold
Bin	False	137851967	1
Bin	True	31369	1

---

"or" expression on lines 384 to 386:

 (start_edge = '1') or (segm_end = '1' and h_sync_valid = '0' and shorten_tseg1_after_tseg2 = '0') 
  <-----LHS------>      <----------------------------------RHS---------------------------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	22914064	1
Bin	False	True	22773402	1
Bin	True	False	6482	1

---

"=" expression on line 384:

 start_edge = '1' 

	Evaluated to	Count	Threshold
Bin	False	45687466	1
Bin	True	6482	1

---

"and" expression on lines 385 to 386:

 segm_end = '1' and h_sync_valid = '0' and shorten_tseg1_after_tseg2 = '0' 
 <----------------LHS---------------->     <-------------RHS-------------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22903867	1
Bin	True	False	7342	1
Bin	True	True	22773402	1

---

"and" expression on line 385:

 segm_end = '1' and h_sync_valid = '0' 
 <----LHS----->     <------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	True	22835973	1
Bin	True	False	21604	1
Bin	True	True	22780744	1

---

"=" expression on line 385:

 segm_end = '1' 

	Evaluated to	Count	Threshold
Bin	False	22891600	1
Bin	True	22802348	1

---

"=" expression on line 385:

 h_sync_valid = '0' 

	Evaluated to	Count	Threshold
Bin	False	77231	1
Bin	True	45616717	1

---

"=" expression on line 386:

 shorten_tseg1_after_tseg2 = '0' 

	Evaluated to	Count	Threshold
Bin	False	16679	1
Bin	True	45677269	1

---

"=" expression on line 396:

 use_basic_segm_length = '1' 

	Evaluated to	Count	Threshold
Bin	False	106820760	1
Bin	True	130546808	1

---

"or" expression on lines 400 to 401:

 segm_end = '1' or resync_edge_valid = '1' or h_sync_valid = '1' or start_edge = '1' 
 <-----------------------------LHS----------------------------->    <-----RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	False	23126615	1
Bin	False	True	6482	1
Bin	True	False	24145823	1

---

"or" expression on lines 400 to 401:

 segm_end = '1' or resync_edge_valid = '1' or h_sync_valid = '1' 
 <------------------LHS------------------>    <------RHS-------> 

	LHS	RHS	Count	Threshold
Bin	False	False	23133097	1
Bin	False	True	52425	1
Bin	True	False	24071794	1

---

"or" expression on line 400:

 segm_end = '1' or resync_edge_valid = '1' 
 <----LHS----->    <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	False	23185522	1
Bin	False	True	729814	1
Bin	True	False	22865553	1

---

"=" expression on line 400:

 segm_end = '1' 

	Evaluated to	Count	Threshold
Bin	False	23915336	1
Bin	True	23363584	1

---

"=" expression on line 400:

 resync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	46051075	1
Bin	True	1227845	1

---

"=" expression on line 401:

 h_sync_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	47204891	1
Bin	True	74029	1

---

"=" expression on line 401:

 start_edge = '1' 

	Evaluated to	Count	Threshold
Bin	False	47272438	1
Bin	True	6482	1

---

"=" expression on line 407:

 res_n = '0' 

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

---

"=" expression on line 410:

 exp_seg_length_ce = '1' 

	Evaluated to	Count	Threshold
Bin	False	520274220	1
Bin	True	23517458	1

---

"=" expression on line 428:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	130034641	1
Bin	True	68202743	1

---

"and" expression on lines 458 to 459:

 (phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and is_tseg2 = '1' and resync_edge_valid = '1' 
 <----------------------------------LHS---------------------------------->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	792192	1
Bin	True	False	13010287	1
Bin	True	True	8215	1

---

"and" expression on lines 458 to 459:

 (phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1') and is_tseg2 = '1' 
  <-----------------------LHS------------------------>      <----RHS-----> 

	LHS	RHS	Count	Threshold
Bin	False	True	5298051	1
Bin	True	False	17398176	1
Bin	True	True	13018502	1

---

"or" expression on line 458:

 phase_err_mt_sjw = '0' or phase_err_sjw_by_one = '1' 
 <--------LHS--------->    <----------RHS-----------> 

	LHS	RHS	Count	Threshold
Bin	False	False	10653132	1
Bin	False	True	7749297	1
Bin	True	False	22667381	1

---

"=" expression on line 458:

 phase_err_mt_sjw = '0' 

	Evaluated to	Count	Threshold
Bin	False	18402429	1
Bin	True	22667381	1

---

"=" expression on line 458:

 phase_err_sjw_by_one = '1' 

	Evaluated to	Count	Threshold
Bin	False	33320513	1
Bin	True	7749297	1

---

"=" expression on line 459:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	22753257	1
Bin	True	18316553	1

---

"=" expression on line 459:

 resync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	40269403	1
Bin	True	800407	1

---

"and" expression on line 468:

 exit_ph2_immediate = '1' and phase_err_sjw_by_one = '0' 
 <---------LHS---------->     <----------RHS-----------> 

	LHS	RHS	Count	Threshold
Bin	False	True	6291048	1
Bin	True	False	192	1
Bin	True	True	8014	1

---

"=" expression on line 468:

 exit_ph2_immediate = '1' 

	Evaluated to	Count	Threshold
Bin	False	12574284	1
Bin	True	8206	1

---

"=" expression on line 468:

 phase_err_sjw_by_one = '0' 

	Evaluated to	Count	Threshold
Bin	False	6283428	1
Bin	True	6299062	1

---

"and" expression on lines 486 to 487:

 is_tseg1 = '1' and resync_edge_valid = '1' and sjw_mt_zero = '1' 
 <------------------LHS------------------->     <------RHS------> 

	LHS	RHS	Count	Threshold
Bin	False	True	29990437	1
Bin	True	False	156211	1
Bin	True	True	623276	1

---

"and" expression on line 486:

 is_tseg1 = '1' and resync_edge_valid = '1' 
 <----LHS----->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	20874	1
Bin	True	False	17227110	1
Bin	True	True	779487	1

---

"=" expression on line 486:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	21337806	1
Bin	True	18006597	1

---

"=" expression on line 486:

 resync_edge_valid = '1' 

	Evaluated to	Count	Threshold
Bin	False	38544042	1
Bin	True	800361	1

---

"=" expression on line 487:

 sjw_mt_zero = '1' 

	Evaluated to	Count	Threshold
Bin	False	8730690	1
Bin	True	30613713	1

---

"and" expression on line 489:

 is_tseg1 = '1' and exit_segm_regular = '1' 
 <----LHS----->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	9938298	1
Bin	True	False	12331654	1
Bin	True	True	5051667	1

---

"=" expression on line 489:

 is_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	21337806	1
Bin	True	17383321	1

---

"=" expression on line 489:

 exit_segm_regular = '1' 

	Evaluated to	Count	Threshold
Bin	False	23731162	1
Bin	True	14989965	1

---

"and" expression on line 496:

 is_tseg2 = '1' and exit_segm_regular = '1' 
 <----LHS----->     <---------RHS---------> 

	LHS	RHS	Count	Threshold
Bin	False	True	5048828	1
Bin	True	False	11364168	1
Bin	True	True	9938090	1

---

"=" expression on line 496:

 is_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	16445258	1
Bin	True	21302258	1

---

"=" expression on line 496:

 exit_segm_regular = '1' 

	Evaluated to	Count	Threshold
Bin	False	22760598	1
Bin	True	14986918	1

---

"or" expression on lines 507 to 508:

 (exit_ph2_immediate = '1') or (exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1') 
  <---------LHS---------->      <----------------------------RHS----------------------------->  

	LHS	RHS	Count	Threshold
Bin	False	False	9981454	1
Bin	False	True	14989731	1
Bin	True	False	8153	1

---

"=" expression on line 507:

 exit_ph2_immediate = '1' 

	Evaluated to	Count	Threshold
Bin	False	24971185	1
Bin	True	8206	1

---

"or" expression on line 508:

 exit_segm_regular_tseg1 = '1' or exit_segm_regular_tseg2 = '1' 
 <------------LHS------------>    <------------RHS------------> 

	LHS	RHS	Count	Threshold
Bin	False	False	9989607	1
Bin	False	True	9938149	1
Bin	True	False	5051635	1

---

"=" expression on line 508:

 exit_segm_regular_tseg1 = '1' 

	Evaluated to	Count	Threshold
Bin	False	19927756	1
Bin	True	5051635	1

---

"=" expression on line 508:

 exit_segm_regular_tseg2 = '1' 

	Evaluated to	Count	Threshold
Bin	False	15041242	1
Bin	True	9938149	1