NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.TXTB_PRIORITY_GEN(7).TXTB_PRIORITY_ODD_GEN	100.0 % (6/6)	100.0 % (4/4)	N.A.	100.0 % (14/14)	N.A.	N.A.	100.0 % (24/24)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

428:            mr_tx_priority_txbbm(i) <= mr_tx_priority(i) when (mr_mode_txbbm = '0') 
429:                                                         else 
430:                                       mr_tx_priority(i - 1);

Count: 490
Threshold: 1

Signal assignment statement:

428: mr_tx_priority_txbbm(i) <= mr_tx_priority(i) when (mr_mode_txbbm = '0')
Count: 235
Threshold: 1

Signal assignment statement:

430: mr_tx_priority(i - 1);
Count: 255
Threshold: 1

If statement:

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and 
433:                                           txtb_allow_bb(i - 1) = '1') 
434:                                     else 
435:                                 '0';

Count: 1687
Threshold: 1

Signal assignment statement:

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and

Count: 7
Threshold: 1

Signal assignment statement:

435: '0';
Count: 1680
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

428: mr_tx_priority_txbbm(i) <= mr_tx_priority(i) when (mr_mode_txbbm = '0')

	Evaluated to	Count	Threshold
Bin	True	235	1
Bin	False	255	1

"if" / "when" / "else" condition:

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and 
433:                                           txtb_allow_bb(i - 1) = '1')

	Evaluated to	Count	Threshold
Bin	True	7	1
Bin	False	1680	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

"and" expression

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and 
433:                                           txtb_allow_bb(i - 1) = '1')

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

428: mr_tx_priority_txbbm(i) <= mr_tx_priority(i) when (mr_mode_txbbm = '0')

	Evaluated to	Count	Threshold
Bin	False	255	1
Bin	True	235	1

"=" expression

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and

	Evaluated to	Count	Threshold
Bin	False	1580	1
Bin	True	107	1

"=" expression

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and

	Evaluated to	Count	Threshold
Bin	False	1336	1
Bin	True	351	1

"and" expression

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and 
                                               <-------LHS------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	337	1
Bin	True	False	93	1
Bin	True	True	14	1

"=" expression

433:                                           txtb_allow_bb(i - 1) = '1')

	Evaluated to	Count	Threshold
Bin	False	7	1
Bin	True	7	1

"and" expression

432:            txtb_is_bb(i / 2) <= '1' when (mr_mode_txbbm = '1' and curr_txtb_index_i = i-1 and 
433:                                           txtb_allow_bb(i - 1) = '1')

	LHS	RHS	Count	Threshold
Bin	True	False	7	1
Bin	True	True	7	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TX_ARBITRATOR_INST.TXTB_PRIORITY_GEN(7).TXTB_PRIORITY_ODD_GEN

File: /__w/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

"and" expression

Covered expressions:

"=" expression

"=" expression

"=" expression

"and" expression

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: