Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| RX_SHIFT_RES_REG_INST |
100.0 % (6/6) |
100.0 % (6/6) |
100.0 % (28/28) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (42/42) |
| RX_SHIFT_CMD_GEN(0) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
100.0 % (7/7) |
N.A. |
N.A. |
100.0 % (12/12) |
| RX_SHIFT_CMD_GEN(1) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
100.0 % (7/7) |
N.A. |
N.A. |
100.0 % (12/12) |
| RX_SHIFT_CMD_GEN(2) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
100.0 % (7/7) |
N.A. |
N.A. |
100.0 % (12/12) |
| RX_SHIFT_CMD_GEN(3) |
100.0 % (3/3) |
100.0 % (2/2) |
N.A. |
100.0 % (7/7) |
N.A. |
N.A. |
100.0 % (12/12) |
| SHIFT_REG_BYTE_INST |
100.0 % (25/25) |
100.0 % (30/30) |
100.0 % (156/156) |
100.0 % (22/22) |
N.A. |
N.A. |
100.0 % (233/233) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
222: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0')
223: else
224: '1'; Count: 159912
Threshold: 1
Signal assignment statement:
222: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') Count: 78351
Threshold: 1
Signal assignment statement:
224: '1'; Count: 81561
Threshold: 1
Signal assignment statement:
260: rec_dlc_d <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; Count: 4978111
Threshold: 1
Signal assignment statement:
262: rx_shift_in_sel_demuxed <= rx_shift_in_sel & rx_shift_in_sel &
263: rx_shift_in_sel; Count: 75296
Threshold: 1
If statement:
289: if (res_n_i_q_scan = '0') then
290: rec_ident <= (others => '0');
...
300: end if;
301: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
290: rec_ident <= (others => '0'); Count: 2597318
Threshold: 1
If statement:
292: if (rx_store_base_id = '1') then
293: rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <=
294: rx_shift_reg_q(9 downto 0) & rx_data_nbs;
295: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
293: rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <=
294: rx_shift_reg_q(9 downto 0) & rx_data_nbs; Count: 52702
Threshold: 1
If statement:
297: if (rx_store_ext_id = '1') then
298: rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <=
299: rx_shift_reg_q(16 downto 0) & rx_data_nbs;
300: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
298: rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <=
299: rx_shift_reg_q(16 downto 0) & rx_data_nbs; Count: 14167
Threshold: 1
If statement:
309: if (res_n_i_q_scan = '0') then
310: rec_ident_type <= '0';
...
314: end if;
315: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
310: rec_ident_type <= '0'; Count: 2597318
Threshold: 1
If statement:
312: if (rx_store_ide = '1') then
313: rec_ident_type <= rx_data_nbs;
314: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
313: rec_ident_type <= rx_data_nbs; Count: 52199
Threshold: 1
If statement:
323: if (res_n_i_q_scan = '0') then
324: rec_is_rtr_i <= '0';
...
328: end if;
329: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
324: rec_is_rtr_i <= '0'; Count: 2597318
Threshold: 1
If statement:
326: if (rx_store_rtr = '1') then
327: rec_is_rtr_i <= rx_data_nbs;
328: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
327: rec_is_rtr_i <= rx_data_nbs; Count: 66604
Threshold: 1
If statement:
333: rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN)
334: else
335: NO_RTR_FRAME; Count: 104039
Threshold: 1
Signal assignment statement:
333: rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) Count: 73999
Threshold: 1
Signal assignment statement:
335: NO_RTR_FRAME; Count: 30040
Threshold: 1
If statement:
342: if (res_n_i_q_scan = '0') then
343: rec_frame_type_i <= '0';
...
347: end if;
348: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
343: rec_frame_type_i <= '0'; Count: 2597318
Threshold: 1
If statement:
345: if (rx_store_edl = '1') then
346: rec_frame_type_i <= rx_data_nbs;
347: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
346: rec_frame_type_i <= rx_data_nbs; Count: 50382
Threshold: 1
If statement:
359: if (res_n_i_q_scan = '0') then
360: rec_esi <= '0';
...
364: end if;
365: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
360: rec_esi <= '0'; Count: 2597318
Threshold: 1
If statement:
362: if (rx_store_esi = '1') then
363: rec_esi <= rx_data_nbs;
364: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
363: rec_esi <= rx_data_nbs; Count: 28077
Threshold: 1
If statement:
373: if (res_n_i_q_scan = '0') then
374: rec_brs <= '0';
...
378: end if;
379: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
374: rec_brs <= '0'; Count: 2597318
Threshold: 1
If statement:
376: if (rx_store_brs = '1') then
377: rec_brs <= rx_data_nbs;
378: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
377: rec_brs <= rx_data_nbs; Count: 28129
Threshold: 1
If statement:
387: if (res_n_i_q_scan = '0') then
388: rec_dlc <= (others => '0');
...
392: end if;
393: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
388: rec_dlc <= (others => '0'); Count: 2597318
Threshold: 1
If statement:
390: if (rx_store_dlc = '1') then
391: rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs;
392: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
391: rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; Count: 49346
Threshold: 1
If statement:
401: if (res_n_i_q_scan = '0') then
402: rx_stuff_count <= (others => '0');
...
406: end if;
407: end if; Count: 1055287652
Threshold: 1
Signal assignment statement:
402: rx_stuff_count <= (others => '0'); Count: 2597318
Threshold: 1
If statement:
404: if (rx_store_stuff_count = '1') then
405: rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs;
406: end if; Count: 526312533
Threshold: 1
Signal assignment statement:
405: rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; Count: 13222
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
222: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 78351 | 1 |
| Bin | False | 81561 | 1 |
"if" / "when" / "else" condition:
289: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
291: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
292: if (rx_store_base_id = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 52702 | 1 |
| Bin | False | 526259831 | 1 |
"if" / "when" / "else" condition:
297: if (rx_store_ext_id = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 14167 | 1 |
| Bin | False | 526298366 | 1 |
"if" / "when" / "else" condition:
309: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
311: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
312: if (rx_store_ide = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 52199 | 1 |
| Bin | False | 526260334 | 1 |
"if" / "when" / "else" condition:
323: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
325: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
326: if (rx_store_rtr = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 66604 | 1 |
| Bin | False | 526245929 | 1 |
"if" / "when" / "else" condition:
333: rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 73999 | 1 |
| Bin | False | 30040 | 1 |
"if" / "when" / "else" condition:
342: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
344: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
345: if (rx_store_edl = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 50382 | 1 |
| Bin | False | 526262151 | 1 |
"if" / "when" / "else" condition:
359: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
361: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
362: if (rx_store_esi = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 28077 | 1 |
| Bin | False | 526284456 | 1 |
"if" / "when" / "else" condition:
373: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
375: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
376: if (rx_store_brs = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 28129 | 1 |
| Bin | False | 526284404 | 1 |
"if" / "when" / "else" condition:
387: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
389: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
390: if (rx_store_dlc = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 49346 | 1 |
| Bin | False | 526263187 | 1 |
"if" / "when" / "else" condition:
401: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2597318 | 1 |
| Bin | False | 1052690334 | 1 |
"if" / "when" / "else" condition:
403: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526312533 | 1 |
| Bin | False | 526377801 | 1 |
"if" / "when" / "else" condition:
404: if (rx_store_stuff_count = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 13222 | 1 |
| Bin | False | 526299311 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
Port:
RX_TRIGGER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10015414 | 1 |
| Bin | 1 | 0 | 10017014 | 1 |
Port:
RX_DATA_NBS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Port:
RX_CLEAR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70279 | 1 |
| Bin | 1 | 0 | 71879 | 1 |
Port:
RX_SHIFT_ENA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 271239 | 1 |
| Bin | 1 | 0 | 561616 | 1 |
Port:
RX_SHIFT_ENA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 276807 | 1 |
| Bin | 1 | 0 | 556048 | 1 |
Port:
RX_SHIFT_ENA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 283080 | 1 |
| Bin | 1 | 0 | 549775 | 1 |
Port:
RX_SHIFT_ENA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 296458 | 1 |
| Bin | 1 | 0 | 536397 | 1 |
Port:
RX_SHIFT_IN_SEL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Port:
RX_STORE_BASE_ID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53369 | 1 |
| Bin | 1 | 0 | 54969 | 1 |
Port:
RX_STORE_EXT_ID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14167 | 1 |
| Bin | 1 | 0 | 15767 | 1 |
Port:
RX_STORE_IDE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104516 | 1 |
| Bin | 1 | 0 | 106116 | 1 |
Port:
RX_STORE_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 133397 | 1 |
| Bin | 1 | 0 | 134997 | 1 |
Port:
RX_STORE_EDL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100870 | 1 |
| Bin | 1 | 0 | 102470 | 1 |
Port:
RX_STORE_DLC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49346 | 1 |
| Bin | 1 | 0 | 50946 | 1 |
Port:
RX_STORE_ESI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56154 | 1 |
| Bin | 1 | 0 | 57754 | 1 |
Port:
RX_STORE_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56258 | 1 |
| Bin | 1 | 0 | 57858 | 1 |
Port:
RX_STORE_STUFF_COUNT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26678 | 1 |
| Bin | 1 | 0 | 28278 | 1 |
Port:
REC_IDENT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34332 | 1 |
| Bin | 1 | 0 | 30165 | 1 |
Port:
REC_IDENT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20951 | 1 |
| Bin | 1 | 0 | 16748 | 1 |
Port:
REC_IDENT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34995 | 1 |
| Bin | 1 | 0 | 29978 | 1 |
Port:
REC_IDENT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26409 | 1 |
| Bin | 1 | 0 | 21440 | 1 |
Port:
REC_IDENT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37621 | 1 |
| Bin | 1 | 0 | 32560 | 1 |
Port:
REC_IDENT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27574 | 1 |
| Bin | 1 | 0 | 22162 | 1 |
Port:
REC_IDENT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37576 | 1 |
| Bin | 1 | 0 | 32729 | 1 |
Port:
REC_IDENT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26623 | 1 |
| Bin | 1 | 0 | 21662 | 1 |
Port:
REC_IDENT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34131 | 1 |
| Bin | 1 | 0 | 30013 | 1 |
Port:
REC_IDENT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25018 | 1 |
| Bin | 1 | 0 | 20939 | 1 |
Port:
REC_IDENT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35861 | 1 |
| Bin | 1 | 0 | 31802 | 1 |
Port:
REC_IDENT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6676 | 1 |
| Bin | 1 | 0 | 77411 | 1 |
Port:
REC_IDENT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 76980 | 1 |
Port:
REC_IDENT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6016 | 1 |
| Bin | 1 | 0 | 75936 | 1 |
Port:
REC_IDENT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6457 | 1 |
| Bin | 1 | 0 | 77301 | 1 |
Port:
REC_IDENT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6203 | 1 |
| Bin | 1 | 0 | 75854 | 1 |
Port:
REC_IDENT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6655 | 1 |
| Bin | 1 | 0 | 77348 | 1 |
Port:
REC_IDENT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6116 | 1 |
| Bin | 1 | 0 | 76014 | 1 |
Port:
REC_IDENT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6759 | 1 |
| Bin | 1 | 0 | 77172 | 1 |
Port:
REC_IDENT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6340 | 1 |
| Bin | 1 | 0 | 76882 | 1 |
Port:
REC_IDENT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7191 | 1 |
| Bin | 1 | 0 | 78168 | 1 |
Port:
REC_IDENT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6170 | 1 |
| Bin | 1 | 0 | 76119 | 1 |
Port:
REC_IDENT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6636 | 1 |
| Bin | 1 | 0 | 77753 | 1 |
Port:
REC_IDENT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6122 | 1 |
| Bin | 1 | 0 | 76213 | 1 |
Port:
REC_IDENT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6712 | 1 |
| Bin | 1 | 0 | 78180 | 1 |
Port:
REC_IDENT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6213 | 1 |
| Bin | 1 | 0 | 76204 | 1 |
Port:
REC_IDENT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7044 | 1 |
| Bin | 1 | 0 | 78347 | 1 |
Port:
REC_IDENT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6316 | 1 |
| Bin | 1 | 0 | 75925 | 1 |
Port:
REC_IDENT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6757 | 1 |
| Bin | 1 | 0 | 77490 | 1 |
Port:
REC_DLC_D(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564607 | 1 |
| Bin | 1 | 0 | 566201 | 1 |
Port:
REC_DLC_D(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576164 | 1 |
| Bin | 1 | 0 | 577759 | 1 |
Port:
REC_DLC_D(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586427 | 1 |
| Bin | 1 | 0 | 588021 | 1 |
Port:
REC_DLC_D(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1391188 | 1 |
| Bin | 1 | 0 | 1389588 | 1 |
Port:
REC_DLC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20320 | 1 |
| Bin | 1 | 0 | 21919 | 1 |
Port:
REC_DLC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22531 | 1 |
| Bin | 1 | 0 | 24130 | 1 |
Port:
REC_DLC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22383 | 1 |
| Bin | 1 | 0 | 23980 | 1 |
Port:
REC_DLC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26951 | 1 |
| Bin | 1 | 0 | 28549 | 1 |
Port:
REC_IS_RTR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22038 | 1 |
| Bin | 1 | 0 | 23636 | 1 |
Port:
REC_IDENT_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15760 | 1 |
| Bin | 1 | 0 | 17358 | 1 |
Port:
REC_FRAME_TYPE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28440 | 1 |
| Bin | 1 | 0 | 30036 | 1 |
Port:
REC_BRS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20406 | 1 |
| Bin | 1 | 0 | 22002 | 1 |
Port:
REC_ESI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2145 | 1 |
| Bin | 1 | 0 | 3743 | 1 |
Port:
STORE_DATA_WORD(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 237198 | 1 |
| Bin | 1 | 0 | 238797 | 1 |
Port:
STORE_DATA_WORD(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 243752 | 1 |
| Bin | 1 | 0 | 245348 | 1 |
Port:
STORE_DATA_WORD(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 254056 | 1 |
| Bin | 1 | 0 | 255652 | 1 |
Port:
STORE_DATA_WORD(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 261408 | 1 |
| Bin | 1 | 0 | 263004 | 1 |
Port:
STORE_DATA_WORD(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270752 | 1 |
| Bin | 1 | 0 | 272349 | 1 |
Port:
STORE_DATA_WORD(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 281246 | 1 |
| Bin | 1 | 0 | 282842 | 1 |
Port:
STORE_DATA_WORD(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 289484 | 1 |
| Bin | 1 | 0 | 291079 | 1 |
Port:
STORE_DATA_WORD(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 297255 | 1 |
| Bin | 1 | 0 | 298852 | 1 |
Port:
STORE_DATA_WORD(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 286221 | 1 |
| Bin | 1 | 0 | 287818 | 1 |
Port:
STORE_DATA_WORD(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 294374 | 1 |
| Bin | 1 | 0 | 295971 | 1 |
Port:
STORE_DATA_WORD(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 302753 | 1 |
| Bin | 1 | 0 | 304349 | 1 |
Port:
STORE_DATA_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 311493 | 1 |
| Bin | 1 | 0 | 313091 | 1 |
Port:
STORE_DATA_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 323361 | 1 |
| Bin | 1 | 0 | 324957 | 1 |
Port:
STORE_DATA_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 330483 | 1 |
| Bin | 1 | 0 | 332080 | 1 |
Port:
STORE_DATA_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 338889 | 1 |
| Bin | 1 | 0 | 340488 | 1 |
Port:
STORE_DATA_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 345150 | 1 |
| Bin | 1 | 0 | 346748 | 1 |
Port:
STORE_DATA_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 386346 | 1 |
| Bin | 1 | 0 | 387945 | 1 |
Port:
STORE_DATA_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 400757 | 1 |
| Bin | 1 | 0 | 402354 | 1 |
Port:
STORE_DATA_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 409685 | 1 |
| Bin | 1 | 0 | 411281 | 1 |
Port:
STORE_DATA_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 419496 | 1 |
| Bin | 1 | 0 | 421093 | 1 |
Port:
STORE_DATA_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 432274 | 1 |
| Bin | 1 | 0 | 433870 | 1 |
Port:
STORE_DATA_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 442097 | 1 |
| Bin | 1 | 0 | 443695 | 1 |
Port:
STORE_DATA_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 454252 | 1 |
| Bin | 1 | 0 | 455847 | 1 |
Port:
STORE_DATA_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465041 | 1 |
| Bin | 1 | 0 | 466639 | 1 |
Port:
STORE_DATA_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 510943 | 1 |
| Bin | 1 | 0 | 512538 | 1 |
Port:
STORE_DATA_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522813 | 1 |
| Bin | 1 | 0 | 524410 | 1 |
Port:
STORE_DATA_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 532557 | 1 |
| Bin | 1 | 0 | 534152 | 1 |
Port:
STORE_DATA_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 542224 | 1 |
| Bin | 1 | 0 | 543819 | 1 |
Port:
STORE_DATA_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555100 | 1 |
| Bin | 1 | 0 | 556695 | 1 |
Port:
STORE_DATA_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564607 | 1 |
| Bin | 1 | 0 | 566201 | 1 |
Port:
STORE_DATA_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576164 | 1 |
| Bin | 1 | 0 | 577759 | 1 |
Port:
STORE_DATA_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586427 | 1 |
| Bin | 1 | 0 | 588021 | 1 |
Port:
RX_CRC(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 701728 | 1 |
| Bin | 1 | 0 | 1344959 | 1 |
Port:
RX_CRC(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 617784 | 1 |
| Bin | 1 | 0 | 1265848 | 1 |
Port:
RX_CRC(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 655293 | 1 |
| Bin | 1 | 0 | 1160355 | 1 |
Port:
RX_CRC(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 633504 | 1 |
| Bin | 1 | 0 | 1228270 | 1 |
Port:
RX_CRC(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1297485 | 1 |
| Bin | 1 | 0 | 2061120 | 1 |
Port:
RX_CRC(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 734490 | 1 |
| Bin | 1 | 0 | 1192630 | 1 |
Port:
RX_CRC(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 584639 | 1 |
| Bin | 1 | 0 | 561025 | 1 |
Port:
RX_CRC(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564221 | 1 |
| Bin | 1 | 0 | 592790 | 1 |
Port:
RX_CRC(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 593957 | 1 |
| Bin | 1 | 0 | 577433 | 1 |
Port:
RX_CRC(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586188 | 1 |
| Bin | 1 | 0 | 609963 | 1 |
Port:
RX_CRC(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 622165 | 1 |
| Bin | 1 | 0 | 598129 | 1 |
Port:
RX_CRC(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 609198 | 1 |
| Bin | 1 | 0 | 637387 | 1 |
Port:
RX_CRC(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 647375 | 1 |
| Bin | 1 | 0 | 618286 | 1 |
Port:
RX_CRC(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 511003 | 1 |
| Bin | 1 | 0 | 512581 | 1 |
Port:
RX_CRC(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522869 | 1 |
| Bin | 1 | 0 | 524443 | 1 |
Port:
RX_CRC(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 532596 | 1 |
| Bin | 1 | 0 | 534236 | 1 |
Port:
RX_CRC(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 542253 | 1 |
| Bin | 1 | 0 | 543880 | 1 |
Port:
RX_CRC(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555203 | 1 |
| Bin | 1 | 0 | 556735 | 1 |
Port:
RX_CRC(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 564666 | 1 |
| Bin | 1 | 0 | 566279 | 1 |
Port:
RX_CRC(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576233 | 1 |
| Bin | 1 | 0 | 577836 | 1 |
Port:
RX_CRC(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 586482 | 1 |
| Bin | 1 | 0 | 588092 | 1 |
Port:
RX_STUFF_COUNT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3649 | 1 |
| Bin | 1 | 0 | 5249 | 1 |
Port:
RX_STUFF_COUNT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7084 | 1 |
| Bin | 1 | 0 | 8683 | 1 |
Port:
RX_STUFF_COUNT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7751 | 1 |
| Bin | 1 | 0 | 9350 | 1 |
Port:
RX_STUFF_COUNT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6695 | 1 |
| Bin | 1 | 0 | 8295 | 1 |
Signal:
RES_N_I_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78361 | 1 |
| Bin | 1 | 0 | 78351 | 1 |
Signal:
RES_N_I_Q_SCAN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63366 | 1 |
| Bin | 1 | 0 | 63357 | 1 |
Signal:
RX_SHIFT_REG_Q(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 809143 | 1 |
| Bin | 1 | 0 | 1320780 | 1 |
Signal:
RX_SHIFT_REG_Q(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 755072 | 1 |
| Bin | 1 | 0 | 1327389 | 1 |
Signal:
RX_SHIFT_REG_Q(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 675152 | 1 |
| Bin | 1 | 0 | 1551895 | 1 |
Signal:
RX_SHIFT_REG_Q(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 756520 | 1 |
| Bin | 1 | 0 | 1450822 | 1 |
Signal:
RX_SHIFT_REG_Q(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 720758 | 1 |
| Bin | 1 | 0 | 1527004 | 1 |
Signal:
RX_SHIFT_REG_Q(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 765596 | 1 |
| Bin | 1 | 0 | 1536247 | 1 |
Signal:
RX_SHIFT_REG_Q(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 721335 | 1 |
| Bin | 1 | 0 | 1617287 | 1 |
Signal:
RX_SHIFT_REG_Q(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 788309 | 1 |
| Bin | 1 | 0 | 1544140 | 1 |
Signal:
RX_SHIFT_REG_Q(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1291605 | 1 |
| Bin | 1 | 0 | 2231838 | 1 |
Signal:
RX_SHIFT_REG_Q(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 800362 | 1 |
| Bin | 1 | 0 | 1485632 | 1 |
Signal:
RX_SHIFT_REG_Q(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 748554 | 1 |
| Bin | 1 | 0 | 1490404 | 1 |
Signal:
RX_SHIFT_REG_Q(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 857095 | 1 |
| Bin | 1 | 0 | 1398168 | 1 |
Signal:
RX_SHIFT_REG_Q(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 764539 | 1 |
| Bin | 1 | 0 | 1415260 | 1 |
Signal:
RX_SHIFT_REG_Q(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 827969 | 1 |
| Bin | 1 | 0 | 1286814 | 1 |
Signal:
RX_SHIFT_REG_Q(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 785177 | 1 |
| Bin | 1 | 0 | 1377833 | 1 |
Signal:
RX_SHIFT_REG_Q(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 852005 | 1 |
| Bin | 1 | 0 | 1324565 | 1 |
Signal:
RX_SHIFT_REG_Q(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 834900 | 1 |
| Bin | 1 | 0 | 1168195 | 1 |
Signal:
RX_SHIFT_REG_Q(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1068357 | 1 |
| Bin | 1 | 0 | 1079565 | 1 |
Signal:
RX_SHIFT_REG_Q(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 876473 | 1 |
| Bin | 1 | 0 | 1276591 | 1 |
Signal:
RX_SHIFT_REG_Q(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1051105 | 1 |
| Bin | 1 | 0 | 1120047 | 1 |
Signal:
RX_SHIFT_REG_Q(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 912126 | 1 |
| Bin | 1 | 0 | 1296182 | 1 |
Signal:
RX_SHIFT_REG_Q(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1081343 | 1 |
| Bin | 1 | 0 | 1133074 | 1 |
Signal:
RX_SHIFT_REG_Q(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 932226 | 1 |
| Bin | 1 | 0 | 1330255 | 1 |
Signal:
RX_SHIFT_REG_Q(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1115680 | 1 |
| Bin | 1 | 0 | 1176644 | 1 |
Signal:
RX_SHIFT_REG_Q(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 987526 | 1 |
| Bin | 1 | 0 | 1359350 | 1 |
Signal:
RX_SHIFT_REG_Q(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1076044 | 1 |
| Bin | 1 | 0 | 1060727 | 1 |
Signal:
RX_SHIFT_REG_Q(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1073077 | 1 |
| Bin | 1 | 0 | 1141412 | 1 |
Signal:
RX_SHIFT_REG_Q(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1126778 | 1 |
| Bin | 1 | 0 | 1111461 | 1 |
Signal:
RX_SHIFT_REG_Q(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1047270 | 1 |
| Bin | 1 | 0 | 1263068 | 1 |
Signal:
RX_SHIFT_REG_Q(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1741862 | 1 |
| Bin | 1 | 0 | 1618121 | 1 |
Signal:
RX_SHIFT_REG_Q(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1084527 | 1 |
| Bin | 1 | 0 | 1106097 | 1 |
Signal:
RX_SHIFT_REG_Q(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1129593 | 1 |
| Bin | 1 | 0 | 1071794 | 1 |
Signal:
RX_SHIFT_CMD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2782947 | 1 |
| Bin | 1 | 0 | 9714712 | 1 |
Signal:
RX_SHIFT_CMD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2827443 | 1 |
| Bin | 1 | 0 | 9670216 | 1 |
Signal:
RX_SHIFT_CMD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2876978 | 1 |
| Bin | 1 | 0 | 9620681 | 1 |
Signal:
RX_SHIFT_CMD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3011469 | 1 |
| Bin | 1 | 0 | 9486190 | 1 |
Signal:
RX_SHIFT_IN_SEL_DEMUXED(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Signal:
RX_SHIFT_IN_SEL_DEMUXED(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Signal:
RX_SHIFT_IN_SEL_DEMUXED(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
Signal:
REC_IS_RTR_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22038 | 1 |
| Bin | 1 | 0 | 23636 | 1 |
Signal:
REC_FRAME_TYPE_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28440 | 1 |
| Bin | 1 | 0 | 30036 | 1 |
Covered expressions:
"=" expression
222: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 89633 | 1 |
| Bin | True | 70279 | 1 |
"=" expression
222: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 151840 | 1 |
| Bin | True | 8072 | 1 |
"or" expression
222: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0')
<----LHS-----> <---RHS---> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 81561 | 1 |
| Bin | False | True | 8072 | 1 |
| Bin | True | False | 70279 | 1 |
"=" expression
289: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
292: if (rx_store_base_id = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526259831 | 1 |
| Bin | True | 52702 | 1 |
"=" expression
297: if (rx_store_ext_id = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526298366 | 1 |
| Bin | True | 14167 | 1 |
"=" expression
309: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
312: if (rx_store_ide = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526260334 | 1 |
| Bin | True | 52199 | 1 |
"=" expression
323: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
326: if (rx_store_rtr = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526245929 | 1 |
| Bin | True | 66604 | 1 |
"=" expression
333: rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 30040 | 1 |
| Bin | True | 73999 | 1 |
"=" expression
342: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
345: if (rx_store_edl = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526262151 | 1 |
| Bin | True | 50382 | 1 |
"=" expression
359: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
362: if (rx_store_esi = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526284456 | 1 |
| Bin | True | 28077 | 1 |
"=" expression
373: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
376: if (rx_store_brs = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526284404 | 1 |
| Bin | True | 28129 | 1 |
"=" expression
387: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
390: if (rx_store_dlc = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526263187 | 1 |
| Bin | True | 49346 | 1 |
"=" expression
401: if (res_n_i_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052690334 | 1 |
| Bin | True | 2597318 | 1 |
"=" expression
404: if (rx_store_stuff_count = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526299311 | 1 |
| Bin | True | 13222 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: