NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST

File:  /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
RX_SHIFT_RES_REG_INST 100.0 % (6/6) 100.0 % (6/6) 100.0 % (28/28) 100.0 % (2/2) N.A. N.A. 100.0 % (42/42)
RX_SHIFT_CMD_GEN(0) 100.0 % (3/3) 100.0 % (2/2) N.A. 100.0 % (7/7) N.A. N.A. 100.0 % (12/12)
RX_SHIFT_CMD_GEN(1) 100.0 % (3/3) 100.0 % (2/2) N.A. 85.7 % (6/7) N.A. N.A. 91.6 % (11/12)
RX_SHIFT_CMD_GEN(2) 100.0 % (3/3) 100.0 % (2/2) N.A. 85.7 % (6/7) N.A. N.A. 91.6 % (11/12)
RX_SHIFT_CMD_GEN(3) 100.0 % (3/3) 100.0 % (2/2) N.A. 85.7 % (6/7) N.A. N.A. 91.6 % (11/12)
SHIFT_REG_BYTE_INST 100.0 % (30/30) 100.0 % (30/30) 100.0 % (156/156) 100.0 % (22/22) N.A. N.A. 100.0 % (238/238)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST 100.0 % (45/45) 100.0 % (54/54) 100.0 % (324/324) 100.0 % (43/43) N.A. N.A. 100.0 % (466/466)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 222 to 224:

222:    res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') 
223:                     else 
224:                 '1'; 
Count: 160910
Threshold: 1

Signal assignment statement on line 222:

222:    res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') 
Count: 78848
Threshold: 1

Signal assignment statement on line 224:

224:                 '1'; 
Count: 82062
Threshold: 1

Signal assignment statement on line 260:

260:    rec_dlc_d <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
Count: 5004569
Threshold: 1

Signal assignment statement on lines 262 to 263:

262:    rx_shift_in_sel_demuxed <= rx_shift_in_sel & rx_shift_in_sel & 
263:                               rx_shift_in_sel; 
Count: 76842
Threshold: 1

If statement on lines 289 to 301:

289:        if (res_n_i_q_scan = '0') then 
290:            rec_ident <= (others => '0'); 
...
300:            end if; 
301:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 290:

290:            rec_ident <= (others => '0'); 
Count: 2605135
Threshold: 1

If statement on lines 292 to 295:

292:            if (rx_store_base_id = '1') then 
293:                rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <= 
294:                    rx_shift_reg_q(9 downto 0) & rx_data_nbs; 
295:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on lines 293 to 294:

293:                rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <= 
294:                    rx_shift_reg_q(9 downto 0) & rx_data_nbs; 
Count: 53181
Threshold: 1

If statement on lines 297 to 300:

297:            if (rx_store_ext_id = '1') then 
298:                rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <= 
299:                    rx_shift_reg_q(16 downto 0) & rx_data_nbs; 
300:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on lines 298 to 299:

298:                rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <= 
299:                    rx_shift_reg_q(16 downto 0) & rx_data_nbs; 
Count: 15808
Threshold: 1

If statement on lines 309 to 315:

309:        if (res_n_i_q_scan = '0') then 
310:            rec_ident_type <= '0'; 
...
314:            end if; 
315:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 310:

310:            rec_ident_type <= '0'; 
Count: 2605135
Threshold: 1

If statement on lines 312 to 314:

312:            if (rx_store_ide = '1') then 
313:                rec_ident_type <= rx_data_nbs; 
314:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 313:

313:                rec_ident_type <= rx_data_nbs; 
Count: 52832
Threshold: 1

If statement on lines 323 to 329:

323:        if (res_n_i_q_scan = '0') then 
324:            rec_is_rtr_i <= '0'; 
...
328:            end if; 
329:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 324:

324:            rec_is_rtr_i <= '0'; 
Count: 2605135
Threshold: 1

If statement on lines 326 to 328:

326:            if (rx_store_rtr = '1') then 
327:                rec_is_rtr_i <= rx_data_nbs; 
328:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 327:

327:                rec_is_rtr_i <= rx_data_nbs; 
Count: 68716
Threshold: 1

If statement on lines 333 to 335:

333:    rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) 
334:                               else 
335:                  NO_RTR_FRAME; 
Count: 104521
Threshold: 1

Signal assignment statement on line 333:

333:    rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) 
Count: 74036
Threshold: 1

Signal assignment statement on line 335:

335:                  NO_RTR_FRAME; 
Count: 30485
Threshold: 1

If statement on lines 342 to 348:

342:        if (res_n_i_q_scan = '0') then 
343:            rec_frame_type_i <= '0'; 
...
347:            end if; 
348:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 343:

343:            rec_frame_type_i <= '0'; 
Count: 2605135
Threshold: 1

If statement on lines 345 to 347:

345:            if (rx_store_edl = '1') then 
346:                rec_frame_type_i <= rx_data_nbs; 
347:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 346:

346:                rec_frame_type_i <= rx_data_nbs; 
Count: 50792
Threshold: 1

Signal assignment statement on line 351:

351:    rec_frame_type <= rec_frame_type_i; 
Count: 60965
Threshold: 1

If statement on lines 359 to 365:

359:        if (res_n_i_q_scan = '0') then 
360:            rec_esi <= '0'; 
...
364:            end if; 
365:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 360:

360:            rec_esi <= '0'; 
Count: 2605135
Threshold: 1

If statement on lines 362 to 364:

362:            if (rx_store_esi = '1') then 
363:                rec_esi <= rx_data_nbs; 
364:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 363:

363:                rec_esi <= rx_data_nbs; 
Count: 28525
Threshold: 1

If statement on lines 373 to 379:

373:        if (res_n_i_q_scan = '0') then 
374:            rec_brs <= '0'; 
...
378:            end if; 
379:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 374:

374:            rec_brs <= '0'; 
Count: 2605135
Threshold: 1

If statement on lines 376 to 378:

376:            if (rx_store_brs = '1') then 
377:                rec_brs <= rx_data_nbs; 
378:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 377:

377:                rec_brs <= rx_data_nbs; 
Count: 28575
Threshold: 1

If statement on lines 387 to 393:

387:        if (res_n_i_q_scan = '0') then 
388:            rec_dlc <= (others => '0'); 
...
392:            end if; 
393:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 388:

388:            rec_dlc <= (others => '0'); 
Count: 2605135
Threshold: 1

If statement on lines 390 to 392:

390:            if (rx_store_dlc = '1') then 
391:                rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
392:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 391:

391:                rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
Count: 49790
Threshold: 1

If statement on lines 401 to 407:

401:        if (res_n_i_q_scan = '0') then 
402:            rx_stuff_count <= (others => '0'); 
...
406:            end if; 
407:        end if; 
Count: 1090129729
Threshold: 1

Signal assignment statement on line 402:

402:            rx_stuff_count <= (others => '0'); 
Count: 2605135
Threshold: 1

If statement on lines 404 to 406:

404:            if (rx_store_stuff_count = '1') then 
405:                rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
406:            end if; 
Count: 543729433
Threshold: 1

Signal assignment statement on line 405:

405:                rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs; 
Count: 13272
Threshold: 1

Signal assignment statement on line 415:

415:    rx_crc <= rx_shift_reg_q(20 downto 0); 
Count: 4853728
Threshold: 1

Signal assignment statement on line 424:

424:    store_data_word <= rx_shift_reg_q; 
Count: 5849115
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 222:

222:    res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0') 
Evaluated toCountThreshold
BinTrue788481
BinFalse820621

"if" / "when" / "else" condition on line 289:

289:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 291:

291:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 292:

292:            if (rx_store_base_id = '1') then 
Evaluated toCountThreshold
BinTrue531811
BinFalse5436762521

"if" / "when" / "else" condition on line 297:

297:            if (rx_store_ext_id = '1') then 
Evaluated toCountThreshold
BinTrue158081
BinFalse5437136251

"if" / "when" / "else" condition on line 309:

309:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 311:

311:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 312:

312:            if (rx_store_ide = '1') then 
Evaluated toCountThreshold
BinTrue528321
BinFalse5436766011

"if" / "when" / "else" condition on line 323:

323:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 325:

325:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 326:

326:            if (rx_store_rtr = '1') then 
Evaluated toCountThreshold
BinTrue687161
BinFalse5436607171

"if" / "when" / "else" condition on line 333:

333:    rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN) 
Evaluated toCountThreshold
BinTrue740361
BinFalse304851

"if" / "when" / "else" condition on line 342:

342:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 344:

344:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 345:

345:            if (rx_store_edl = '1') then 
Evaluated toCountThreshold
BinTrue507921
BinFalse5436786411

"if" / "when" / "else" condition on line 359:

359:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 361:

361:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 362:

362:            if (rx_store_esi = '1') then 
Evaluated toCountThreshold
BinTrue285251
BinFalse5437009081

"if" / "when" / "else" condition on line 373:

373:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 375:

375:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 376:

376:            if (rx_store_brs = '1') then 
Evaluated toCountThreshold
BinTrue285751
BinFalse5437008581

"if" / "when" / "else" condition on line 387:

387:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 389:

389:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 390:

390:            if (rx_store_dlc = '1') then 
Evaluated toCountThreshold
BinTrue497901
BinFalse5436796431

"if" / "when" / "else" condition on line 401:

401:        if (res_n_i_q_scan = '0') then 
Evaluated toCountThreshold
BinTrue26051351
BinFalse10875245941

"if" / "when" / "else" condition on line 403:

403:        elsif (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue5437294331
BinFalse5437951611

"if" / "when" / "else" condition on line 404:

404:            if (rx_store_stuff_count = '1') then 
Evaluated toCountThreshold
BinTrue132721
BinFalse5437161611

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RES_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 SCAN_ENABLE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_TRIGGER
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_DATA_NBS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_CLEAR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_SHIFT_ENA
ElementFromToCountThresholdExcluded due to
Bin(3)0101Exclude file
Bin(3)1001Exclude file
Bin(2)0101Exclude file
Bin(2)1001Exclude file
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 RX_SHIFT_IN_SEL
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_BASE_ID
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_EXT_ID
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_IDE
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_RTR
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_EDL
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_DLC
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_ESI
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_BRS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_STORE_STUFF_COUNT
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 REC_IDENT
ElementFromToCountThreshold
Bin(28)01379581
Bin(28)10319041
Bin(27)01234511
Bin(27)10184851
Bin(26)01351971
Bin(26)10307341
Bin(25)01234551
Bin(25)10189071
Bin(24)01350241
Bin(24)10301401
Bin(23)01280381
Bin(23)10220731
Bin(22)01381771
Bin(22)10324731
Bin(21)01266661
Bin(21)10213461
Bin(20)01343721
Bin(20)10296801
Bin(19)01268141
Bin(19)10214321
Bin(18)01364751
Bin(18)10315371
Bin(17)0163541
Bin(17)10731341
Bin(16)0176661
Bin(16)10761811
Bin(15)0180761
Bin(15)10763111
Bin(14)0180121
Bin(14)10768701
Bin(13)0160901
Bin(13)10731601
Bin(12)0160631
Bin(12)10727081
Bin(11)0167841
Bin(11)10749631
Bin(10)0174571
Bin(10)10757541
Bin(9)0162221
Bin(9)10729611
Bin(8)0175331
Bin(8)10759531
Bin(7)0181511
Bin(7)10771511
Bin(6)0168151
Bin(6)10742061
Bin(5)0169281
Bin(5)10743001
Bin(4)0175561
Bin(4)10765751
Bin(3)0173271
Bin(3)10755141
Bin(2)0188871
Bin(2)10789801
Bin(1)0177011
Bin(1)10762971
Bin(0)0164731
Bin(0)10738511

Port:

 REC_DLC_D
ElementFromToCountThreshold
Bin(3)015663571
Bin(3)105679501
Bin(2)015776271
Bin(2)105792191
Bin(1)015867711
Bin(1)105883631
Bin(0)0113926771
Bin(0)1013910761

Port:

 REC_DLC
ElementFromToCountThreshold
Bin(3)01213421
Bin(3)10229421
Bin(2)01221081
Bin(2)10237051
Bin(1)01217971
Bin(1)10233941
Bin(0)01285421
Bin(0)10301391

Port:

 REC_IS_RTR
FromToCountThreshold
Bin01218371
Bin10234361

Port:

 REC_IDENT_TYPE
FromToCountThreshold
Bin01176281
Bin10192261

Port:

 REC_FRAME_TYPE
FromToCountThreshold
Bin01288841
Bin10304801

Port:

 REC_BRS
FromToCountThreshold
Bin01203991
Bin10219951

Port:

 REC_ESI
FromToCountThreshold
Bin0125241
Bin1041231

Port:

 STORE_DATA_WORD
ElementFromToCountThreshold
Bin(31)012405821
Bin(31)102421801
Bin(30)012473041
Bin(30)102489011
Bin(29)012585141
Bin(29)102601081
Bin(28)012657521
Bin(28)102673511
Bin(27)012763961
Bin(27)102779931
Bin(26)012844281
Bin(26)102860251
Bin(25)012922581
Bin(25)102938531
Bin(24)013004821
Bin(24)103020811
Bin(23)012885781
Bin(23)102901761
Bin(22)012957441
Bin(22)102973451
Bin(21)013042751
Bin(21)103058701
Bin(20)013118641
Bin(20)103134641
Bin(19)013228641
Bin(19)103244601
Bin(18)013316111
Bin(18)103332071
Bin(17)013377801
Bin(17)103393791
Bin(16)013442331
Bin(16)103458331
Bin(15)013854581
Bin(15)103870571
Bin(14)013991091
Bin(14)104007061
Bin(13)014084321
Bin(13)104100281
Bin(12)014195571
Bin(12)104211531
Bin(11)014319181
Bin(11)104335131
Bin(10)014437371
Bin(10)104453311
Bin(9)014534151
Bin(9)104550121
Bin(8)014653471
Bin(8)104669431
Bin(7)015119841
Bin(7)105135781
Bin(6)015230261
Bin(6)105246191
Bin(5)015342261
Bin(5)105358221
Bin(4)015447241
Bin(4)105463181
Bin(3)015548171
Bin(3)105564101
Bin(2)015663571
Bin(2)105679501
Bin(1)015776271
Bin(1)105792191
Bin(0)015867711
Bin(0)105883631

Port:

 RX_CRC
ElementFromToCountThreshold
Bin(20)016978131
Bin(20)1013802861
Bin(19)016146061
Bin(19)1012367271
Bin(18)016623711
Bin(18)1012008681
Bin(17)016176541
Bin(17)1012027761
Bin(16)0112872601
Bin(16)1020647861
Bin(15)017380021
Bin(15)1011953781
Bin(14)015844641
Bin(14)105597981
Bin(13)015605681
Bin(13)105881601
Bin(12)015968401
Bin(12)105770041
Bin(11)015807161
Bin(11)106070661
Bin(10)016262941
Bin(10)105989611
Bin(9)016038241
Bin(9)106289741
Bin(8)016416941
Bin(8)106184241
Bin(7)015120411
Bin(7)105136691
Bin(6)015230831
Bin(6)105246741
Bin(5)015342631
Bin(5)105358691
Bin(4)015447641
Bin(4)105463731
Bin(3)015548791
Bin(3)105564641
Bin(2)015664711
Bin(2)105680121
Bin(1)015776871
Bin(1)105793201
Bin(0)015868211
Bin(0)105884401

Port:

 RX_STUFF_COUNT
ElementFromToCountThreshold
Bin(3)0136951
Bin(3)1052961
Bin(2)0168751
Bin(2)1084751
Bin(1)0177831
Bin(1)1093811
Bin(0)0164821
Bin(0)1080811

Signal:

 RES_N_I_D
FromToCountThreshold
Bin01788601
Bin10788481

Signal:

 RES_N_I_Q_SCAN
FromToCountThreshold
Bin01638451
Bin10638341

Signal:

 RX_SHIFT_REG_Q
ElementFromToCountThreshold
Bin(31)017977591
Bin(31)1013459151
Bin(30)017384811
Bin(30)1013494171
Bin(29)016779781
Bin(29)1015556541
Bin(28)017601421
Bin(28)1014817441
Bin(27)016960201
Bin(27)1015830151
Bin(26)017746771
Bin(26)1015155311
Bin(25)017018651
Bin(25)1015899441
Bin(24)017845251
Bin(24)1015261511
Bin(23)0112915181
Bin(23)1022246211
Bin(22)017945401
Bin(22)1014773981
Bin(21)017377861
Bin(21)1015140581
Bin(20)018560901
Bin(20)1014257521
Bin(19)017607671
Bin(19)1013829851
Bin(18)018376051
Bin(18)1013295651
Bin(17)017627671
Bin(17)1013502291
Bin(16)018316371
Bin(16)1013081411
Bin(15)018256611
Bin(15)1011601391
Bin(14)0110661531
Bin(14)1010848201
Bin(13)018730221
Bin(13)1012526581
Bin(12)0110542281
Bin(12)1011171511
Bin(11)019008071
Bin(11)1012767651
Bin(10)0110839371
Bin(10)1011664601
Bin(9)019208331
Bin(9)1012931501
Bin(8)0110968851
Bin(8)1011629671
Bin(7)019778281
Bin(7)1013713451
Bin(6)0110737001
Bin(6)1010464271
Bin(5)0110486431
Bin(5)1011450001
Bin(4)0111460151
Bin(4)1010942561
Bin(3)0110469301
Bin(3)1012433141
Bin(2)0117322671
Bin(2)1016313641
Bin(1)0110733891
Bin(1)1011018701
Bin(0)0111233791
Bin(0)1010760521

Signal:

 RX_SHIFT_CMD
ElementFromToCountThreshold
Bin(3)0128131951
Bin(3)1097129241
Bin(2)0128605881
Bin(2)1096655311
Bin(1)0129124851
Bin(1)1096136341
Bin(0)0130475471
Bin(0)1094785721

Signal:

 RX_SHIFT_IN_SEL_DEMUXED
ElementFromToCountThreshold
Bin(3)01368201
Bin(3)10384211
Bin(2)01368201
Bin(2)10384211
Bin(1)01368201
Bin(1)10384211

Signal:

 REC_IS_RTR_I
FromToCountThreshold
Bin01218371
Bin10234361

Signal:

 REC_FRAME_TYPE_I
FromToCountThreshold
Bin01288841
Bin10304801

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 222:

 rx_clear = '1' or res_n = '0' 
 <----LHS----->    <---RHS---> 
LHSRHSCountThreshold
BinFalseFalse820621
BinFalseTrue80721
BinTrueFalse707761

"=" expression on line 222:

 rx_clear = '1' 
Evaluated toCountThreshold
BinFalse901341
BinTrue707761

"=" expression on line 222:

 res_n = '0' 
Evaluated toCountThreshold
BinFalse1528381
BinTrue80721

"=" expression on line 289:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 292:

 rx_store_base_id = '1' 
Evaluated toCountThreshold
BinFalse5436762521
BinTrue531811

"=" expression on line 297:

 rx_store_ext_id = '1' 
Evaluated toCountThreshold
BinFalse5437136251
BinTrue158081

"=" expression on line 309:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 312:

 rx_store_ide = '1' 
Evaluated toCountThreshold
BinFalse5436766011
BinTrue528321

"=" expression on line 323:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 326:

 rx_store_rtr = '1' 
Evaluated toCountThreshold
BinFalse5436607171
BinTrue687161

"=" expression on line 333:

 rec_frame_type_i = NORMAL_CAN 
Evaluated toCountThreshold
BinFalse304851
BinTrue740361

"=" expression on line 342:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 345:

 rx_store_edl = '1' 
Evaluated toCountThreshold
BinFalse5436786411
BinTrue507921

"=" expression on line 359:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 362:

 rx_store_esi = '1' 
Evaluated toCountThreshold
BinFalse5437009081
BinTrue285251

"=" expression on line 373:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 376:

 rx_store_brs = '1' 
Evaluated toCountThreshold
BinFalse5437008581
BinTrue285751

"=" expression on line 387:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 390:

 rx_store_dlc = '1' 
Evaluated toCountThreshold
BinFalse5436796431
BinTrue497901

"=" expression on line 401:

 res_n_i_q_scan = '0' 
Evaluated toCountThreshold
BinFalse10875245941
BinTrue26051351

"=" expression on line 404:

 rx_store_stuff_count = '1' 
Evaluated toCountThreshold
BinFalse5437161611
BinTrue132721

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: