NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.RX_SHIFT_CMD_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	85.7 % (6/7)	N.A.	N.A.	91.6 % (11/12)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.RX_SHIFT_CMD_GEN(1)

100.0 % (3/3)

100.0 % (2/2)

N.A.

85.7 % (6/7)

N.A.

91.6 % (11/12)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 251 to 253:

251:        rx_shift_cmd(i) <= '1' when (rx_trigger = '1' and rx_shift_ena(i) = '1') 
252:                               else 
253:                           '0';

Count: 21008222
Threshold: 1

Signal assignment statement on line 251:

251: rx_shift_cmd(i) <= '1' when (rx_trigger = '1' and rx_shift_ena(i) = '1')
Count: 2909748
Threshold: 1

Signal assignment statement on line 253:

253: '0';
Count: 18098474
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 251:

251: rx_shift_cmd(i) <= '1' when (rx_trigger = '1' and rx_shift_ena(i) = '1')

	Evaluated to	Count	Threshold
Bin	True	2909748	1
Bin	False	18098474	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

"and" expression on line 251:

 rx_trigger = '1' and rx_shift_ena(i) = '1' 
 <-----LHS------>     <--------RHS-------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1

Excluded expressions:

Covered expressions:

"and" expression on line 251:

 rx_trigger = '1' and rx_shift_ena(i) = '1' 
 <-----LHS------>     <--------RHS-------->

	LHS	RHS	Count	Threshold
Bin	True	False	7728021	1
Bin	True	True	2909748	1

"=" expression on line 251:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	10370453	1
Bin	True	10637769	1

"=" expression on line 251:

rx_shift_ena(i) = '1'

	Evaluated to	Count	Threshold
Bin	False	7728021	1
Bin	True	2909748	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.RX_SHIFT_REG_INST.RX_SHIFT_CMD_GEN(1)

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 251 to 253:

Signal assignment statement on line 251:

Signal assignment statement on line 253:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 251:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

"and" expression on line 251:

Excluded expressions:

Covered expressions:

"and" expression on line 251:

"=" expression on line 251:

"=" expression on line 251:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: