NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_17_RX_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (120/120)	100.0 % (21/21)	N.A.	N.A.	100.0 % (169/169)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 6244664
Threshold: 1

If statement:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 13392042
Threshold: 1

Signal assignment statement:

155: crc_d <= (others => '0');
Count: 205223
Threshold: 1

Signal assignment statement:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 205223
Threshold: 1

Signal assignment statement:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 6633708
Threshold: 1

Signal assignment statement:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 6553111
Threshold: 1

If statement:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 22330801
Threshold: 1

Signal assignment statement:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 112514
Threshold: 1

Signal assignment statement:

166: '1' when (enable = '1' and trig = '1') else
Count: 6895167
Threshold: 1

Signal assignment statement:

167: '0';
Count: 15323120
Threshold: 1

If statement:

174:        if (res_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

175: crc_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

178: crc_q <= crc_d;
Count: 6966803
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	205223	1
Bin	False	13186819	1

"if" / "when" / "else" condition:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	6633708	1
Bin	False	6553111	1

"if" / "when" / "else" condition:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	112514	1
Bin	False	22218287	1

"if" / "when" / "else" condition:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6895167	1
Bin	False	15323120	1

"if" / "when" / "else" condition:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	6966803	1
Bin	False	519407497	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

DATA_IN

	From	To	Count	Threshold
Bin	0	1	1387496	1
Bin	1	0	1385896	1

Port:

TRIG

	From	To	Count	Threshold
Bin	0	1	11043148	1
Bin	1	0	11044748	1

Port:

ENABLE

	From	To	Count	Threshold
Bin	0	1	61272	1
Bin	1	0	62872	1

Port:

INIT_VECT_MSB

	From	To	Count	Threshold
Bin	0	1	1730	1
Bin	1	0	1730	1

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold
Bin	0	1	112514	1
Bin	1	0	114114	1

Port:

CRC(16)

	From	To	Count	Threshold
Bin	0	1	1734039	1
Bin	1	0	1735633	1

Port:

CRC(15)

	From	To	Count	Threshold
Bin	0	1	1744508	1
Bin	1	0	1746106	1

Port:

CRC(14)

	From	To	Count	Threshold
Bin	0	1	1759054	1
Bin	1	0	1760651	1

Port:

CRC(13)

	From	To	Count	Threshold
Bin	0	1	1757156	1
Bin	1	0	1758753	1

Port:

CRC(12)

	From	To	Count	Threshold
Bin	0	1	1695908	1
Bin	1	0	1697506	1

Port:

CRC(11)

	From	To	Count	Threshold
Bin	0	1	1710517	1
Bin	1	0	1712115	1

Port:

CRC(10)

	From	To	Count	Threshold
Bin	0	1	1657718	1
Bin	1	0	1659317	1

Port:

CRC(9)

	From	To	Count	Threshold
Bin	0	1	1671362	1
Bin	1	0	1672959	1

Port:

CRC(8)

	From	To	Count	Threshold
Bin	0	1	1685982	1
Bin	1	0	1687581	1

Port:

CRC(7)

	From	To	Count	Threshold
Bin	0	1	1699437	1
Bin	1	0	1701036	1

Port:

CRC(6)

	From	To	Count	Threshold
Bin	0	1	1713617	1
Bin	1	0	1715217	1

Port:

CRC(5)

	From	To	Count	Threshold
Bin	0	1	1713382	1
Bin	1	0	1714978	1

Port:

CRC(4)

	From	To	Count	Threshold
Bin	0	1	1725540	1
Bin	1	0	1727138	1

Port:

CRC(3)

	From	To	Count	Threshold
Bin	0	1	1744070	1
Bin	1	0	1745668	1

Port:

CRC(2)

	From	To	Count	Threshold
Bin	0	1	1713985	1
Bin	1	0	1715584	1

Port:

CRC(1)

	From	To	Count	Threshold
Bin	0	1	1729286	1
Bin	1	0	1730885	1

Port:

CRC(0)

	From	To	Count	Threshold
Bin	0	1	1757719	1
Bin	1	0	1759317	1

Signal:

CRC_Q(16)

	From	To	Count	Threshold
Bin	0	1	3542232	1
Bin	1	0	3379981	1

Signal:

CRC_Q(15)

	From	To	Count	Threshold
Bin	0	1	1744508	1
Bin	1	0	1753320	1

Signal:

CRC_Q(14)

	From	To	Count	Threshold
Bin	0	1	1759054	1
Bin	1	0	1769413	1

Signal:

CRC_Q(13)

	From	To	Count	Threshold
Bin	0	1	1757156	1
Bin	1	0	1767092	1

Signal:

CRC_Q(12)

	From	To	Count	Threshold
Bin	0	1	1695908	1
Bin	1	0	1705972	1

Signal:

CRC_Q(11)

	From	To	Count	Threshold
Bin	0	1	1710517	1
Bin	1	0	1719751	1

Signal:

CRC_Q(10)

	From	To	Count	Threshold
Bin	0	1	1657718	1
Bin	1	0	1666644	1

Signal:

CRC_Q(9)

	From	To	Count	Threshold
Bin	0	1	1671362	1
Bin	1	0	1680340	1

Signal:

CRC_Q(8)

	From	To	Count	Threshold
Bin	0	1	1685982	1
Bin	1	0	1696282	1

Signal:

CRC_Q(7)

	From	To	Count	Threshold
Bin	0	1	1699437	1
Bin	1	0	1709826	1

Signal:

CRC_Q(6)

	From	To	Count	Threshold
Bin	0	1	1713617	1
Bin	1	0	1723547	1

Signal:

CRC_Q(5)

	From	To	Count	Threshold
Bin	0	1	1713382	1
Bin	1	0	1723731	1

Signal:

CRC_Q(4)

	From	To	Count	Threshold
Bin	0	1	1725540	1
Bin	1	0	1734641	1

Signal:

CRC_Q(3)

	From	To	Count	Threshold
Bin	0	1	1744070	1
Bin	1	0	1754224	1

Signal:

CRC_Q(2)

	From	To	Count	Threshold
Bin	0	1	1713985	1
Bin	1	0	1723298	1

Signal:

CRC_Q(1)

	From	To	Count	Threshold
Bin	0	1	1729286	1
Bin	1	0	1738106	1

Signal:

CRC_Q(0)

	From	To	Count	Threshold
Bin	0	1	1757719	1
Bin	1	0	1768021	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	3121529	1
Bin	1	0	3119935	1

Signal:

CRC_D(16)

	From	To	Count	Threshold
Bin	0	1	6723309	1
Bin	1	0	6566512	1

Signal:

CRC_D(15)

	From	To	Count	Threshold
Bin	0	1	1759056	1
Bin	1	0	1837992	1

Signal:

CRC_D(14)

	From	To	Count	Threshold
Bin	0	1	4867813	1
Bin	1	0	4958622	1

Signal:

CRC_D(13)

	From	To	Count	Threshold
Bin	0	1	4806177	1
Bin	1	0	4895230	1

Signal:

CRC_D(12)

	From	To	Count	Threshold
Bin	0	1	1710517	1
Bin	1	0	1787359	1

Signal:

CRC_D(11)

	From	To	Count	Threshold
Bin	0	1	4768063	1
Bin	1	0	4854961	1

Signal:

CRC_D(10)

	From	To	Count	Threshold
Bin	0	1	1671365	1
Bin	1	0	1745238	1

Signal:

CRC_D(9)

	From	To	Count	Threshold
Bin	0	1	1685984	1
Bin	1	0	1765629	1

Signal:

CRC_D(8)

	From	To	Count	Threshold
Bin	0	1	1699441	1
Bin	1	0	1778935	1

Signal:

CRC_D(7)

	From	To	Count	Threshold
Bin	0	1	1713621	1
Bin	1	0	1795658	1

Signal:

CRC_D(6)

	From	To	Count	Threshold
Bin	0	1	4823400	1
Bin	1	0	4913834	1

Signal:

CRC_D(5)

	From	To	Count	Threshold
Bin	0	1	1725544	1
Bin	1	0	1794729	1

Signal:

CRC_D(4)

	From	To	Count	Threshold
Bin	0	1	4853893	1
Bin	1	0	4943183	1

Signal:

CRC_D(3)

	From	To	Count	Threshold
Bin	0	1	4823798	1
Bin	1	0	4901923	1

Signal:

CRC_D(2)

	From	To	Count	Threshold
Bin	0	1	1729290	1
Bin	1	0	1808856	1

Signal:

CRC_D(1)

	From	To	Count	Threshold
Bin	0	1	4867954	1
Bin	1	0	4962733	1

Signal:

CRC_D(0)

	From	To	Count	Threshold
Bin	0	1	3122203	1
Bin	1	0	3198009	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	7007681	1
Bin	1	0	7009281	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

150:    crc_nxt         <= data_in xor crc_q(G_CRC_WIDTH - 1); 
                           <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1531263	1
Bin	'0'	'1'	1606337	1
Bin	'1'	'0'	1515192	1
Bin	'1'	'1'	1588672	1

"=" expression

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	False	13186819	1
Bin	True	205223	1

"=" expression

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	False	6553111	1
Bin	True	6633708	1

"=" expression

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	False	22218287	1
Bin	True	112514	1

"=" expression

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	False	8424836	1
Bin	True	13793451	1

"=" expression

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	False	11170948	1
Bin	True	11047339	1

"and" expression

166:              '1' when (enable = '1' and trig = '1') else 
                            <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4152172	1
Bin	True	False	6898284	1
Bin	True	True	6895167	1

"=" expression

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	519407497	1
Bin	True	6966803	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_17_RX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal: