NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_TX_ARBITRATOR_INST.G_EACH_BUF(5).FUNC_COV_TX_ARBITRATOR_PER_BUF_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_tx_arbitrator_per_buf.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_TX_ARBITRATOR_INST.G_EACH_BUF(5).FUNC_COV_TX_ARBITRATOR_PER_BUF_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (3/3) 100.0 % (5/5)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin01176844351
Bin10176846001

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

122:    -- psl txt_lock_buf_cov : cover 
123:    --    {curr_txtb_index_i = G_TXT_BUF_INDEX and txtb_hw_cmd.lock = '1'}; 
Count: 202
Threshold: 1

PSL cover point:

125:    -- psl txt_unlock_buf_cov : cover 
126:    --    {curr_txtb_index_i = 0 and txtb_hw_cmd_unlock = '1'}; 
Count: 1456
Threshold: 1

PSL cover point:

131:    -- psl buf_ready_to_not_ready_cov : cover 
132:    --    {txtb_available(G_TXT_BUF_INDEX) = '1' and select_buf_index = G_TXT_BUF_INDEX and 
133:    --     txtb_hw_cmd.lock = '0'; txtb_available(G_TXT_BUF_INDEX) = '0'} 
134:    --    report "Buffer became non-ready but not due to lock command"; 
Count: 45
Threshold: 1