NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_15_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (108/108)	100.0 % (21/21)	N.A.	N.A.	100.0 % (157/157)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 5679117
Threshold: 1

If statement:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 11700184
Threshold: 1

Signal assignment statement:

155: crc_d <= (others => '0');
Count: 193351
Threshold: 1

Signal assignment statement:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 193351
Threshold: 1

Signal assignment statement:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 5858973
Threshold: 1

Signal assignment statement:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 5647860
Threshold: 1

If statement:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 20812265
Threshold: 1

Signal assignment statement:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 112514
Threshold: 1

Signal assignment statement:

166: '1' when (enable = '1' and trig = '1') else
Count: 6194473
Threshold: 1

Signal assignment statement:

167: '0';
Count: 14505278
Threshold: 1

If statement:

174:        if (res_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

175: crc_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

178: crc_q <= crc_d;
Count: 6038940
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	193351	1
Bin	False	11506833	1

"if" / "when" / "else" condition:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	5858973	1
Bin	False	5647860	1

"if" / "when" / "else" condition:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	112514	1
Bin	False	20699751	1

"if" / "when" / "else" condition:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6194473	1
Bin	False	14505278	1

"if" / "when" / "else" condition:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	6038940	1
Bin	False	520335360	1

Uncovered toggles:

Excluded toggles:

Port:

INIT_VECT_MSB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

DATA_IN

	From	To	Count	Threshold
Bin	0	1	1386117	1
Bin	1	0	1384517	1

Port:

TRIG

	From	To	Count	Threshold
Bin	0	1	10305150	1
Bin	1	0	10306749	1

Port:

ENABLE

	From	To	Count	Threshold
Bin	0	1	55285	1
Bin	1	0	56885	1

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold
Bin	0	1	112514	1
Bin	1	0	114114	1

Port:

CRC(14)

	From	To	Count	Threshold
Bin	0	1	1452642	1
Bin	1	0	1454241	1

Port:

CRC(13)

	From	To	Count	Threshold
Bin	0	1	1404381	1
Bin	1	0	1405979	1

Port:

CRC(12)

	From	To	Count	Threshold
Bin	0	1	1416815	1
Bin	1	0	1418414	1

Port:

CRC(11)

	From	To	Count	Threshold
Bin	0	1	1431040	1
Bin	1	0	1432636	1

Port:

CRC(10)

	From	To	Count	Threshold
Bin	0	1	1444591	1
Bin	1	0	1446189	1

Port:

CRC(9)

	From	To	Count	Threshold
Bin	0	1	1438246	1
Bin	1	0	1439842	1

Port:

CRC(8)

	From	To	Count	Threshold
Bin	0	1	1452223	1
Bin	1	0	1453819	1

Port:

CRC(7)

	From	To	Count	Threshold
Bin	0	1	1489085	1
Bin	1	0	1490683	1

Port:

CRC(6)

	From	To	Count	Threshold
Bin	0	1	1428572	1
Bin	1	0	1430168	1

Port:

CRC(5)

	From	To	Count	Threshold
Bin	0	1	1442138	1
Bin	1	0	1443734	1

Port:

CRC(4)

	From	To	Count	Threshold
Bin	0	1	1454104	1
Bin	1	0	1455703	1

Port:

CRC(3)

	From	To	Count	Threshold
Bin	0	1	1453743	1
Bin	1	0	1455342	1

Port:

CRC(2)

	From	To	Count	Threshold
Bin	0	1	1440570	1
Bin	1	0	1442165	1

Port:

CRC(1)

	From	To	Count	Threshold
Bin	0	1	1456437	1
Bin	1	0	1458034	1

Port:

CRC(0)

	From	To	Count	Threshold
Bin	0	1	1470076	1
Bin	1	0	1471674	1

Signal:

CRC_Q(14)

	From	To	Count	Threshold
Bin	0	1	2877856	1
Bin	1	0	2918278	1

Signal:

CRC_Q(13)

	From	To	Count	Threshold
Bin	0	1	1404381	1
Bin	1	0	1406014	1

Signal:

CRC_Q(12)

	From	To	Count	Threshold
Bin	0	1	1416815	1
Bin	1	0	1418414	1

Signal:

CRC_Q(11)

	From	To	Count	Threshold
Bin	0	1	1431040	1
Bin	1	0	1432636	1

Signal:

CRC_Q(10)

	From	To	Count	Threshold
Bin	0	1	1444591	1
Bin	1	0	1446189	1

Signal:

CRC_Q(9)

	From	To	Count	Threshold
Bin	0	1	1438246	1
Bin	1	0	1439842	1

Signal:

CRC_Q(8)

	From	To	Count	Threshold
Bin	0	1	1452223	1
Bin	1	0	1453819	1

Signal:

CRC_Q(7)

	From	To	Count	Threshold
Bin	0	1	1489085	1
Bin	1	0	1490683	1

Signal:

CRC_Q(6)

	From	To	Count	Threshold
Bin	0	1	1428572	1
Bin	1	0	1430168	1

Signal:

CRC_Q(5)

	From	To	Count	Threshold
Bin	0	1	1442138	1
Bin	1	0	1443734	1

Signal:

CRC_Q(4)

	From	To	Count	Threshold
Bin	0	1	1454104	1
Bin	1	0	1455703	1

Signal:

CRC_Q(3)

	From	To	Count	Threshold
Bin	0	1	1453743	1
Bin	1	0	1455342	1

Signal:

CRC_Q(2)

	From	To	Count	Threshold
Bin	0	1	1440570	1
Bin	1	0	1442165	1

Signal:

CRC_Q(1)

	From	To	Count	Threshold
Bin	0	1	1456437	1
Bin	1	0	1458034	1

Signal:

CRC_Q(0)

	From	To	Count	Threshold
Bin	0	1	1470076	1
Bin	1	0	1471674	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	2838758	1
Bin	1	0	2837159	1

Signal:

CRC_D(14)

	From	To	Count	Threshold
Bin	0	1	5833793	1
Bin	1	0	5782218	1

Signal:

CRC_D(13)

	From	To	Count	Threshold
Bin	0	1	1416817	1
Bin	1	0	1418455	1

Signal:

CRC_D(12)

	From	To	Count	Threshold
Bin	0	1	1431041	1
Bin	1	0	1432637	1

Signal:

CRC_D(11)

	From	To	Count	Threshold
Bin	0	1	1444594	1
Bin	1	0	1446192	1

Signal:

CRC_D(10)

	From	To	Count	Threshold
Bin	0	1	4347883	1
Bin	1	0	4347924	1

Signal:

CRC_D(9)

	From	To	Count	Threshold
Bin	0	1	1452224	1
Bin	1	0	1453820	1

Signal:

CRC_D(8)

	From	To	Count	Threshold
Bin	0	1	4399612	1
Bin	1	0	4399607	1

Signal:

CRC_D(7)

	From	To	Count	Threshold
Bin	0	1	4337993	1
Bin	1	0	4338034	1

Signal:

CRC_D(6)

	From	To	Count	Threshold
Bin	0	1	1442139	1
Bin	1	0	1443735	1

Signal:

CRC_D(5)

	From	To	Count	Threshold
Bin	0	1	1454106	1
Bin	1	0	1455705	1

Signal:

CRC_D(4)

	From	To	Count	Threshold
Bin	0	1	4364503	1
Bin	1	0	4364499	1

Signal:

CRC_D(3)

	From	To	Count	Threshold
Bin	0	1	4351770	1
Bin	1	0	4351812	1

Signal:

CRC_D(2)

	From	To	Count	Threshold
Bin	0	1	1456439	1
Bin	1	0	1458036	1

Signal:

CRC_D(1)

	From	To	Count	Threshold
Bin	0	1	1470078	1
Bin	1	0	1471676	1

Signal:

CRC_D(0)

	From	To	Count	Threshold
Bin	0	1	2923505	1
Bin	1	0	2923500	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	6306987	1
Bin	1	0	6308587	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

150:    crc_nxt         <= data_in xor crc_q(G_CRC_WIDTH - 1); 
                           <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1440395	1
Bin	'0'	'1'	1383571	1
Bin	'1'	'0'	1455187	1
Bin	'1'	'1'	1396764	1

"=" expression

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	False	11506833	1
Bin	True	193351	1

"=" expression

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	False	5647860	1
Bin	True	5858973	1

"=" expression

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	False	20699751	1
Bin	True	112514	1

"=" expression

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	False	8328725	1
Bin	True	12371026	1

"=" expression

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	False	10405925	1
Bin	True	10293826	1

"and" expression

166:              '1' when (enable = '1' and trig = '1') else 
                            <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4099353	1
Bin	True	False	6176553	1
Bin	True	True	6194473	1

"=" expression

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	520335360	1
Bin	True	6038940	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_15_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

If statement:

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If statement:

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If statement:

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If statement:

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Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Port:

Covered toggles:

Port:

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