NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_15_INST	100.0 % (15/15)	100.0 % (14/14)	100.0 % (108/108)	100.0 % (21/21)	N.A.	N.A.	100.0 % (158/158)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_15_INST

100.0 % (15/15)

100.0 % (14/14)

100.0 % (108/108)

100.0 % (21/21)

N.A.

100.0 % (158/158)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

150: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
Count: 5693475
Threshold: 1

If statement on lines 154 to 162:

154:        if (load_init_vect = '1') then 
155:            crc_d <= (others => '0'); 
...
161:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0'); 
162:        end if;

Count: 11734643
Threshold: 1

Signal assignment statement on line 155:

155: crc_d <= (others => '0');
Count: 196307
Threshold: 1

Signal assignment statement on line 156:

156: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
Count: 196307
Threshold: 1

Signal assignment statement on lines 158 to 159:

158:            crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor 
159:                      G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);

Count: 5878576
Threshold: 1

Signal assignment statement on line 161:

161: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
Count: 5659760
Threshold: 1

If statement on lines 165 to 167:

165:    crc_ce <= '1' when (load_init_vect = '1') else 
166:              '1' when (enable = '1' and trig = '1') else 
167:              '0';

Count: 21497962
Threshold: 1

Signal assignment statement on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else
Count: 113459
Threshold: 1

Signal assignment statement on line 166:

166: '1' when (enable = '1' and trig = '1') else
Count: 6212302
Threshold: 1

Signal assignment statement on line 167:

167: '0';
Count: 15172201
Threshold: 1

If statement on lines 174 to 180:

174:        if (res_n = '0') then 
175:            crc_q             <= (others => '0'); 
...
179:            end if; 
180:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 175:

175: crc_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 177 to 179:

177:            if (crc_ce = '1') then 
178:                crc_q <= crc_d; 
179:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 178:

178: crc_q <= crc_d;
Count: 6057816
Threshold: 1

Signal assignment statement on line 184:

184: crc <= crc_q;
Count: 5815949
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

154: if (load_init_vect = '1') then

	Evaluated to	Count	Threshold
Bin	True	196307	1
Bin	False	11538336	1

"if" / "when" / "else" condition on line 157:

157: elsif (crc_nxt = '1') then

	Evaluated to	Count	Threshold
Bin	True	5878576	1
Bin	False	5659760	1

"if" / "when" / "else" condition on line 165:

165: crc_ce <= '1' when (load_init_vect = '1') else

	Evaluated to	Count	Threshold
Bin	True	113459	1
Bin	False	21384503	1

"if" / "when" / "else" condition on line 166:

166: '1' when (enable = '1' and trig = '1') else

	Evaluated to	Count	Threshold
Bin	True	6212302	1
Bin	False	15172201	1

"if" / "when" / "else" condition on line 174:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 176:

176: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 177:

177: if (crc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	6057816	1
Bin	False	537733862	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DATA_IN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRIG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INIT_VECT_MSB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOAD_INIT_VECT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

CRC

	Element	From	To	Count	Threshold
Bin	(14)	0	1	1456224	1
Bin	(14)	1	0	1457824	1
Bin	(13)	0	1	1412724	1
Bin	(13)	1	0	1414324	1
Bin	(12)	0	1	1427215	1
Bin	(12)	1	0	1428815	1
Bin	(11)	0	1	1440985	1
Bin	(11)	1	0	1442580	1
Bin	(10)	0	1	1455761	1
Bin	(10)	1	0	1457360	1
Bin	(9)	0	1	1446457	1
Bin	(9)	1	0	1448054	1
Bin	(8)	0	1	1461592	1
Bin	(8)	1	0	1463189	1
Bin	(7)	0	1	1492415	1
Bin	(7)	1	0	1494015	1
Bin	(6)	0	1	1426024	1
Bin	(6)	1	0	1427621	1
Bin	(5)	0	1	1440703	1
Bin	(5)	1	0	1442299	1
Bin	(4)	0	1	1453240	1
Bin	(4)	1	0	1454838	1
Bin	(3)	0	1	1455932	1
Bin	(3)	1	0	1457530	1
Bin	(2)	0	1	1446410	1
Bin	(2)	1	0	1448008	1
Bin	(1)	0	1	1462137	1
Bin	(1)	1	0	1463734	1
Bin	(0)	0	1	1474486	1
Bin	(0)	1	0	1476084	1

Signal:

CRC_Q

	Element	From	To	Count	Threshold
Bin	(14)	0	1	2887194	1
Bin	(14)	1	0	2927154	1
Bin	(13)	0	1	1412724	1
Bin	(13)	1	0	1414351	1
Bin	(12)	0	1	1427215	1
Bin	(12)	1	0	1428815	1
Bin	(11)	0	1	1440985	1
Bin	(11)	1	0	1442580	1
Bin	(10)	0	1	1455761	1
Bin	(10)	1	0	1457360	1
Bin	(9)	0	1	1446457	1
Bin	(9)	1	0	1448054	1
Bin	(8)	0	1	1461592	1
Bin	(8)	1	0	1463189	1
Bin	(7)	0	1	1492415	1
Bin	(7)	1	0	1494015	1
Bin	(6)	0	1	1426024	1
Bin	(6)	1	0	1427621	1
Bin	(5)	0	1	1440703	1
Bin	(5)	1	0	1442299	1
Bin	(4)	0	1	1453240	1
Bin	(4)	1	0	1454838	1
Bin	(3)	0	1	1455932	1
Bin	(3)	1	0	1457530	1
Bin	(2)	0	1	1446410	1
Bin	(2)	1	0	1448008	1
Bin	(1)	0	1	1462137	1
Bin	(1)	1	0	1463734	1
Bin	(0)	0	1	1474486	1
Bin	(0)	1	0	1476084	1

Signal:

CRC_NXT

	From	To	Count	Threshold
Bin	0	1	2845936	1
Bin	1	0	2844337	1

Signal:

CRC_D

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5849385	1
Bin	(14)	1	0	5799083	1
Bin	(13)	0	1	1427218	1
Bin	(13)	1	0	1428849	1
Bin	(12)	0	1	1440986	1
Bin	(12)	1	0	1442581	1
Bin	(11)	0	1	1455761	1
Bin	(11)	1	0	1457360	1
Bin	(10)	0	1	4364052	1
Bin	(10)	1	0	4364079	1
Bin	(9)	0	1	1461595	1
Bin	(9)	1	0	1463192	1
Bin	(8)	0	1	4410067	1
Bin	(8)	1	0	4410065	1
Bin	(7)	0	1	4342534	1
Bin	(7)	1	0	4342561	1
Bin	(6)	0	1	1440704	1
Bin	(6)	1	0	1442300	1
Bin	(5)	0	1	1453241	1
Bin	(5)	1	0	1454839	1
Bin	(4)	0	1	4374226	1
Bin	(4)	1	0	4374224	1
Bin	(3)	0	1	4364925	1
Bin	(3)	1	0	4364953	1
Bin	(2)	0	1	1462138	1
Bin	(2)	1	0	1463735	1
Bin	(1)	0	1	1474489	1
Bin	(1)	1	0	1476087	1
Bin	(0)	0	1	2930093	1
Bin	(0)	1	0	2930090	1

Signal:

CRC_CE

	From	To	Count	Threshold
Bin	0	1	6325761	1
Bin	1	0	6327362	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

 data_in xor crc_q(G_CRC_WIDTH - 1) 
 <-LHS->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1440164	1
Bin	'0'	'1'	1389993	1
Bin	'1'	'0'	1455943	1
Bin	'1'	'1'	1404173	1

"=" expression on line 154:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	11538336	1
Bin	True	196307	1

"=" expression on line 157:

crc_nxt = '1'

	Evaluated to	Count	Threshold
Bin	False	5659760	1
Bin	True	5878576	1

"=" expression on line 165:

load_init_vect = '1'

	Evaluated to	Count	Threshold
Bin	False	21384503	1
Bin	True	113459	1

"and" expression on line 166:

 enable = '1' and trig = '1' 
 <---LHS---->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	False	True	4423333	1
Bin	True	False	6194466	1
Bin	True	True	6212302	1

"=" expression on line 166:

enable = '1'

	Evaluated to	Count	Threshold
Bin	False	8977735	1
Bin	True	12406768	1

"=" expression on line 166:

trig = '1'

	Evaluated to	Count	Threshold
Bin	False	10748868	1
Bin	True	10635635	1

"=" expression on line 174:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 177:

crc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	537733862	1
Bin	True	6057816	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.CAN_CRC_INST.CRC_CALC_15_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 150:

If statement on lines 154 to 162:

Signal assignment statement on line 155:

Signal assignment statement on line 156:

Signal assignment statement on lines 158 to 159:

Signal assignment statement on line 161:

If statement on lines 165 to 167:

Signal assignment statement on line 165:

Signal assignment statement on line 166:

Signal assignment statement on line 167:

If statement on lines 174 to 180:

Signal assignment statement on line 175:

If statement on lines 177 to 179:

Signal assignment statement on line 178:

Signal assignment statement on line 184:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 154:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 165:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 176:

"if" / "when" / "else" condition on line 177:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression on line 150:

"=" expression on line 154:

"=" expression on line 157:

"=" expression on line 165:

"and" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 174:

"=" expression on line 177:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: