NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CLK_GATE_TXT_BUFFER_RAM_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (23/23)
TXT_BUFFER_RAM_INST	100.0 % (52/52)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2304/2308)
TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CLK_GATE_TXT_BUFFER_RAM_COMP

100.0 % (3/3)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (23/23)

TXT_BUFFER_RAM_INST

100.0 % (52/52)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2304/2308)

TXT_BUFFER_FSM_INST

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST	100.0 % (32/32)	100.0 % (20/20)	100.0 % (462/462)	100.0 % (53/53)	N.A.	N.A.	100.0 % (567/567)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST

100.0 % (32/32)

100.0 % (20/20)

100.0 % (462/462)

100.0 % (53/53)

N.A.

100.0 % (567/567)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

246:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
247:                             else 
248:                         '0';

Count: 23436
Threshold: 1

Signal assignment statement on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 11285
Threshold: 1

Signal assignment statement on line 248:

248: '0';
Count: 12151
Threshold: 1

If statement on lines 259 to 261:

259:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
260:                                                   else 
261:                                    (others => '0');

Count: 5157
Threshold: 1

Signal assignment statement on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 1660
Threshold: 1

Signal assignment statement on line 261:

261: (others => '0');
Count: 3497
Threshold: 1

If statement on lines 269 to 273:

269:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
270:                           else 
271:                       '1' when (mr_tst_control_tmaena = '1') 
272:                           else 
273:                       '0';

Count: 41330
Threshold: 1

Signal assignment statement on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 20095
Threshold: 1

Signal assignment statement on line 271:

271: '1' when (mr_tst_control_tmaena = '1')
Count: 240
Threshold: 1

Signal assignment statement on line 273:

273: '0';
Count: 20995
Threshold: 1

If statement on lines 280 to 284:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID) 
283:                                     else 
284:                                 '0';

Count: 44728
Threshold: 1

Signal assignment statement on line 280:

280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 91
Threshold: 1

Signal assignment statement on line 284:

284: '0';
Count: 44637
Threshold: 1

Signal assignment statement on line 286:

286: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 512
Threshold: 1

If statement on lines 294 to 302:

294:        if (res_n = '0') then 
295:            mr_tx_command_txce_q <= '0'; 
...
301:            mr_tx_command_txca_q <= mr_tx_command_txca; 
302:        end if;

Count: 35169394
Threshold: 1

Signal assignment statement on line 295:

295: mr_tx_command_txce_q <= '0';
Count: 760504
Threshold: 1

Signal assignment statement on line 296:

296: mr_tx_command_txcr_q <= '0';
Count: 760504
Threshold: 1

Signal assignment statement on line 297:

297: mr_tx_command_txca_q <= '0';
Count: 760504
Threshold: 1

Signal assignment statement on line 299:

299: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 17204001
Threshold: 1

Signal assignment statement on line 300:

300: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 17204001
Threshold: 1

Signal assignment statement on line 301:

301: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 17204001
Threshold: 1

If statement on lines 305 to 307:

305:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
306:                                 else 
307:                             '0';

Count: 925
Threshold: 1

Signal assignment statement on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 24
Threshold: 1

Signal assignment statement on line 307:

307: '0';
Count: 901
Threshold: 1

If statement on lines 308 to 310:

308:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
309:                                 else 
310:                             '0';

Count: 6329
Threshold: 1

Signal assignment statement on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 260
Threshold: 1

Signal assignment statement on line 310:

310: '0';
Count: 6069
Threshold: 1

If statement on lines 312 to 314:

312:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
313:                         else 
314:                     '0';

Count: 1677
Threshold: 1

Signal assignment statement on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 46
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 1631
Threshold: 1

Signal assignment statement on line 317:

317: abort_or_skipped <= abort_applied;
Count: 422
Threshold: 1

Signal assignment statement on line 405:

405: txtb_parity_mismatch <= parity_mismatch;
Count: 1222
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	11285	1
Bin	False	12151	1

"if" / "when" / "else" condition on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	1660	1
Bin	False	3497	1

"if" / "when" / "else" condition on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	20095	1
Bin	False	21235	1

"if" / "when" / "else" condition on line 271:

271: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	240	1
Bin	False	20995	1

"if" / "when" / "else" condition on lines 280 to 282:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	91	1
Bin	False	44637	1

"if" / "when" / "else" condition on line 294:

294: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	760504	1
Bin	False	34408890	1

"if" / "when" / "else" condition on line 298:

298: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	17204001	1
Bin	False	17204889	1

"if" / "when" / "else" condition on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	24	1
Bin	False	901	1

"if" / "when" / "else" condition on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	260	1
Bin	False	6069	1

"if" / "when" / "else" condition on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	46	1
Bin	False	1631	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	122	1
Bin	(31)	1	0	287	1
Bin	(30)	0	1	124	1
Bin	(30)	1	0	289	1
Bin	(29)	0	1	119	1
Bin	(29)	1	0	284	1
Bin	(28)	0	1	131	1
Bin	(28)	1	0	296	1
Bin	(27)	0	1	131	1
Bin	(27)	1	0	296	1
Bin	(26)	0	1	134	1
Bin	(26)	1	0	299	1
Bin	(25)	0	1	137	1
Bin	(25)	1	0	302	1
Bin	(24)	0	1	134	1
Bin	(24)	1	0	299	1
Bin	(23)	0	1	143	1
Bin	(23)	1	0	308	1
Bin	(22)	0	1	130	1
Bin	(22)	1	0	295	1
Bin	(21)	0	1	135	1
Bin	(21)	1	0	300	1
Bin	(20)	0	1	143	1
Bin	(20)	1	0	308	1
Bin	(19)	0	1	131	1
Bin	(19)	1	0	296	1
Bin	(18)	0	1	138	1
Bin	(18)	1	0	303	1
Bin	(17)	0	1	134	1
Bin	(17)	1	0	299	1
Bin	(16)	0	1	115	1
Bin	(16)	1	0	280	1
Bin	(15)	0	1	135	1
Bin	(15)	1	0	300	1
Bin	(14)	0	1	113	1
Bin	(14)	1	0	278	1
Bin	(13)	0	1	125	1
Bin	(13)	1	0	290	1
Bin	(12)	0	1	122	1
Bin	(12)	1	0	287	1
Bin	(11)	0	1	126	1
Bin	(11)	1	0	291	1
Bin	(10)	0	1	125	1
Bin	(10)	1	0	290	1
Bin	(9)	0	1	129	1
Bin	(9)	1	0	294	1
Bin	(8)	0	1	131	1
Bin	(8)	1	0	296	1
Bin	(7)	0	1	135	1
Bin	(7)	1	0	300	1
Bin	(6)	0	1	132	1
Bin	(6)	1	0	297	1
Bin	(5)	0	1	129	1
Bin	(5)	1	0	294	1
Bin	(4)	0	1	123	1
Bin	(4)	1	0	288	1
Bin	(3)	0	1	127	1
Bin	(3)	1	0	292	1
Bin	(2)	0	1	123	1
Bin	(2)	1	0	288	1
Bin	(1)	0	1	134	1
Bin	(1)	1	0	299	1
Bin	(0)	0	1	120	1
Bin	(0)	1	0	285	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	272	1
Bin	(3)	1	0	107	1
Bin	(2)	0	1	183	1
Bin	(2)	1	0	348	1
Bin	(1)	0	1	230	1
Bin	(1)	1	0	395	1
Bin	(0)	0	1	224	1
Bin	(0)	1	0	389	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	162	1
Bin	1	0	327	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	3036	1
Bin	LOCK	1	0	3201	1
Bin	VALID	0	1	1158	1
Bin	VALID	1	0	1323	1
Bin	ERR	0	1	442	1
Bin	ERR	1	0	607	1
Bin	ARBL	0	1	17	1
Bin	ARBL	1	0	182	1
Bin	FAILED	0	1	1417	1
Bin	FAILED	1	0	1582	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	120	1
Bin	(31)	1	0	285	1
Bin	(30)	0	1	81	1
Bin	(30)	1	0	246	1
Bin	(29)	0	1	120	1
Bin	(29)	1	0	285	1
Bin	(28)	0	1	299	1
Bin	(28)	1	0	464	1
Bin	(27)	0	1	244	1
Bin	(27)	1	0	409	1
Bin	(26)	0	1	267	1
Bin	(26)	1	0	432	1
Bin	(25)	0	1	261	1
Bin	(25)	1	0	426	1
Bin	(24)	0	1	321	1
Bin	(24)	1	0	486	1
Bin	(23)	0	1	282	1
Bin	(23)	1	0	447	1
Bin	(22)	0	1	275	1
Bin	(22)	1	0	440	1
Bin	(21)	0	1	269	1
Bin	(21)	1	0	434	1
Bin	(20)	0	1	289	1
Bin	(20)	1	0	454	1
Bin	(19)	0	1	336	1
Bin	(19)	1	0	501	1
Bin	(18)	0	1	294	1
Bin	(18)	1	0	459	1
Bin	(17)	0	1	260	1
Bin	(17)	1	0	425	1
Bin	(16)	0	1	167	1
Bin	(16)	1	0	332	1
Bin	(15)	0	1	206	1
Bin	(15)	1	0	371	1
Bin	(14)	0	1	163	1
Bin	(14)	1	0	328	1
Bin	(13)	0	1	240	1
Bin	(13)	1	0	405	1
Bin	(12)	0	1	196	1
Bin	(12)	1	0	361	1
Bin	(11)	0	1	187	1
Bin	(11)	1	0	352	1
Bin	(10)	0	1	243	1
Bin	(10)	1	0	408	1
Bin	(9)	0	1	323	1
Bin	(9)	1	0	488	1
Bin	(8)	0	1	164	1
Bin	(8)	1	0	329	1
Bin	(7)	0	1	398	1
Bin	(7)	1	0	563	1
Bin	(6)	0	1	306	1
Bin	(6)	1	0	471	1
Bin	(5)	0	1	240	1
Bin	(5)	1	0	405	1
Bin	(4)	0	1	236	1
Bin	(4)	1	0	401	1
Bin	(3)	0	1	344	1
Bin	(3)	1	0	509	1
Bin	(2)	0	1	369	1
Bin	(2)	1	0	534	1
Bin	(1)	0	1	319	1
Bin	(1)	1	0	484	1
Bin	(0)	0	1	352	1
Bin	(0)	1	0	517	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	244	1
Bin	1	0	409	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	373	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	446	1
Bin	1	0	611	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	373	1
Bin	1	0	208	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	208	1
Bin	1	0	373	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	266	1
Bin	(31)	1	0	421	1
Bin	(30)	0	1	234	1
Bin	(30)	1	0	389	1
Bin	(29)	0	1	289	1
Bin	(29)	1	0	444	1
Bin	(28)	0	1	774	1
Bin	(28)	1	0	924	1
Bin	(27)	0	1	622	1
Bin	(27)	1	0	773	1
Bin	(26)	0	1	698	1
Bin	(26)	1	0	849	1
Bin	(25)	0	1	529	1
Bin	(25)	1	0	680	1
Bin	(24)	0	1	829	1
Bin	(24)	1	0	978	1
Bin	(23)	0	1	567	1
Bin	(23)	1	0	718	1
Bin	(22)	0	1	679	1
Bin	(22)	1	0	831	1
Bin	(21)	0	1	769	1
Bin	(21)	1	0	919	1
Bin	(20)	0	1	787	1
Bin	(20)	1	0	940	1
Bin	(19)	0	1	861	1
Bin	(19)	1	0	1010	1
Bin	(18)	0	1	600	1
Bin	(18)	1	0	752	1
Bin	(17)	0	1	556	1
Bin	(17)	1	0	708	1
Bin	(16)	0	1	486	1
Bin	(16)	1	0	640	1
Bin	(15)	0	1	618	1
Bin	(15)	1	0	769	1
Bin	(14)	0	1	493	1
Bin	(14)	1	0	645	1
Bin	(13)	0	1	490	1
Bin	(13)	1	0	641	1
Bin	(12)	0	1	502	1
Bin	(12)	1	0	653	1
Bin	(11)	0	1	493	1
Bin	(11)	1	0	647	1
Bin	(10)	0	1	635	1
Bin	(10)	1	0	787	1
Bin	(9)	0	1	759	1
Bin	(9)	1	0	907	1
Bin	(8)	0	1	419	1
Bin	(8)	1	0	572	1
Bin	(7)	0	1	907	1
Bin	(7)	1	0	1048	1
Bin	(6)	0	1	821	1
Bin	(6)	1	0	966	1
Bin	(5)	0	1	601	1
Bin	(5)	1	0	752	1
Bin	(4)	0	1	603	1
Bin	(4)	1	0	754	1
Bin	(3)	0	1	742	1
Bin	(3)	1	0	886	1
Bin	(2)	0	1	1063	1
Bin	(2)	1	0	1209	1
Bin	(1)	0	1	922	1
Bin	(1)	1	0	1071	1
Bin	(0)	0	1	708	1
Bin	(0)	1	0	852	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	256	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	301	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	2838	1
Bin	1	0	3003	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	512	1
Bin	1	0	677	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	24	1
Bin	1	0	189	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	260	1
Bin	1	0	425	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	46	1
Bin	1	0	211	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	11285	1
Bin	1	0	11450	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	20335	1
Bin	1	0	20500	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	341482	1
Bin	1	0	341647	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	446	1
Bin	1	0	611	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 246:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	11658	1
Bin	True	False	60	1
Bin	True	True	11285	1

"=" expression on line 246:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	12091	1
Bin	True	11345	1

"=" expression on line 246:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	493	1
Bin	True	22943	1

"=" expression on line 259:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	3497	1
Bin	True	1660	1

"or" expression on line 269:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	21235	1
Bin	False	True	11285	1
Bin	True	False	8810	1

"=" expression on line 269:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	32520	1
Bin	True	8810	1

"=" expression on line 269:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	30045	1
Bin	True	11285	1

"=" expression on line 271:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	20995	1
Bin	True	240	1

"and" expression on lines 280 to 282:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	2898	1
Bin	True	False	1007	1
Bin	True	True	91	1

"and" expression on lines 280 to 281:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	17796	1
Bin	True	False	1325	1
Bin	True	True	1098	1

"=" expression on line 280:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	42305	1
Bin	True	2423	1

"=" expression on line 281:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	25834	1
Bin	True	18894	1

"=" expression on line 282:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	41739	1
Bin	True	2989	1

"=" expression on line 294:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	34408890	1
Bin	True	760504	1

"and" expression on line 305:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	99	1
Bin	True	False	116	1
Bin	True	True	24	1

"=" expression on line 305:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	785	1
Bin	True	140	1

"=" expression on line 305:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	802	1
Bin	True	123	1

"and" expression on line 308:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	209	1
Bin	True	False	2708	1
Bin	True	True	260	1

"=" expression on line 308:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	3361	1
Bin	True	2968	1

"=" expression on line 308:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	5860	1
Bin	True	469	1

"and" expression on line 312:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	125	1
Bin	True	False	466	1
Bin	True	True	46	1

"=" expression on line 312:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	1165	1
Bin	True	512	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	1506	1
Bin	True	171	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(6).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

Signal assignment statement on line 246:

Signal assignment statement on line 248:

If statement on lines 259 to 261:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

If statement on lines 269 to 273:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 273:

If statement on lines 280 to 284:

Signal assignment statement on line 280:

Signal assignment statement on line 284:

Signal assignment statement on line 286:

If statement on lines 294 to 302:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Signal assignment statement on line 297:

Signal assignment statement on line 299:

Signal assignment statement on line 300:

Signal assignment statement on line 301:

If statement on lines 305 to 307:

Signal assignment statement on line 305:

Signal assignment statement on line 307:

If statement on lines 308 to 310:

Signal assignment statement on line 308:

Signal assignment statement on line 310:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

Signal assignment statement on line 317:

Signal assignment statement on line 405:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

"if" / "when" / "else" condition on line 259:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 271:

"if" / "when" / "else" condition on lines 280 to 282:

"if" / "when" / "else" condition on line 294:

"if" / "when" / "else" condition on line 298:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

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Port:

Port:

Port:

Port: