NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_TX_INST	100.0 % (19/19)	100.0 % (20/20)	100.0 % (46/46)	100.0 % (6/6)	N.A.	N.A.	100.0 % (91/91)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

114: dlc_int <= to_integer(unsigned(dlc));
Count: 14406
Threshold: 1

If statement:

117:    data_len_8_to_64_integer <= 
118:        12 when (dlc = "1001") else 
...
124:        64 when (dlc = "1111") else 
125:        0;

Count: 14406
Threshold: 1

Signal assignment statement:

118: 12 when (dlc = "1001") else
Count: 214
Threshold: 1

Signal assignment statement:

119: 16 when (dlc = "1010") else
Count: 189
Threshold: 1

Signal assignment statement:

120: 20 when (dlc = "1011") else
Count: 126
Threshold: 1

Signal assignment statement:

121: 24 when (dlc = "1100") else
Count: 264
Threshold: 1

Signal assignment statement:

122: 32 when (dlc = "1101") else
Count: 155
Threshold: 1

Signal assignment statement:

123: 48 when (dlc = "1110") else
Count: 178
Threshold: 1

Signal assignment statement:

124: 64 when (dlc = "1111") else
Count: 96
Threshold: 1

Signal assignment statement:

125: 0;
Count: 13184
Threshold: 1

If statement:

130:    data_len_can_2_0 <= dlc when (dlc_int <= 8) 
131:                            else 
132:                        "1000";

Count: 25612
Threshold: 1

Signal assignment statement:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)
Count: 23169
Threshold: 1

Signal assignment statement:

132: "1000";
Count: 2443
Threshold: 1

If statement:

137:    data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8) 
138:                                     else 
139:                       std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));

Count: 25612
Threshold: 1

Signal assignment statement:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)
Count: 23169
Threshold: 1

Signal assignment statement:

139: std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));
Count: 2443
Threshold: 1

If statement:

142:    data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN) 
143:                                            else 
144:                   data_len_can_fd;

Count: 18578
Threshold: 1

Signal assignment statement:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)
Count: 12472
Threshold: 1

Signal assignment statement:

144: data_len_can_fd;
Count: 6106
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

118: 12 when (dlc = "1001") else

	Evaluated to	Count	Threshold
Bin	True	214	1
Bin	False	14192	1

"if" / "when" / "else" condition:

119: 16 when (dlc = "1010") else

	Evaluated to	Count	Threshold
Bin	True	189	1
Bin	False	14003	1

"if" / "when" / "else" condition:

120: 20 when (dlc = "1011") else

	Evaluated to	Count	Threshold
Bin	True	126	1
Bin	False	13877	1

"if" / "when" / "else" condition:

121: 24 when (dlc = "1100") else

	Evaluated to	Count	Threshold
Bin	True	264	1
Bin	False	13613	1

"if" / "when" / "else" condition:

122: 32 when (dlc = "1101") else

	Evaluated to	Count	Threshold
Bin	True	155	1
Bin	False	13458	1

"if" / "when" / "else" condition:

123: 48 when (dlc = "1110") else

	Evaluated to	Count	Threshold
Bin	True	178	1
Bin	False	13280	1

"if" / "when" / "else" condition:

124: 64 when (dlc = "1111") else

	Evaluated to	Count	Threshold
Bin	True	96	1
Bin	False	13184	1

"if" / "when" / "else" condition:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	23169	1
Bin	False	2443	1

"if" / "when" / "else" condition:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	23169	1
Bin	False	2443	1

"if" / "when" / "else" condition:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	True	12472	1
Bin	False	6106	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DLC(3)

	From	To	Count	Threshold
Bin	0	1	1530	1
Bin	1	0	3129	1

Port:

DLC(2)

	From	To	Count	Threshold
Bin	0	1	1943	1
Bin	1	0	3543	1

Port:

DLC(1)

	From	To	Count	Threshold
Bin	0	1	1905	1
Bin	1	0	3504	1

Port:

DLC(0)

	From	To	Count	Threshold
Bin	0	1	3494	1
Bin	1	0	5094	1

Port:

FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	2691	1
Bin	1	0	4291	1

Port:

DATA_LENGTH(6)

	From	To	Count	Threshold
Bin	0	1	94	1
Bin	1	0	1694	1

Port:

DATA_LENGTH(5)

	From	To	Count	Threshold
Bin	0	1	198	1
Bin	1	0	1798	1

Port:

DATA_LENGTH(4)

	From	To	Count	Threshold
Bin	0	1	424	1
Bin	1	0	2024	1

Port:

DATA_LENGTH(3)

	From	To	Count	Threshold
Bin	0	1	1858	1
Bin	1	0	3457	1

Port:

DATA_LENGTH(2)

	From	To	Count	Threshold
Bin	0	1	2148	1
Bin	1	0	3748	1

Port:

DATA_LENGTH(1)

	From	To	Count	Threshold
Bin	0	1	1922	1
Bin	1	0	3522	1

Port:

DATA_LENGTH(0)

	From	To	Count	Threshold
Bin	0	1	3493	1
Bin	1	0	5093	1

Signal:

DATA_LEN_CAN_2_0(3)

	From	To	Count	Threshold
Bin	0	1	1530	1
Bin	1	0	3129	1

Signal:

DATA_LEN_CAN_2_0(2)

	From	To	Count	Threshold
Bin	0	1	1963	1
Bin	1	0	3563	1

Signal:

DATA_LEN_CAN_2_0(1)

	From	To	Count	Threshold
Bin	0	1	1922	1
Bin	1	0	3522	1

Signal:

DATA_LEN_CAN_2_0(0)

	From	To	Count	Threshold
Bin	0	1	3493	1
Bin	1	0	5093	1

Signal:

DATA_LEN_CAN_FD(6)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1696	1

Signal:

DATA_LEN_CAN_FD(5)

	From	To	Count	Threshold
Bin	0	1	322	1
Bin	1	0	1922	1

Signal:

DATA_LEN_CAN_FD(4)

	From	To	Count	Threshold
Bin	0	1	714	1
Bin	1	0	2313	1

Signal:

DATA_LEN_CAN_FD(3)

	From	To	Count	Threshold
Bin	0	1	1583	1
Bin	1	0	3183	1

Signal:

DATA_LEN_CAN_FD(2)

	From	To	Count	Threshold
Bin	0	1	2283	1
Bin	1	0	3883	1

Signal:

DATA_LEN_CAN_FD(1)

	From	To	Count	Threshold
Bin	0	1	1922	1
Bin	1	0	3522	1

Signal:

DATA_LEN_CAN_FD(0)

	From	To	Count	Threshold
Bin	0	1	3493	1
Bin	1	0	5093	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	False	2443	1
Bin	True	23169	1

"<=" expression

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	False	2443	1
Bin	True	23169	1

"=" expression

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	False	6106	1
Bin	True	12472	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_TX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

"<=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: