File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- DLC Decoder
71: --
72: -- Purpose:
73: -- Decode DLC to byte length of Data field in CAN Frame. Support both CAN 2.0
74: -- and CAN FD. Decoder returns '0' if frame type is 'CAN_2_0' and DLC is
75: -- greater than 8.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.all;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
84:
85: entity dlc_decoder is
86: port (
87: -- DLC Input (as in CAN Standard)
88: dlc : in std_logic_vector(3 downto 0);
89:
90: -- Frame Type (0 - CAN 2.0, 1 - CAN FD)
91: frame_type : in std_logic;
92:
93: -- Data length (decoded)
94: data_length : out std_logic_vector(6 downto 0)
95: );
96: end dlc_decoder;
97:
98: architecture rtl of dlc_decoder is
99:
100: signal data_len_8_to_64_integer : natural range 0 to 64;
101:
102: -- Data length fot standard CAN 2.0 frame
103: signal data_len_can_2_0 : std_logic_vector(3 downto 0);
104:
105: -- Data length fot standard CAN FD frame
106: signal data_len_can_fd : std_logic_vector(6 downto 0);
107:
108: signal dlc_int : natural range 0 to 64;
109:
110: begin
111:
112: -- Typecast to natural
113: dlc_int <= to_integer(unsigned(dlc));
114:
115: -- Decoder for DLCs higher than 8 in CAN FD Frame
116: data_len_8_to_64_integer <=
117: 12 when (dlc = "1001") else
118: 16 when (dlc = "1010") else
119: 20 when (dlc = "1011") else
120: 24 when (dlc = "1100") else
121: 32 when (dlc = "1101") else
122: 48 when (dlc = "1110") else
123: 64 when (dlc = "1111") else
124: 0;
125:
126: -- Mux for CAN 2.0 DLC:
127: -- 1. Take DLC itself for values less or equal than 8
128: -- 2. Hard-code 8 (all DLCs above 8 mean 8 bytes in spec.)
129: data_len_can_2_0 <= dlc when (dlc_int <= 8)
130: else
131: "1000";
132:
133: -- Mux for CAN FD DLC:
134: -- 1. Take DLC itself for values less or equal than 8
135: -- 2. Use decoder above for values higher than 8.
136: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)
137: else
138: std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));
139:
140: -- According the CAN frame type, select output vector
141: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)
142: else
143: data_len_can_fd;
144:
145: end rtl;