NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	100.0 % (30/30)	N.A.	N.A.	100.0 % (1641/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (17/17)	N.A.	N.A.	100.0 % (109/109)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST	100.0 % (18/18)	100.0 % (12/12)	100.0 % (516/516)	100.0 % (15/15)	N.A.	N.A.	100.0 % (561/561)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 4626
Threshold: 1

Signal assignment statement:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 304
Threshold: 1

Signal assignment statement:

280: '0';
Count: 4322
Threshold: 1

If statement:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 49588826
Threshold: 1

Signal assignment statement:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 49534119
Threshold: 1

Signal assignment statement:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 54707
Threshold: 1

If statement:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 190177
Threshold: 1

Signal assignment statement:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 186043
Threshold: 1

Signal assignment statement:

289: mr_tst_control_twrstb;
Count: 4134
Threshold: 1

If statement:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 1586755
Threshold: 1

Signal assignment statement:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 1552223
Threshold: 1

Signal assignment statement:

293: mr_tst_wdata_tst_wdata;
Count: 34532
Threshold: 1

If statement:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 175764
Threshold: 1

Signal assignment statement:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 171889
Threshold: 1

Signal assignment statement:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 3875
Threshold: 1

If statement:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 20424
Threshold: 1

Signal assignment statement:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 2321
Threshold: 1

Signal assignment statement:

302: (others => '0');
Count: 18103
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	Evaluated to	Count	Threshold
Bin	True	304	1
Bin	False	4322	1

"if" / "when" / "else" condition:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	49534119	1
Bin	False	54707	1

"if" / "when" / "else" condition:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	186043	1
Bin	False	4134	1

"if" / "when" / "else" condition:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	1552223	1
Bin	False	34532	1

"if" / "when" / "else" condition:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	True	171889	1
Bin	False	3875	1

"if" / "when" / "else" condition:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')

	Evaluated to	Count	Threshold
Bin	True	2321	1
Bin	False	18103	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13641406	1
Bin	1	0	13642066	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	2844	1
Bin	1	0	2844	1

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold
Bin	0	1	110	1
Bin	1	0	770	1

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold
Bin	0	1	636	1
Bin	1	0	1296	1

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold
Bin	0	1	31329	1
Bin	1	0	33257	1

Port:

MR_TST_DEST_TST_ADDR(4)

	From	To	Count	Threshold
Bin	0	1	3406	1
Bin	1	0	4066	1

Port:

MR_TST_DEST_TST_ADDR(3)

	From	To	Count	Threshold
Bin	0	1	4810	1
Bin	1	0	5470	1

Port:

MR_TST_DEST_TST_ADDR(2)

	From	To	Count	Threshold
Bin	0	1	9862	1
Bin	1	0	10522	1

Port:

MR_TST_DEST_TST_ADDR(1)

	From	To	Count	Threshold
Bin	0	1	21367	1
Bin	1	0	22027	1

Port:

MR_TST_DEST_TST_ADDR(0)

	From	To	Count	Threshold
Bin	0	1	42723	1
Bin	1	0	43383	1

Port:

MR_TST_DEST_TST_MTGT(3)

	From	To	Count	Threshold
Bin	0	1	214	1
Bin	1	0	874	1

Port:

MR_TST_DEST_TST_MTGT(2)

	From	To	Count	Threshold
Bin	0	1	353	1
Bin	1	0	1013	1

Port:

MR_TST_DEST_TST_MTGT(1)

	From	To	Count	Threshold
Bin	0	1	472	1
Bin	1	0	1132	1

Port:

MR_TST_DEST_TST_MTGT(0)

	From	To	Count	Threshold
Bin	0	1	896	1
Bin	1	0	1556	1

Port:

MR_TST_WDATA_TST_WDATA(31)

	From	To	Count	Threshold
Bin	0	1	1490	1
Bin	1	0	2150	1

Port:

MR_TST_WDATA_TST_WDATA(30)

	From	To	Count	Threshold
Bin	0	1	1437	1
Bin	1	0	2097	1

Port:

MR_TST_WDATA_TST_WDATA(29)

	From	To	Count	Threshold
Bin	0	1	1448	1
Bin	1	0	2108	1

Port:

MR_TST_WDATA_TST_WDATA(28)

	From	To	Count	Threshold
Bin	0	1	1585	1
Bin	1	0	2245	1

Port:

MR_TST_WDATA_TST_WDATA(27)

	From	To	Count	Threshold
Bin	0	1	1607	1
Bin	1	0	2267	1

Port:

MR_TST_WDATA_TST_WDATA(26)

	From	To	Count	Threshold
Bin	0	1	1590	1
Bin	1	0	2250	1

Port:

MR_TST_WDATA_TST_WDATA(25)

	From	To	Count	Threshold
Bin	0	1	1603	1
Bin	1	0	2263	1

Port:

MR_TST_WDATA_TST_WDATA(24)

	From	To	Count	Threshold
Bin	0	1	1673	1
Bin	1	0	2333	1

Port:

MR_TST_WDATA_TST_WDATA(23)

	From	To	Count	Threshold
Bin	0	1	1542	1
Bin	1	0	2202	1

Port:

MR_TST_WDATA_TST_WDATA(22)

	From	To	Count	Threshold
Bin	0	1	1481	1
Bin	1	0	2141	1

Port:

MR_TST_WDATA_TST_WDATA(21)

	From	To	Count	Threshold
Bin	0	1	1519	1
Bin	1	0	2179	1

Port:

MR_TST_WDATA_TST_WDATA(20)

	From	To	Count	Threshold
Bin	0	1	1613	1
Bin	1	0	2273	1

Port:

MR_TST_WDATA_TST_WDATA(19)

	From	To	Count	Threshold
Bin	0	1	1608	1
Bin	1	0	2268	1

Port:

MR_TST_WDATA_TST_WDATA(18)

	From	To	Count	Threshold
Bin	0	1	1595	1
Bin	1	0	2255	1

Port:

MR_TST_WDATA_TST_WDATA(17)

	From	To	Count	Threshold
Bin	0	1	1591	1
Bin	1	0	2251	1

Port:

MR_TST_WDATA_TST_WDATA(16)

	From	To	Count	Threshold
Bin	0	1	1629	1
Bin	1	0	2289	1

Port:

MR_TST_WDATA_TST_WDATA(15)

	From	To	Count	Threshold
Bin	0	1	1530	1
Bin	1	0	2190	1

Port:

MR_TST_WDATA_TST_WDATA(14)

	From	To	Count	Threshold
Bin	0	1	1465	1
Bin	1	0	2125	1

Port:

MR_TST_WDATA_TST_WDATA(13)

	From	To	Count	Threshold
Bin	0	1	1515	1
Bin	1	0	2175	1

Port:

MR_TST_WDATA_TST_WDATA(12)

	From	To	Count	Threshold
Bin	0	1	1598	1
Bin	1	0	2258	1

Port:

MR_TST_WDATA_TST_WDATA(11)

	From	To	Count	Threshold
Bin	0	1	1604	1
Bin	1	0	2264	1

Port:

MR_TST_WDATA_TST_WDATA(10)

	From	To	Count	Threshold
Bin	0	1	1606	1
Bin	1	0	2266	1

Port:

MR_TST_WDATA_TST_WDATA(9)

	From	To	Count	Threshold
Bin	0	1	1630	1
Bin	1	0	2290	1

Port:

MR_TST_WDATA_TST_WDATA(8)

	From	To	Count	Threshold
Bin	0	1	1644	1
Bin	1	0	2304	1

Port:

MR_TST_WDATA_TST_WDATA(7)

	From	To	Count	Threshold
Bin	0	1	1589	1
Bin	1	0	2249	1

Port:

MR_TST_WDATA_TST_WDATA(6)

	From	To	Count	Threshold
Bin	0	1	1527	1
Bin	1	0	2187	1

Port:

MR_TST_WDATA_TST_WDATA(5)

	From	To	Count	Threshold
Bin	0	1	1554	1
Bin	1	0	2214	1

Port:

MR_TST_WDATA_TST_WDATA(4)

	From	To	Count	Threshold
Bin	0	1	1594	1
Bin	1	0	2254	1

Port:

MR_TST_WDATA_TST_WDATA(3)

	From	To	Count	Threshold
Bin	0	1	1602	1
Bin	1	0	2262	1

Port:

MR_TST_WDATA_TST_WDATA(2)

	From	To	Count	Threshold
Bin	0	1	1615	1
Bin	1	0	2275	1

Port:

MR_TST_WDATA_TST_WDATA(1)

	From	To	Count	Threshold
Bin	0	1	1616	1
Bin	1	0	2276	1

Port:

MR_TST_WDATA_TST_WDATA(0)

	From	To	Count	Threshold
Bin	0	1	1677	1
Bin	1	0	2337	1

Port:

MR_TST_RDATA_TST_RDATA(31)

	From	To	Count	Threshold
Bin	0	1	486	1
Bin	1	0	1146	1

Port:

MR_TST_RDATA_TST_RDATA(30)

	From	To	Count	Threshold
Bin	0	1	493	1
Bin	1	0	1153	1

Port:

MR_TST_RDATA_TST_RDATA(29)

	From	To	Count	Threshold
Bin	0	1	469	1
Bin	1	0	1129	1

Port:

MR_TST_RDATA_TST_RDATA(28)

	From	To	Count	Threshold
Bin	0	1	573	1
Bin	1	0	1233	1

Port:

MR_TST_RDATA_TST_RDATA(27)

	From	To	Count	Threshold
Bin	0	1	550	1
Bin	1	0	1210	1

Port:

MR_TST_RDATA_TST_RDATA(26)

	From	To	Count	Threshold
Bin	0	1	549	1
Bin	1	0	1209	1

Port:

MR_TST_RDATA_TST_RDATA(25)

	From	To	Count	Threshold
Bin	0	1	558	1
Bin	1	0	1218	1

Port:

MR_TST_RDATA_TST_RDATA(24)

	From	To	Count	Threshold
Bin	0	1	550	1
Bin	1	0	1210	1

Port:

MR_TST_RDATA_TST_RDATA(23)

	From	To	Count	Threshold
Bin	0	1	555	1
Bin	1	0	1215	1

Port:

MR_TST_RDATA_TST_RDATA(22)

	From	To	Count	Threshold
Bin	0	1	551	1
Bin	1	0	1211	1

Port:

MR_TST_RDATA_TST_RDATA(21)

	From	To	Count	Threshold
Bin	0	1	562	1
Bin	1	0	1222	1

Port:

MR_TST_RDATA_TST_RDATA(20)

	From	To	Count	Threshold
Bin	0	1	566	1
Bin	1	0	1226	1

Port:

MR_TST_RDATA_TST_RDATA(19)

	From	To	Count	Threshold
Bin	0	1	528	1
Bin	1	0	1188	1

Port:

MR_TST_RDATA_TST_RDATA(18)

	From	To	Count	Threshold
Bin	0	1	582	1
Bin	1	0	1242	1

Port:

MR_TST_RDATA_TST_RDATA(17)

	From	To	Count	Threshold
Bin	0	1	520	1
Bin	1	0	1180	1

Port:

MR_TST_RDATA_TST_RDATA(16)

	From	To	Count	Threshold
Bin	0	1	513	1
Bin	1	0	1173	1

Port:

MR_TST_RDATA_TST_RDATA(15)

	From	To	Count	Threshold
Bin	0	1	508	1
Bin	1	0	1168	1

Port:

MR_TST_RDATA_TST_RDATA(14)

	From	To	Count	Threshold
Bin	0	1	536	1
Bin	1	0	1196	1

Port:

MR_TST_RDATA_TST_RDATA(13)

	From	To	Count	Threshold
Bin	0	1	516	1
Bin	1	0	1176	1

Port:

MR_TST_RDATA_TST_RDATA(12)

	From	To	Count	Threshold
Bin	0	1	529	1
Bin	1	0	1189	1

Port:

MR_TST_RDATA_TST_RDATA(11)

	From	To	Count	Threshold
Bin	0	1	532	1
Bin	1	0	1192	1

Port:

MR_TST_RDATA_TST_RDATA(10)

	From	To	Count	Threshold
Bin	0	1	522	1
Bin	1	0	1182	1

Port:

MR_TST_RDATA_TST_RDATA(9)

	From	To	Count	Threshold
Bin	0	1	534	1
Bin	1	0	1194	1

Port:

MR_TST_RDATA_TST_RDATA(8)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	1174	1

Port:

MR_TST_RDATA_TST_RDATA(7)

	From	To	Count	Threshold
Bin	0	1	552	1
Bin	1	0	1212	1

Port:

MR_TST_RDATA_TST_RDATA(6)

	From	To	Count	Threshold
Bin	0	1	533	1
Bin	1	0	1193	1

Port:

MR_TST_RDATA_TST_RDATA(5)

	From	To	Count	Threshold
Bin	0	1	520	1
Bin	1	0	1180	1

Port:

MR_TST_RDATA_TST_RDATA(4)

	From	To	Count	Threshold
Bin	0	1	546	1
Bin	1	0	1206	1

Port:

MR_TST_RDATA_TST_RDATA(3)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	1179	1

Port:

MR_TST_RDATA_TST_RDATA(2)

	From	To	Count	Threshold
Bin	0	1	552	1
Bin	1	0	1212	1

Port:

MR_TST_RDATA_TST_RDATA(1)

	From	To	Count	Threshold
Bin	0	1	501	1
Bin	1	0	1161	1

Port:

MR_TST_RDATA_TST_RDATA(0)

	From	To	Count	Threshold
Bin	0	1	545	1
Bin	1	0	1205	1

Port:

TXTB_PORT_A_ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	249017	1
Bin	1	0	24501565	1

Port:

TXTB_PORT_A_ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	396175	1
Bin	1	0	24354407	1

Port:

TXTB_PORT_A_ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	299014	1
Bin	1	0	24451568	1

Port:

TXTB_PORT_A_ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	24194275	1
Bin	1	0	556307	1

Port:

TXTB_PORT_A_ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	15940744	1
Bin	1	0	8809838	1

Port:

TXTB_PORT_A_DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	26356	1
Bin	1	0	762824	1

Port:

TXTB_PORT_A_DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	28657	1
Bin	1	0	760523	1

Port:

TXTB_PORT_A_DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	27152	1
Bin	1	0	762028	1

Port:

TXTB_PORT_A_DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	44044	1
Bin	1	0	745136	1

Port:

TXTB_PORT_A_DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	37637	1
Bin	1	0	751543	1

Port:

TXTB_PORT_A_DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	35980	1
Bin	1	0	753200	1

Port:

TXTB_PORT_A_DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	49211	1
Bin	1	0	739969	1

Port:

TXTB_PORT_A_DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	36691	1
Bin	1	0	752489	1

Port:

TXTB_PORT_A_DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	35471	1
Bin	1	0	753709	1

Port:

TXTB_PORT_A_DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	44528	1
Bin	1	0	744652	1

Port:

TXTB_PORT_A_DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	38824	1
Bin	1	0	750356	1

Port:

TXTB_PORT_A_DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	37253	1
Bin	1	0	751927	1

Port:

TXTB_PORT_A_DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	64725	1
Bin	1	0	724455	1

Port:

TXTB_PORT_A_DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	84831	1
Bin	1	0	704349	1

Port:

TXTB_PORT_A_DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	79950	1
Bin	1	0	709230	1

Port:

TXTB_PORT_A_DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	141786	1
Bin	1	0	647394	1

Port:

TXTB_PORT_A_DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	33296	1
Bin	1	0	755884	1

Port:

TXTB_PORT_A_DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	41814	1
Bin	1	0	747366	1

Port:

TXTB_PORT_A_DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	36216	1
Bin	1	0	752964	1

Port:

TXTB_PORT_A_DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	40217	1
Bin	1	0	748963	1

Port:

TXTB_PORT_A_DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	58401	1
Bin	1	0	730779	1

Port:

TXTB_PORT_A_DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	61314	1
Bin	1	0	727866	1

Port:

TXTB_PORT_A_DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	79096	1
Bin	1	0	710084	1

Port:

TXTB_PORT_A_DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	80705	1
Bin	1	0	708475	1

Port:

TXTB_PORT_A_DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	68788	1
Bin	1	0	720392	1

Port:

TXTB_PORT_A_DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	65064	1
Bin	1	0	724116	1

Port:

TXTB_PORT_A_DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	65949	1
Bin	1	0	723231	1

Port:

TXTB_PORT_A_DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	83106	1
Bin	1	0	706074	1

Port:

TXTB_PORT_A_DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	90500	1
Bin	1	0	698680	1

Port:

TXTB_PORT_A_DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	100212	1
Bin	1	0	688968	1

Port:

TXTB_PORT_A_DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	165652	1
Bin	1	0	623528	1

Port:

TXTB_PORT_A_DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	141015	1
Bin	1	0	648165	1

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold
Bin	0	1	640015	1
Bin	1	0	149165	1

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	45533	1
Bin	1	0	46193	1

Port:

TXTB_PORT_A_BE(3)

	From	To	Count	Threshold
Bin	0	1	24721305	1
Bin	1	0	28617	1

Port:

TXTB_PORT_A_BE(2)

	From	To	Count	Threshold
Bin	0	1	24721613	1
Bin	1	0	28309	1

Port:

TXTB_PORT_A_BE(1)

	From	To	Count	Threshold
Bin	0	1	24633047	1
Bin	1	0	116875	1

Port:

TXTB_PORT_A_BE(0)

	From	To	Count	Threshold
Bin	0	1	24634059	1
Bin	1	0	115863	1

Port:

TXTB_PORT_B_ADDRESS(4)

	From	To	Count	Threshold
Bin	0	1	10515	1
Bin	1	0	11175	1

Port:

TXTB_PORT_B_ADDRESS(3)

	From	To	Count	Threshold
Bin	0	1	346	1
Bin	1	0	1006	1

Port:

TXTB_PORT_B_ADDRESS(2)

	From	To	Count	Threshold
Bin	0	1	15447	1
Bin	1	0	16107	1

Port:

TXTB_PORT_B_ADDRESS(1)

	From	To	Count	Threshold
Bin	0	1	12158	1
Bin	1	0	12158	1

Port:

TXTB_PORT_B_ADDRESS(0)

	From	To	Count	Threshold
Bin	0	1	34271	1
Bin	1	0	34931	1

Port:

TXTB_PORT_B_DATA_OUT(31)

	From	To	Count	Threshold
Bin	0	1	973	1
Bin	1	0	1592	1

Port:

TXTB_PORT_B_DATA_OUT(30)

	From	To	Count	Threshold
Bin	0	1	1091	1
Bin	1	0	1711	1

Port:

TXTB_PORT_B_DATA_OUT(29)

	From	To	Count	Threshold
Bin	0	1	993	1
Bin	1	0	1612	1

Port:

TXTB_PORT_B_DATA_OUT(28)

	From	To	Count	Threshold
Bin	0	1	2718	1
Bin	1	0	3327	1

Port:

TXTB_PORT_B_DATA_OUT(27)

	From	To	Count	Threshold
Bin	0	1	2695	1
Bin	1	0	3296	1

Port:

TXTB_PORT_B_DATA_OUT(26)

	From	To	Count	Threshold
Bin	0	1	2787	1
Bin	1	0	3394	1

Port:

TXTB_PORT_B_DATA_OUT(25)

	From	To	Count	Threshold
Bin	0	1	2562	1
Bin	1	0	3169	1

Port:

TXTB_PORT_B_DATA_OUT(24)

	From	To	Count	Threshold
Bin	0	1	2692	1
Bin	1	0	3300	1

Port:

TXTB_PORT_B_DATA_OUT(23)

	From	To	Count	Threshold
Bin	0	1	3012	1
Bin	1	0	3615	1

Port:

TXTB_PORT_B_DATA_OUT(22)

	From	To	Count	Threshold
Bin	0	1	2766	1
Bin	1	0	3367	1

Port:

TXTB_PORT_B_DATA_OUT(21)

	From	To	Count	Threshold
Bin	0	1	3130	1
Bin	1	0	3728	1

Port:

TXTB_PORT_B_DATA_OUT(20)

	From	To	Count	Threshold
Bin	0	1	2846	1
Bin	1	0	3450	1

Port:

TXTB_PORT_B_DATA_OUT(19)

	From	To	Count	Threshold
Bin	0	1	3322	1
Bin	1	0	3922	1

Port:

TXTB_PORT_B_DATA_OUT(18)

	From	To	Count	Threshold
Bin	0	1	3063	1
Bin	1	0	3669	1

Port:

TXTB_PORT_B_DATA_OUT(17)

	From	To	Count	Threshold
Bin	0	1	2398	1
Bin	1	0	3013	1

Port:

TXTB_PORT_B_DATA_OUT(16)

	From	To	Count	Threshold
Bin	0	1	2168	1
Bin	1	0	2784	1

Port:

TXTB_PORT_B_DATA_OUT(15)

	From	To	Count	Threshold
Bin	0	1	1899	1
Bin	1	0	2508	1

Port:

TXTB_PORT_B_DATA_OUT(14)

	From	To	Count	Threshold
Bin	0	1	2448	1
Bin	1	0	3064	1

Port:

TXTB_PORT_B_DATA_OUT(13)

	From	To	Count	Threshold
Bin	0	1	2061	1
Bin	1	0	2674	1

Port:

TXTB_PORT_B_DATA_OUT(12)

	From	To	Count	Threshold
Bin	0	1	2487	1
Bin	1	0	3100	1

Port:

TXTB_PORT_B_DATA_OUT(11)

	From	To	Count	Threshold
Bin	0	1	2085	1
Bin	1	0	2696	1

Port:

TXTB_PORT_B_DATA_OUT(10)

	From	To	Count	Threshold
Bin	0	1	2481	1
Bin	1	0	3092	1

Port:

TXTB_PORT_B_DATA_OUT(9)

	From	To	Count	Threshold
Bin	0	1	3211	1
Bin	1	0	3810	1

Port:

TXTB_PORT_B_DATA_OUT(8)

	From	To	Count	Threshold
Bin	0	1	2183	1
Bin	1	0	2793	1

Port:

TXTB_PORT_B_DATA_OUT(7)

	From	To	Count	Threshold
Bin	0	1	4011	1
Bin	1	0	4597	1

Port:

TXTB_PORT_B_DATA_OUT(6)

	From	To	Count	Threshold
Bin	0	1	3294	1
Bin	1	0	3888	1

Port:

TXTB_PORT_B_DATA_OUT(5)

	From	To	Count	Threshold
Bin	0	1	3111	1
Bin	1	0	3719	1

Port:

TXTB_PORT_B_DATA_OUT(4)

	From	To	Count	Threshold
Bin	0	1	1852	1
Bin	1	0	2466	1

Port:

TXTB_PORT_B_DATA_OUT(3)

	From	To	Count	Threshold
Bin	0	1	2671	1
Bin	1	0	3265	1

Port:

TXTB_PORT_B_DATA_OUT(2)

	From	To	Count	Threshold
Bin	0	1	3234	1
Bin	1	0	3837	1

Port:

TXTB_PORT_B_DATA_OUT(1)

	From	To	Count	Threshold
Bin	0	1	2781	1
Bin	1	0	3377	1

Port:

TXTB_PORT_B_DATA_OUT(0)

	From	To	Count	Threshold
Bin	0	1	3526	1
Bin	1	0	4121	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1580	1
Bin	1	0	2240	1

Signal:

TXTB_PORT_A_ADDRESS_I(4)

	From	To	Count	Threshold
Bin	0	1	249177	1
Bin	1	0	24476309	1

Signal:

TXTB_PORT_A_ADDRESS_I(3)

	From	To	Count	Threshold
Bin	0	1	396315	1
Bin	1	0	24329131	1

Signal:

TXTB_PORT_A_ADDRESS_I(2)

	From	To	Count	Threshold
Bin	0	1	299383	1
Bin	1	0	24426521	1

Signal:

TXTB_PORT_A_ADDRESS_I(1)

	From	To	Count	Threshold
Bin	0	1	24183911	1
Bin	1	0	542807	1

Signal:

TXTB_PORT_A_ADDRESS_I(0)

	From	To	Count	Threshold
Bin	0	1	15922367	1
Bin	1	0	8806091	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	46503	1
Bin	1	0	47313	1

Signal:

TXTB_PORT_A_DATA_I(31)

	From	To	Count	Threshold
Bin	0	1	25826	1
Bin	1	0	746948	1

Signal:

TXTB_PORT_A_DATA_I(30)

	From	To	Count	Threshold
Bin	0	1	28125	1
Bin	1	0	744663	1

Signal:

TXTB_PORT_A_DATA_I(29)

	From	To	Count	Threshold
Bin	0	1	26617	1
Bin	1	0	746119	1

Signal:

TXTB_PORT_A_DATA_I(28)

	From	To	Count	Threshold
Bin	0	1	43526	1
Bin	1	0	729314	1

Signal:

TXTB_PORT_A_DATA_I(27)

	From	To	Count	Threshold
Bin	0	1	37131	1
Bin	1	0	735717	1

Signal:

TXTB_PORT_A_DATA_I(26)

	From	To	Count	Threshold
Bin	0	1	35466	1
Bin	1	0	737378	1

Signal:

TXTB_PORT_A_DATA_I(25)

	From	To	Count	Threshold
Bin	0	1	48636	1
Bin	1	0	724208	1

Signal:

TXTB_PORT_A_DATA_I(24)

	From	To	Count	Threshold
Bin	0	1	36191	1
Bin	1	0	736659	1

Signal:

TXTB_PORT_A_DATA_I(23)

	From	To	Count	Threshold
Bin	0	1	34962	1
Bin	1	0	737886	1

Signal:

TXTB_PORT_A_DATA_I(22)

	From	To	Count	Threshold
Bin	0	1	44024	1
Bin	1	0	728824	1

Signal:

TXTB_PORT_A_DATA_I(21)

	From	To	Count	Threshold
Bin	0	1	38311	1
Bin	1	0	734535	1

Signal:

TXTB_PORT_A_DATA_I(20)

	From	To	Count	Threshold
Bin	0	1	36729	1
Bin	1	0	736097	1

Signal:

TXTB_PORT_A_DATA_I(19)

	From	To	Count	Threshold
Bin	0	1	62608	1
Bin	1	0	710230	1

Signal:

TXTB_PORT_A_DATA_I(18)

	From	To	Count	Threshold
Bin	0	1	76422	1
Bin	1	0	696488	1

Signal:

TXTB_PORT_A_DATA_I(17)

	From	To	Count	Threshold
Bin	0	1	76216	1
Bin	1	0	696582	1

Signal:

TXTB_PORT_A_DATA_I(16)

	From	To	Count	Threshold
Bin	0	1	136306	1
Bin	1	0	636528	1

Signal:

TXTB_PORT_A_DATA_I(15)

	From	To	Count	Threshold
Bin	0	1	32795	1
Bin	1	0	740025	1

Signal:

TXTB_PORT_A_DATA_I(14)

	From	To	Count	Threshold
Bin	0	1	41285	1
Bin	1	0	731537	1

Signal:

TXTB_PORT_A_DATA_I(13)

	From	To	Count	Threshold
Bin	0	1	35707	1
Bin	1	0	737121	1

Signal:

TXTB_PORT_A_DATA_I(12)

	From	To	Count	Threshold
Bin	0	1	39715	1
Bin	1	0	733131	1

Signal:

TXTB_PORT_A_DATA_I(11)

	From	To	Count	Threshold
Bin	0	1	57878	1
Bin	1	0	714926	1

Signal:

TXTB_PORT_A_DATA_I(10)

	From	To	Count	Threshold
Bin	0	1	60791	1
Bin	1	0	712027	1

Signal:

TXTB_PORT_A_DATA_I(9)

	From	To	Count	Threshold
Bin	0	1	78521	1
Bin	1	0	694319	1

Signal:

TXTB_PORT_A_DATA_I(8)

	From	To	Count	Threshold
Bin	0	1	80173	1
Bin	1	0	692633	1

Signal:

TXTB_PORT_A_DATA_I(7)

	From	To	Count	Threshold
Bin	0	1	68290	1
Bin	1	0	704578	1

Signal:

TXTB_PORT_A_DATA_I(6)

	From	To	Count	Threshold
Bin	0	1	64556	1
Bin	1	0	708320	1

Signal:

TXTB_PORT_A_DATA_I(5)

	From	To	Count	Threshold
Bin	0	1	65430	1
Bin	1	0	707404	1

Signal:

TXTB_PORT_A_DATA_I(4)

	From	To	Count	Threshold
Bin	0	1	80291	1
Bin	1	0	692533	1

Signal:

TXTB_PORT_A_DATA_I(3)

	From	To	Count	Threshold
Bin	0	1	85667	1
Bin	1	0	687147	1

Signal:

TXTB_PORT_A_DATA_I(2)

	From	To	Count	Threshold
Bin	0	1	95190	1
Bin	1	0	677689	1

Signal:

TXTB_PORT_A_DATA_I(1)

	From	To	Count	Threshold
Bin	0	1	157097	1
Bin	1	0	615746	1

Signal:

TXTB_PORT_A_DATA_I(0)

	From	To	Count	Threshold
Bin	0	1	133139	1
Bin	1	0	639818	1

Signal:

TXTB_PORT_B_ADDRESS_I(4)

	From	To	Count	Threshold
Bin	0	1	10675	1
Bin	1	0	11335	1

Signal:

TXTB_PORT_B_ADDRESS_I(3)

	From	To	Count	Threshold
Bin	0	1	486	1
Bin	1	0	1146	1

Signal:

TXTB_PORT_B_ADDRESS_I(2)

	From	To	Count	Threshold
Bin	0	1	15816	1
Bin	1	0	16476	1

Signal:

TXTB_PORT_B_ADDRESS_I(1)

	From	To	Count	Threshold
Bin	0	1	13067	1
Bin	1	0	13067	1

Signal:

TXTB_PORT_B_ADDRESS_I(0)

	From	To	Count	Threshold
Bin	0	1	35808	1
Bin	1	0	36468	1

Signal:

TXTB_PORT_B_DATA_OUT_I(31)

	From	To	Count	Threshold
Bin	0	1	973	1
Bin	1	0	1592	1

Signal:

TXTB_PORT_B_DATA_OUT_I(30)

	From	To	Count	Threshold
Bin	0	1	1091	1
Bin	1	0	1711	1

Signal:

TXTB_PORT_B_DATA_OUT_I(29)

	From	To	Count	Threshold
Bin	0	1	993	1
Bin	1	0	1612	1

Signal:

TXTB_PORT_B_DATA_OUT_I(28)

	From	To	Count	Threshold
Bin	0	1	2718	1
Bin	1	0	3327	1

Signal:

TXTB_PORT_B_DATA_OUT_I(27)

	From	To	Count	Threshold
Bin	0	1	2695	1
Bin	1	0	3296	1

Signal:

TXTB_PORT_B_DATA_OUT_I(26)

	From	To	Count	Threshold
Bin	0	1	2787	1
Bin	1	0	3394	1

Signal:

TXTB_PORT_B_DATA_OUT_I(25)

	From	To	Count	Threshold
Bin	0	1	2562	1
Bin	1	0	3169	1

Signal:

TXTB_PORT_B_DATA_OUT_I(24)

	From	To	Count	Threshold
Bin	0	1	2692	1
Bin	1	0	3300	1

Signal:

TXTB_PORT_B_DATA_OUT_I(23)

	From	To	Count	Threshold
Bin	0	1	3012	1
Bin	1	0	3615	1

Signal:

TXTB_PORT_B_DATA_OUT_I(22)

	From	To	Count	Threshold
Bin	0	1	2766	1
Bin	1	0	3367	1

Signal:

TXTB_PORT_B_DATA_OUT_I(21)

	From	To	Count	Threshold
Bin	0	1	3130	1
Bin	1	0	3728	1

Signal:

TXTB_PORT_B_DATA_OUT_I(20)

	From	To	Count	Threshold
Bin	0	1	2846	1
Bin	1	0	3450	1

Signal:

TXTB_PORT_B_DATA_OUT_I(19)

	From	To	Count	Threshold
Bin	0	1	3322	1
Bin	1	0	3922	1

Signal:

TXTB_PORT_B_DATA_OUT_I(18)

	From	To	Count	Threshold
Bin	0	1	3063	1
Bin	1	0	3669	1

Signal:

TXTB_PORT_B_DATA_OUT_I(17)

	From	To	Count	Threshold
Bin	0	1	2398	1
Bin	1	0	3013	1

Signal:

TXTB_PORT_B_DATA_OUT_I(16)

	From	To	Count	Threshold
Bin	0	1	2168	1
Bin	1	0	2784	1

Signal:

TXTB_PORT_B_DATA_OUT_I(15)

	From	To	Count	Threshold
Bin	0	1	1899	1
Bin	1	0	2508	1

Signal:

TXTB_PORT_B_DATA_OUT_I(14)

	From	To	Count	Threshold
Bin	0	1	2448	1
Bin	1	0	3064	1

Signal:

TXTB_PORT_B_DATA_OUT_I(13)

	From	To	Count	Threshold
Bin	0	1	2061	1
Bin	1	0	2674	1

Signal:

TXTB_PORT_B_DATA_OUT_I(12)

	From	To	Count	Threshold
Bin	0	1	2487	1
Bin	1	0	3100	1

Signal:

TXTB_PORT_B_DATA_OUT_I(11)

	From	To	Count	Threshold
Bin	0	1	2085	1
Bin	1	0	2696	1

Signal:

TXTB_PORT_B_DATA_OUT_I(10)

	From	To	Count	Threshold
Bin	0	1	2481	1
Bin	1	0	3092	1

Signal:

TXTB_PORT_B_DATA_OUT_I(9)

	From	To	Count	Threshold
Bin	0	1	3211	1
Bin	1	0	3810	1

Signal:

TXTB_PORT_B_DATA_OUT_I(8)

	From	To	Count	Threshold
Bin	0	1	2183	1
Bin	1	0	2793	1

Signal:

TXTB_PORT_B_DATA_OUT_I(7)

	From	To	Count	Threshold
Bin	0	1	4011	1
Bin	1	0	4597	1

Signal:

TXTB_PORT_B_DATA_OUT_I(6)

	From	To	Count	Threshold
Bin	0	1	3294	1
Bin	1	0	3888	1

Signal:

TXTB_PORT_B_DATA_OUT_I(5)

	From	To	Count	Threshold
Bin	0	1	3111	1
Bin	1	0	3719	1

Signal:

TXTB_PORT_B_DATA_OUT_I(4)

	From	To	Count	Threshold
Bin	0	1	1852	1
Bin	1	0	2466	1

Signal:

TXTB_PORT_B_DATA_OUT_I(3)

	From	To	Count	Threshold
Bin	0	1	2671	1
Bin	1	0	3265	1

Signal:

TXTB_PORT_B_DATA_OUT_I(2)

	From	To	Count	Threshold
Bin	0	1	3234	1
Bin	1	0	3837	1

Signal:

TXTB_PORT_B_DATA_OUT_I(1)

	From	To	Count	Threshold
Bin	0	1	2781	1
Bin	1	0	3377	1

Signal:

TXTB_PORT_B_DATA_OUT_I(0)

	From	To	Count	Threshold
Bin	0	1	3526	1
Bin	1	0	4121	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	964	1

Signal:

PARITY_WORD(20)

	From	To	Count	Threshold
Bin	0	1	127	1
Bin	1	0	2769	1

Signal:

PARITY_WORD(19)

	From	To	Count	Threshold
Bin	0	1	6	1
Bin	1	0	2890	1

Signal:

PARITY_WORD(18)

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	2884	1

Signal:

PARITY_WORD(17)

	From	To	Count	Threshold
Bin	0	1	34	1
Bin	1	0	2862	1

Signal:

PARITY_WORD(16)

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	2851	1

Signal:

PARITY_WORD(15)

	From	To	Count	Threshold
Bin	0	1	56	1
Bin	1	0	2840	1

Signal:

PARITY_WORD(14)

	From	To	Count	Threshold
Bin	0	1	55	1
Bin	1	0	2841	1

Signal:

PARITY_WORD(13)

	From	To	Count	Threshold
Bin	0	1	43	1
Bin	1	0	2853	1

Signal:

PARITY_WORD(12)

	From	To	Count	Threshold
Bin	0	1	49	1
Bin	1	0	2847	1

Signal:

PARITY_WORD(11)

	From	To	Count	Threshold
Bin	0	1	86	1
Bin	1	0	2810	1

Signal:

PARITY_WORD(10)

	From	To	Count	Threshold
Bin	0	1	91	1
Bin	1	0	2805	1

Signal:

PARITY_WORD(9)

	From	To	Count	Threshold
Bin	0	1	107	1
Bin	1	0	2789	1

Signal:

PARITY_WORD(8)

	From	To	Count	Threshold
Bin	0	1	119	1
Bin	1	0	2777	1

Signal:

PARITY_WORD(7)

	From	To	Count	Threshold
Bin	0	1	129	1
Bin	1	0	2767	1

Signal:

PARITY_WORD(6)

	From	To	Count	Threshold
Bin	0	1	187	1
Bin	1	0	2709	1

Signal:

PARITY_WORD(5)

	From	To	Count	Threshold
Bin	0	1	352	1
Bin	1	0	2544	1

Signal:

PARITY_WORD(4)

	From	To	Count	Threshold
Bin	0	1	705	1
Bin	1	0	2191	1

Signal:

PARITY_WORD(3)

	From	To	Count	Threshold
Bin	0	1	1262	1
Bin	1	0	1634	1

Signal:

PARITY_WORD(2)

	From	To	Count	Threshold
Bin	0	1	1560	1
Bin	1	0	1336	1

Signal:

PARITY_WORD(1)

	From	To	Count	Threshold
Bin	0	1	986	1
Bin	1	0	1910	1

Signal:

PARITY_WORD(0)

	From	To	Count	Threshold
Bin	0	1	1167	1
Bin	1	0	1729	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	4609	1
Bin	1	0	4022	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	4766	1
Bin	1	0	5426	1

Uncovered expressions:

Excluded expressions:

"and" expression

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and

	Evaluated to	Count	Threshold
Bin	False	2875	1
Bin	True	1751	1

"and" expression

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))

	LHS	RHS	Count	Threshold
Bin	True	False	1447	1
Bin	True	True	304	1

"=" expression

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	54707	1
Bin	True	49534119	1

"=" expression

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	4134	1
Bin	True	186043	1

"=" expression

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	34532	1
Bin	True	1552223	1

"=" expression

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')

	Evaluated to	Count	Threshold
Bin	False	3875	1
Bin	True	171889	1

"=" expression

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')

	Evaluated to	Count	Threshold
Bin	False	18103	1
Bin	True	2321	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd

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