NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	90.0 % (27/30)	N.A.	N.A.	99.8 % (1638/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (13/13)	N.A.	N.A.	100.0 % (105/105)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (516/516)	93.3 % (14/15)	N.A.	N.A.	99.8 % (561/562)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208: txtb_port_b_data_out <= txtb_port_b_data_out_i;
Count: 18976
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 4626
Threshold: 1

Signal assignment statement on line 277:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 307
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 4319
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 49965312
Threshold: 1

Signal assignment statement on line 283:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 49910570
Threshold: 1

Signal assignment statement on line 285:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 54742
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 190009
Threshold: 1

Signal assignment statement on line 287:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 185863
Threshold: 1

Signal assignment statement on line 289:

289: mr_tst_control_twrstb;
Count: 4146
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 1614750
Threshold: 1

Signal assignment statement on line 291:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 1580187
Threshold: 1

Signal assignment statement on line 293:

293: mr_tst_wdata_tst_wdata;
Count: 34563
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 179957
Threshold: 1

Signal assignment statement on line 296:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 176077
Threshold: 1

Signal assignment statement on line 298:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 3880
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 20250
Threshold: 1

Signal assignment statement on line 300:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 2328
Threshold: 1

Signal assignment statement on line 302:

302: (others => '0');
Count: 17922
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	307	1
Bin	False	4319	1

	Evaluated to	Count	Threshold
Bin	True	49910570	1
Bin	False	54742	1

	Evaluated to	Count	Threshold
Bin	True	185863	1
Bin	False	4146	1

	Evaluated to	Count	Threshold
Bin	True	1580187	1
Bin	False	34563	1

	Evaluated to	Count	Threshold
Bin	True	176077	1
Bin	False	3880	1

	Evaluated to	Count	Threshold
Bin	True	2328	1
Bin	False	17922	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	493	1
Bin	(31)	1	0	1153	1
Bin	(30)	0	1	492	1
Bin	(30)	1	0	1152	1
Bin	(29)	0	1	482	1
Bin	(29)	1	0	1142	1
Bin	(28)	0	1	560	1
Bin	(28)	1	0	1220	1
Bin	(27)	0	1	533	1
Bin	(27)	1	0	1193	1
Bin	(26)	0	1	552	1
Bin	(26)	1	0	1212	1
Bin	(25)	0	1	552	1
Bin	(25)	1	0	1212	1
Bin	(24)	0	1	565	1
Bin	(24)	1	0	1225	1
Bin	(23)	0	1	572	1
Bin	(23)	1	0	1232	1
Bin	(22)	0	1	537	1
Bin	(22)	1	0	1197	1
Bin	(21)	0	1	560	1
Bin	(21)	1	0	1220	1
Bin	(20)	0	1	540	1
Bin	(20)	1	0	1200	1
Bin	(19)	0	1	573	1
Bin	(19)	1	0	1233	1
Bin	(18)	0	1	574	1
Bin	(18)	1	0	1234	1
Bin	(17)	0	1	519	1
Bin	(17)	1	0	1179	1
Bin	(16)	0	1	527	1
Bin	(16)	1	0	1187	1
Bin	(15)	0	1	525	1
Bin	(15)	1	0	1185	1
Bin	(14)	0	1	529	1
Bin	(14)	1	0	1189	1
Bin	(13)	0	1	516	1
Bin	(13)	1	0	1176	1
Bin	(12)	0	1	524	1
Bin	(12)	1	0	1184	1
Bin	(11)	0	1	525	1
Bin	(11)	1	0	1185	1
Bin	(10)	0	1	506	1
Bin	(10)	1	0	1166	1
Bin	(9)	0	1	528	1
Bin	(9)	1	0	1188	1
Bin	(8)	0	1	518	1
Bin	(8)	1	0	1178	1
Bin	(7)	0	1	573	1
Bin	(7)	1	0	1233	1
Bin	(6)	0	1	554	1
Bin	(6)	1	0	1214	1
Bin	(5)	0	1	510	1
Bin	(5)	1	0	1170	1
Bin	(4)	0	1	529	1
Bin	(4)	1	0	1189	1
Bin	(3)	0	1	536	1
Bin	(3)	1	0	1196	1
Bin	(2)	0	1	549	1
Bin	(2)	1	0	1209	1
Bin	(1)	0	1	562	1
Bin	(1)	1	0	1222	1
Bin	(0)	0	1	528	1
Bin	(0)	1	0	1188	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1015	1
Bin	(31)	1	0	1635	1
Bin	(30)	0	1	1063	1
Bin	(30)	1	0	1683	1
Bin	(29)	0	1	977	1
Bin	(29)	1	0	1597	1
Bin	(28)	0	1	2792	1
Bin	(28)	1	0	3399	1
Bin	(27)	0	1	2892	1
Bin	(27)	1	0	3501	1
Bin	(26)	0	1	2755	1
Bin	(26)	1	0	3360	1
Bin	(25)	0	1	2709	1
Bin	(25)	1	0	3317	1
Bin	(24)	0	1	2966	1
Bin	(24)	1	0	3571	1
Bin	(23)	0	1	2592	1
Bin	(23)	1	0	3199	1
Bin	(22)	0	1	2633	1
Bin	(22)	1	0	3243	1
Bin	(21)	0	1	3175	1
Bin	(21)	1	0	3775	1
Bin	(20)	0	1	2748	1
Bin	(20)	1	0	3348	1
Bin	(19)	0	1	3251	1
Bin	(19)	1	0	3849	1
Bin	(18)	0	1	2660	1
Bin	(18)	1	0	3267	1
Bin	(17)	0	1	2228	1
Bin	(17)	1	0	2843	1
Bin	(16)	0	1	2243	1
Bin	(16)	1	0	2859	1
Bin	(15)	0	1	2054	1
Bin	(15)	1	0	2671	1
Bin	(14)	0	1	2312	1
Bin	(14)	1	0	2928	1
Bin	(13)	0	1	2251	1
Bin	(13)	1	0	2865	1
Bin	(12)	0	1	2078	1
Bin	(12)	1	0	2693	1
Bin	(11)	0	1	1928	1
Bin	(11)	1	0	2546	1
Bin	(10)	0	1	2386	1
Bin	(10)	1	0	3001	1
Bin	(9)	0	1	2720	1
Bin	(9)	1	0	3319	1
Bin	(8)	0	1	2581	1
Bin	(8)	1	0	3192	1
Bin	(7)	0	1	3743	1
Bin	(7)	1	0	4328	1
Bin	(6)	0	1	3412	1
Bin	(6)	1	0	4003	1
Bin	(5)	0	1	3212	1
Bin	(5)	1	0	3820	1
Bin	(4)	0	1	2429	1
Bin	(4)	1	0	3042	1
Bin	(3)	0	1	2837	1
Bin	(3)	1	0	3442	1
Bin	(2)	0	1	3033	1
Bin	(2)	1	0	3631	1
Bin	(1)	0	1	3175	1
Bin	(1)	1	0	3772	1
Bin	(0)	0	1	3518	1
Bin	(0)	1	0	4116	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1635	1
Bin	1	0	2295	1

Signal:

TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	249441	1
Bin	(4)	1	0	24664244	1
Bin	(3)	0	1	406715	1
Bin	(3)	1	0	24506934	1
Bin	(2)	0	1	307699	1
Bin	(2)	1	0	24606404	1
Bin	(1)	0	1	24366729	1
Bin	(1)	1	0	548202	1
Bin	(0)	0	1	15896548	1
Bin	(0)	1	0	9020125	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	46368	1
Bin	1	0	47178	1

Signal:

TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	32790	1
Bin	(31)	1	0	753965	1
Bin	(30)	0	1	33488	1
Bin	(30)	1	0	753275	1
Bin	(29)	0	1	34587	1
Bin	(29)	1	0	752162	1
Bin	(28)	0	1	49000	1
Bin	(28)	1	0	737793	1
Bin	(27)	0	1	46651	1
Bin	(27)	1	0	740138	1
Bin	(26)	0	1	45075	1
Bin	(26)	1	0	741722	1
Bin	(25)	0	1	52712	1
Bin	(25)	1	0	734085	1
Bin	(24)	0	1	42476	1
Bin	(24)	1	0	744305	1
Bin	(23)	0	1	41901	1
Bin	(23)	1	0	744898	1
Bin	(22)	0	1	47995	1
Bin	(22)	1	0	738788	1
Bin	(21)	0	1	40961	1
Bin	(21)	1	0	745856	1
Bin	(20)	0	1	43264	1
Bin	(20)	1	0	743549	1
Bin	(19)	0	1	69313	1
Bin	(19)	1	0	717524	1
Bin	(18)	0	1	78543	1
Bin	(18)	1	0	708338	1
Bin	(17)	0	1	80305	1
Bin	(17)	1	0	706496	1
Bin	(16)	0	1	140644	1
Bin	(16)	1	0	646174	1
Bin	(15)	0	1	39132	1
Bin	(15)	1	0	747687	1
Bin	(14)	0	1	48488	1
Bin	(14)	1	0	738303	1
Bin	(13)	0	1	42214	1
Bin	(13)	1	0	744595	1
Bin	(12)	0	1	44149	1
Bin	(12)	1	0	742652	1
Bin	(11)	0	1	64628	1
Bin	(11)	1	0	722175	1
Bin	(10)	0	1	68369	1
Bin	(10)	1	0	718420	1
Bin	(9)	0	1	87247	1
Bin	(9)	1	0	699578	1
Bin	(8)	0	1	85798	1
Bin	(8)	1	0	700967	1
Bin	(7)	0	1	75019	1
Bin	(7)	1	0	711826	1
Bin	(6)	0	1	70469	1
Bin	(6)	1	0	716398	1
Bin	(5)	0	1	70215	1
Bin	(5)	1	0	716580	1
Bin	(4)	0	1	86684	1
Bin	(4)	1	0	700141	1
Bin	(3)	0	1	95559	1
Bin	(3)	1	0	691244	1
Bin	(2)	0	1	105258	1
Bin	(2)	1	0	681580	1
Bin	(1)	0	1	163176	1
Bin	(1)	1	0	623671	1
Bin	(0)	0	1	139094	1
Bin	(0)	1	0	647818	1

Signal:

TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	11003	1
Bin	(4)	1	0	11663	1
Bin	(3)	0	1	496	1
Bin	(3)	1	0	1156	1
Bin	(2)	0	1	16840	1
Bin	(2)	1	0	17500	1
Bin	(1)	0	1	13500	1
Bin	(1)	1	0	13501	1
Bin	(0)	0	1	37175	1
Bin	(0)	1	0	37834	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1015	1
Bin	(31)	1	0	1635	1
Bin	(30)	0	1	1063	1
Bin	(30)	1	0	1683	1
Bin	(29)	0	1	977	1
Bin	(29)	1	0	1597	1
Bin	(28)	0	1	2792	1
Bin	(28)	1	0	3399	1
Bin	(27)	0	1	2892	1
Bin	(27)	1	0	3501	1
Bin	(26)	0	1	2755	1
Bin	(26)	1	0	3360	1
Bin	(25)	0	1	2709	1
Bin	(25)	1	0	3317	1
Bin	(24)	0	1	2966	1
Bin	(24)	1	0	3571	1
Bin	(23)	0	1	2592	1
Bin	(23)	1	0	3199	1
Bin	(22)	0	1	2633	1
Bin	(22)	1	0	3243	1
Bin	(21)	0	1	3175	1
Bin	(21)	1	0	3775	1
Bin	(20)	0	1	2748	1
Bin	(20)	1	0	3348	1
Bin	(19)	0	1	3251	1
Bin	(19)	1	0	3849	1
Bin	(18)	0	1	2660	1
Bin	(18)	1	0	3267	1
Bin	(17)	0	1	2228	1
Bin	(17)	1	0	2843	1
Bin	(16)	0	1	2243	1
Bin	(16)	1	0	2859	1
Bin	(15)	0	1	2054	1
Bin	(15)	1	0	2671	1
Bin	(14)	0	1	2312	1
Bin	(14)	1	0	2928	1
Bin	(13)	0	1	2251	1
Bin	(13)	1	0	2865	1
Bin	(12)	0	1	2078	1
Bin	(12)	1	0	2693	1
Bin	(11)	0	1	1928	1
Bin	(11)	1	0	2546	1
Bin	(10)	0	1	2386	1
Bin	(10)	1	0	3001	1
Bin	(9)	0	1	2720	1
Bin	(9)	1	0	3319	1
Bin	(8)	0	1	2581	1
Bin	(8)	1	0	3192	1
Bin	(7)	0	1	3743	1
Bin	(7)	1	0	4328	1
Bin	(6)	0	1	3412	1
Bin	(6)	1	0	4003	1
Bin	(5)	0	1	3212	1
Bin	(5)	1	0	3820	1
Bin	(4)	0	1	2429	1
Bin	(4)	1	0	3042	1
Bin	(3)	0	1	2837	1
Bin	(3)	1	0	3442	1
Bin	(2)	0	1	3033	1
Bin	(2)	1	0	3631	1
Bin	(1)	0	1	3175	1
Bin	(1)	1	0	3772	1
Bin	(0)	0	1	3518	1
Bin	(0)	1	0	4116	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	307	1
Bin	1	0	967	1

Signal:

PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	115	1
Bin	(20)	1	0	2850	1
Bin	(19)	0	1	4	1
Bin	(19)	1	0	2961	1
Bin	(18)	0	1	22	1
Bin	(18)	1	0	2943	1
Bin	(17)	0	1	28	1
Bin	(17)	1	0	2937	1
Bin	(16)	0	1	16	1
Bin	(16)	1	0	2949	1
Bin	(15)	0	1	31	1
Bin	(15)	1	0	2934	1
Bin	(14)	0	1	32	1
Bin	(14)	1	0	2933	1
Bin	(13)	0	1	67	1
Bin	(13)	1	0	2898	1
Bin	(12)	0	1	50	1
Bin	(12)	1	0	2915	1
Bin	(11)	0	1	102	1
Bin	(11)	1	0	2863	1
Bin	(10)	0	1	104	1
Bin	(10)	1	0	2861	1
Bin	(9)	0	1	126	1
Bin	(9)	1	0	2839	1
Bin	(8)	0	1	121	1
Bin	(8)	1	0	2844	1
Bin	(7)	0	1	193	1
Bin	(7)	1	0	2772	1
Bin	(6)	0	1	188	1
Bin	(6)	1	0	2777	1
Bin	(5)	0	1	389	1
Bin	(5)	1	0	2576	1
Bin	(4)	0	1	732	1
Bin	(4)	1	0	2233	1
Bin	(3)	0	1	1331	1
Bin	(3)	1	0	1634	1
Bin	(2)	0	1	1637	1
Bin	(2)	1	0	1328	1
Bin	(1)	0	1	997	1
Bin	(1)	1	0	1968	1
Bin	(0)	0	1	1145	1
Bin	(0)	1	0	1820	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	4595	1
Bin	1	0	4008	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	4565	1
Bin	1	0	5225	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

If statement on lines 277 to 280:

Signal assignment statement on line 277:

Signal assignment statement on line 280:

If statement on lines 283 to 285:

Signal assignment statement on line 283:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 287:

Signal assignment statement on line 289:

If statement on lines 291 to 293:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 296 to 298:

Signal assignment statement on line 296:

Signal assignment statement on line 298:

If statement on lines 300 to 302:

Signal assignment statement on line 300:

Signal assignment statement on line 302:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

"if" / "when" / "else" condition on line 283:

"if" / "when" / "else" condition on line 287:

"if" / "when" / "else" condition on line 291:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 300:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

"and" expression on lines 277 to 278:

Excluded expressions:

Covered expressions:

"and" expression on lines 277 to 278:

"=" expression on line 277:

"=" expression on line 283:

"=" expression on line 287:

"=" expression on line 291:

"=" expression on line 296:

"=" expression on line 300:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: