NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.GLOBAL_RST_RST_REG_INST.MUX2_RES_TST_INST	100.0 % (3/3)	100.0 % (2/2)	100.0 % (8/8)	N.A.	N.A.	N.A.	100.0 % (13/13)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.GLOBAL_RST_RST_REG_INST.MUX2_RES_TST_INST

100.0 % (3/3)

100.0 % (2/2)

100.0 % (8/8)

N.A.

100.0 % (13/13)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement on lines 106 to 108:

106:    with sel select z <= 
107:        a when '0', 
108:        b when others;

Count: 33720
Threshold: 1

Signal assignment statement on line 107:

107: a when '0',
Count: 32114
Threshold: 1

Signal assignment statement on line 108:

108: b when others;
Count: 1606
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice on line 107:

107: a when '0',

	Choice of	Count	Threshold
Bin	`'0'`	32114	1

"case" / "with" / "select" choice on line 108:

108: b when others;

	Choice of	Count	Threshold
Bin	`others`	1606	1

Uncovered toggles:

Excluded toggles:

Port:

A

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

B

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SEL

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

Z

	From	To	Count	Threshold
Bin	0	1	8084	1
Bin	1	0	8072	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.GLOBAL_RST_RST_REG_INST.MUX2_RES_TST_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Sequential statement on lines 106 to 108:

Signal assignment statement on line 107:

Signal assignment statement on line 108:

Uncovered branches:

Excluded branches:

Covered branches:

"case" / "with" / "select" choice on line 107:

"case" / "with" / "select" choice on line 108:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Covered toggles:

Port:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: