NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.TRIGGER_MUX_INST

File:  /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Nested Instances Statement Branch Toggle Expression FSM state Functional Average
CRC_TRIG_TX_WBS_REG 100.0 % (3/3) 100.0 % (4/4) 100.0 % (8/8) 100.0 % (2/2) N.A. N.A. 100.0 % (17/17)
CRC_DATA_RX_WBS_REG 100.0 % (4/4) 100.0 % (6/6) 100.0 % (10/10) 100.0 % (4/4) N.A. N.A. 100.0 % (24/24)

Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.TRIGGER_MUX_INST 100.0 % (22/22) 100.0 % (16/16) 100.0 % (38/38) 100.0 % (46/46) N.A. N.A. 100.0 % (122/122)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 188 to 190:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0') 
189:                         else 
190:                     '0'; 

Count: 24665147
Threshold: 1

Signal assignment statement on line 188:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0') 
Count: 11391077
Threshold: 1

Signal assignment statement on line 190:

190:                     '0'
Count: 13274070
Threshold: 1

If statement on lines 192 to 194:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
193:                         else 
194:                     '0'; 

Count: 22790009
Threshold: 1

Signal assignment statement on line 192:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
Count: 10359813
Threshold: 1

Signal assignment statement on line 194:

194:                     '0'
Count: 12430196
Threshold: 1

Signal assignment statement on line 203:

203:    bst_trigger <= tx_trigger
Count: 22785355
Threshold: 1

Signal assignment statement on line 204:

204:    bds_trigger <= rx_triggers(1)
Count: 45560178
Threshold: 1

If statement on lines 214 to 216:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
215:                           else 
216:                       '0'; 

Count: 22790009
Threshold: 1

Signal assignment statement on line 214:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
Count: 10359813
Threshold: 1

Signal assignment statement on line 216:

216:                       '0'
Count: 12430196
Threshold: 1

If statement on lines 218 to 220:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0') 
219:                           else 
220:                       '0'; 

Count: 24665147
Threshold: 1

Signal assignment statement on line 218:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0') 
Count: 11391077
Threshold: 1

Signal assignment statement on line 220:

220:                       '0'
Count: 13274070
Threshold: 1

If statement on lines 243 to 245:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
244:                       '1' when (tx_trigger_q = '1') else 
245:                       '0'; 

Count: 24687107
Threshold: 1

Signal assignment statement on line 243:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
Count: 215455
Threshold: 1

Signal assignment statement on line 244:

244:                       '1' when (tx_trigger_q = '1') else 
Count: 12509781
Threshold: 1

Signal assignment statement on line 245:

245:                       '0'
Count: 11961871
Threshold: 1

If statement on lines 267 to 269:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
268:                       '1' when (rx_triggers(0) = '1') else 
269:                       '0'; 

Count: 22818634
Threshold: 1

Signal assignment statement on line 267:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
Count: 159300
Threshold: 1

Signal assignment statement on line 268:

268:                       '1' when (rx_triggers(0) = '1') else 
Count: 11302587
Threshold: 1

Signal assignment statement on line 269:

269:                       '0'
Count: 11356747
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 188:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0'
Evaluated toCountThreshold
BinTrue113910771
BinFalse132740701

"if" / "when" / "else" condition on line 192:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0'
Evaluated toCountThreshold
BinTrue103598131
BinFalse124301961

"if" / "when" / "else" condition on line 214:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0'
Evaluated toCountThreshold
BinTrue103598131
BinFalse124301961

"if" / "when" / "else" condition on line 218:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0'
Evaluated toCountThreshold
BinTrue113910771
BinFalse132740701

"if" / "when" / "else" condition on line 243:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
Evaluated toCountThreshold
BinTrue2154551
BinFalse244716521

"if" / "when" / "else" condition on line 244:

244:                       '1' when (tx_trigger_q = '1') else 
Evaluated toCountThreshold
BinTrue125097811
BinFalse119618711

"if" / "when" / "else" condition on line 267:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
Evaluated toCountThreshold
BinTrue1593001
BinFalse226593341

"if" / "when" / "else" condition on line 268:

268:                       '1' when (rx_triggers(0) = '1') else 
Evaluated toCountThreshold
BinTrue113025871
BinFalse113567471

Uncovered toggles:

Excluded toggles:

Port:

 CLK_SYS
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RES_N
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 RX_TRIGGERS
ElementFromToCountThresholdExcluded due to
Bin(1)0101Exclude file
Bin(1)1001Exclude file
Bin(0)0101Exclude file
Bin(0)1001Exclude file

Port:

 TX_TRIGGER
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 DATA_HALT
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 DESTUFFED
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 FIXED_STUFF
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Port:

 BDS_DATA_IN
FromToCountThresholdExcluded due to
Bin0101Exclude file
Bin1001Exclude file

Covered toggles:

Port:

 PC_TX_TRIGGER
FromToCountThreshold
Bin01113910771
Bin10113926771

Port:

 PC_RX_TRIGGER
FromToCountThreshold
Bin01103598131
Bin10103614141

Port:

 BST_TRIGGER
FromToCountThreshold
Bin01113910771
Bin10113926771

Port:

 BDS_TRIGGER
FromToCountThreshold
Bin01227784881
Bin10227800891

Port:

 CRC_TRIG_RX_NBS
FromToCountThreshold
Bin01103598131
Bin10103614141

Port:

 CRC_TRIG_TX_NBS
FromToCountThreshold
Bin01113910771
Bin10113926771

Port:

 CRC_TRIG_RX_WBS
FromToCountThreshold
Bin01113025871
Bin10113041881

Port:

 CRC_TRIG_TX_WBS
FromToCountThreshold
Bin01114239991
Bin10114255991

Port:

 CRC_DATA_RX_WBS
FromToCountThreshold
Bin0113974961
Bin1013990861

Signal:

 TX_TRIGGER_Q
FromToCountThreshold
Bin01113869441
Bin10113885441

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 188:

 tx_trigger = '1' and data_halt = '0' 
 <-----LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue117075901
BinTrueFalse6249831
BinTrueTrue113910771

"=" expression on line 188:

 tx_trigger = '1' 
Evaluated toCountThreshold
BinFalse126490871
BinTrue120160601

"=" expression on line 188:

 data_halt = '0' 
Evaluated toCountThreshold
BinFalse15664801
BinTrue230986671

"and" expression on line 192:

 rx_triggers(0) = '1' and destuffed = '0' 
 <-------LHS-------->     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue103821461
BinTrueFalse10224241
BinTrueTrue103598131

"=" expression on line 192:

 rx_triggers(0) = '1' 
Evaluated toCountThreshold
BinFalse114077721
BinTrue113822371

"=" expression on line 192:

 destuffed = '0' 
Evaluated toCountThreshold
BinFalse20480501
BinTrue207419591

"and" expression on line 214:

 rx_triggers(0) = '1' and destuffed = '0' 
 <-------LHS-------->     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue103821461
BinTrueFalse10224241
BinTrueTrue103598131

"=" expression on line 214:

 rx_triggers(0) = '1' 
Evaluated toCountThreshold
BinFalse114077721
BinTrue113822371

"=" expression on line 214:

 destuffed = '0' 
Evaluated toCountThreshold
BinFalse20480501
BinTrue207419591

"and" expression on line 218:

 tx_trigger = '1' and data_halt = '0' 
 <-----LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue117075901
BinTrueFalse6249831
BinTrueTrue113910771

"=" expression on line 218:

 tx_trigger = '1' 
Evaluated toCountThreshold
BinFalse126490871
BinTrue120160601

"=" expression on line 218:

 data_halt = '0' 
Evaluated toCountThreshold
BinFalse15664801
BinTrue230986671

"and" expression on line 243:

 fixed_stuff = '1' and data_halt = '1' 
 <------LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue13554341
BinTrueFalse7665721
BinTrueTrue2154551

"=" expression on line 243:

 fixed_stuff = '1' 
Evaluated toCountThreshold
BinFalse237050801
BinTrue9820271

"=" expression on line 243:

 data_halt = '1' 
Evaluated toCountThreshold
BinFalse231162181
BinTrue15708891

"=" expression on line 244:

 tx_trigger_q = '1' 
Evaluated toCountThreshold
BinFalse119618711
BinTrue125097811

"and" expression on line 267:

 fixed_stuff = '1' and destuffed = '1' 
 <------LHS------>     <-----RHS-----> 

LHSRHSCountThreshold
BinFalseTrue18860081
BinTrueFalse5705101
BinTrueTrue1593001

"=" expression on line 267:

 fixed_stuff = '1' 
Evaluated toCountThreshold
BinFalse220888241
BinTrue7298101

"=" expression on line 267:

 destuffed = '1' 
Evaluated toCountThreshold
BinFalse207733261
BinTrue20453081

"=" expression on line 268:

 rx_triggers(0) = '1' 
Evaluated toCountThreshold
BinFalse113567471
BinTrue113025871

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: