NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CRC_TRIG_TX_WBS_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)
CRC_DATA_RX_WBS_REG	100.0 % (4/4)	100.0 % (6/6)	100.0 % (10/10)	100.0 % (4/4)	N.A.	N.A.	100.0 % (24/24)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.TRIGGER_MUX_INST	100.0 % (20/20)	100.0 % (16/16)	100.0 % (38/38)	100.0 % (46/46)	N.A.	N.A.	100.0 % (120/120)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0') 
189:                         else 
190:                     '0';

Count: 23980675
Threshold: 1

Signal assignment statement:

188: pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0')
Count: 11044003
Threshold: 1

Signal assignment statement:

190: '0';
Count: 12936672
Threshold: 1

If statement:

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
193:                         else 
194:                     '0';

Count: 22095805
Threshold: 1

Signal assignment statement:

192: pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0')
Count: 10015414
Threshold: 1

Signal assignment statement:

194: '0';
Count: 12080391
Threshold: 1

If statement:

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
215:                           else 
216:                       '0';

Count: 22095805
Threshold: 1

Signal assignment statement:

214: crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0')
Count: 10015414
Threshold: 1

Signal assignment statement:

216: '0';
Count: 12080391
Threshold: 1

If statement:

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0') 
219:                           else 
220:                       '0';

Count: 23980675
Threshold: 1

Signal assignment statement:

218: crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0')
Count: 11044003
Threshold: 1

Signal assignment statement:

220: '0';
Count: 12936672
Threshold: 1

If statement:

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
244:                       '1' when (tx_trigger_q = '1') else 
245:                       '0';

Count: 24002725
Threshold: 1

Signal assignment statement:

243: crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else
Count: 230213
Threshold: 1

Signal assignment statement:

244: '1' when (tx_trigger_q = '1') else
Count: 12160263
Threshold: 1

Signal assignment statement:

245: '0';
Count: 11612249
Threshold: 1

If statement:

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
268:                       '1' when (rx_triggers(0) = '1') else 
269:                       '0';

Count: 22124337
Threshold: 1

Signal assignment statement:

267: crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else
Count: 159106
Threshold: 1

Signal assignment statement:

268: '1' when (rx_triggers(0) = '1') else
Count: 10955682
Threshold: 1

Signal assignment statement:

269: '0';
Count: 11009549
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

188: pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0')

	Evaluated to	Count	Threshold
Bin	True	11044003	1
Bin	False	12936672	1

"if" / "when" / "else" condition:

192: pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0')

	Evaluated to	Count	Threshold
Bin	True	10015414	1
Bin	False	12080391	1

"if" / "when" / "else" condition:

214: crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0')

	Evaluated to	Count	Threshold
Bin	True	10015414	1
Bin	False	12080391	1

"if" / "when" / "else" condition:

218: crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0')

	Evaluated to	Count	Threshold
Bin	True	11044003	1
Bin	False	12936672	1

"if" / "when" / "else" condition:

243: crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else

	Evaluated to	Count	Threshold
Bin	True	230213	1
Bin	False	23772512	1

"if" / "when" / "else" condition:

244: '1' when (tx_trigger_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	12160263	1
Bin	False	11612249	1

"if" / "when" / "else" condition:

267: crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else

	Evaluated to	Count	Threshold
Bin	True	159106	1
Bin	False	21965231	1

"if" / "when" / "else" condition:

268: '1' when (rx_triggers(0) = '1') else

	Evaluated to	Count	Threshold
Bin	True	10955682	1
Bin	False	11009549	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

RX_TRIGGERS(1)

	From	To	Count	Threshold
Bin	0	1	33119362	1
Bin	1	0	33122562	1

Port:

RX_TRIGGERS(0)

	From	To	Count	Threshold
Bin	0	1	22070470	1
Bin	1	0	44169854	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

DATA_HALT

	From	To	Count	Threshold
Bin	0	1	944735	1
Bin	1	0	946335	1

Port:

DESTUFFED

	From	To	Count	Threshold
Bin	0	1	1019821	1
Bin	1	0	1021421	1

Port:

FIXED_STUFF

	From	To	Count	Threshold
Bin	0	1	13466	1
Bin	1	0	15066	1

Port:

BDS_DATA_IN

	From	To	Count	Threshold
Bin	0	1	1401177	1
Bin	1	0	1399577	1

Port:

PC_TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

PC_RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10015414	1
Bin	1	0	10017014	1

Port:

BST_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

BDS_TRIGGER

	From	To	Count	Threshold
Bin	0	1	22084127	1
Bin	1	0	22085727	1

Port:

CRC_TRIG_RX_NBS

	From	To	Count	Threshold
Bin	0	1	10015414	1
Bin	1	0	10017014	1

Port:

CRC_TRIG_TX_NBS

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Port:

CRC_TRIG_RX_WBS

	From	To	Count	Threshold
Bin	0	1	10955682	1
Bin	1	0	10957282	1

Port:

CRC_TRIG_TX_WBS

	From	To	Count	Threshold
Bin	0	1	11079571	1
Bin	1	0	11081170	1

Port:

CRC_DATA_RX_WBS

	From	To	Count	Threshold
Bin	0	1	1396008	1
Bin	1	0	1397599	1

Signal:

TX_TRIGGER_Q

	From	To	Count	Threshold
Bin	0	1	11039962	1
Bin	1	0	11041561	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

188: pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0')

	Evaluated to	Count	Threshold
Bin	False	12307954	1
Bin	True	11672721	1

"=" expression

188: pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0')

	Evaluated to	Count	Threshold
Bin	False	1575053	1
Bin	True	22405622	1

"and" expression

188:    pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0') 
                                   <-----LHS------>     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	11361619	1
Bin	True	False	628718	1
Bin	True	True	11044003	1

"=" expression

192: pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0')

	Evaluated to	Count	Threshold
Bin	False	11060570	1
Bin	True	11035235	1

"=" expression

192: pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0')

	Evaluated to	Count	Threshold
Bin	False	2042842	1
Bin	True	20052963	1

"and" expression

192:    pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
                                   <-------LHS-------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	10037549	1
Bin	True	False	1019821	1
Bin	True	True	10015414	1

"=" expression

214: crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0')

	Evaluated to	Count	Threshold
Bin	False	11060570	1
Bin	True	11035235	1

"=" expression

214: crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0')

	Evaluated to	Count	Threshold
Bin	False	2042842	1
Bin	True	20052963	1

"and" expression

214:    crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0') 
                                     <-------LHS-------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	10037549	1
Bin	True	False	1019821	1
Bin	True	True	10015414	1

"=" expression

218: crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0')

	Evaluated to	Count	Threshold
Bin	False	12307954	1
Bin	True	11672721	1

"=" expression

218: crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0')

	Evaluated to	Count	Threshold
Bin	False	1575053	1
Bin	True	22405622	1

"and" expression

218:    crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0') 
                                     <-----LHS------>     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	11361619	1
Bin	True	False	628718	1
Bin	True	True	11044003	1

"=" expression

243: crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else

	Evaluated to	Count	Threshold
Bin	False	23004088	1
Bin	True	998637	1

"=" expression

243: crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else

	Evaluated to	Count	Threshold
Bin	False	22423437	1
Bin	True	1579288	1

"and" expression

243:    crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else 
                                     <------LHS------>     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	1349075	1
Bin	True	False	768424	1
Bin	True	True	230213	1

"=" expression

244: '1' when (tx_trigger_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	11612249	1
Bin	True	12160263	1

"=" expression

267: crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else

	Evaluated to	Count	Threshold
Bin	False	21395227	1
Bin	True	729110	1

"=" expression

267: crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else

	Evaluated to	Count	Threshold
Bin	False	20084249	1
Bin	True	2040088	1

"and" expression

267:    crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else 
                                     <------LHS------>     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	True	1880982	1
Bin	True	False	570004	1
Bin	True	True	159106	1

"=" expression

268: '1' when (rx_triggers(0) = '1') else

	Evaluated to	Count	Threshold
Bin	False	11009549	1
Bin	True	10955682	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.TRIGGER_MUX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/trigger_mux.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"and" expression