NVC code coverage report

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

BIT_GEN(0)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(1)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(2)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(3)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(4)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(5)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

BIT_GEN(6)

100.0 % (4/4)

100.0 % (6/6)

N.A.

100.0 % (4/4)

N.A.

100.0 % (14/14)

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_PROP_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (54/54)	100.0 % (6/6)	N.A.	N.A.	100.0 % (61/61)

Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_PROP_REG_COMP

100.0 % (1/1)

N.A.

100.0 % (54/54)

100.0 % (6/6)

N.A.

100.0 % (61/61)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 321594
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	31028760	1
Bin	1	0	31030360	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	109550	1
Bin	1	0	980295	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	103929	1
Bin	1	0	985916	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	162358	1
Bin	1	0	927487	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	135873	1
Bin	1	0	953972	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	159944	1
Bin	1	0	929901	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	236123	1
Bin	1	0	853722	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	198401	1
Bin	1	0	891444	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	144497	1
Bin	1	0	146097	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	6623	1
Bin	1	0	8223	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	1800	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	312	1
Bin	1	0	1909	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	223	1
Bin	1	0	1820	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	1870	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	3820	1
Bin	1	0	2221	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	261	1
Bin	1	0	1858	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	1793	1
Bin	1	0	194	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	202	1
Bin	1	0	6445	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	345	1
Bin	1	0	6302	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	259	1
Bin	1	0	6388	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	317	1
Bin	1	0	6330	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	4344	1
Bin	1	0	2303	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	288	1
Bin	1	0	6359	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	6453	1
Bin	1	0	194	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	6306	1
Bin	1	0	7906	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	6623	1
Bin	'1'	'0'	154280	1
Bin	'1'	'1'	6311	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	55537	1
Bin	'1'	'0'	5	1
Bin	'1'	'1'	6306	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_PROP_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: