NVC code coverage report

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_CFG_CAPTURE_INST	100.0 % (25/25)	100.0 % (14/14)	100.0 % (270/270)	100.0 % (20/20)	N.A.	N.A.	100.0 % (329/329)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 200 to 206:

200:        if (res_n = '0') then 
201:            mr_settings_ena_reg     <= '0'; 
...
205:            mr_settings_ena_reg_2   <= mr_settings_ena_reg; 
206:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 201:

201: mr_settings_ena_reg <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 202:

202: mr_settings_ena_reg_2 <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 204:

204: mr_settings_ena_reg <= mr_settings_ena;
Count: 543791678
Threshold: 1

Signal assignment statement on line 205:

205: mr_settings_ena_reg_2 <= mr_settings_ena_reg;
Count: 543791678
Threshold: 1

If statement on lines 210 to 211:

210:    capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else 
211:               '0';

Count: 30710
Threshold: 1

Signal assignment statement on line 210:

210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else
Count: 9714
Threshold: 1

Signal assignment statement on line 211:

211: '0';
Count: 20996
Threshold: 1

If statement on lines 215 to 216:

215:    start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else 
216:                  '0';

Count: 25877
Threshold: 1

Signal assignment statement on line 215:

215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else
Count: 6482
Threshold: 1

Signal assignment statement on line 216:

216: '0';
Count: 19395
Threshold: 1

Signal assignment statement on line 221:

221: tseg2_nbt <= std_logic_vector(resize(unsigned(mr_btr_ph2), G_TSEG2_NBT_WIDTH));
Count: 10699
Threshold: 1

Signal assignment statement on line 222:

222: tseg2_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_ph2_fd),G_TSEG2_DBT_WIDTH));
Count: 10093
Threshold: 1

Signal assignment statement on line 227:

227: sjw_nbt <= std_logic_vector(resize(unsigned(mr_btr_sjw), G_SJW_NBT_WIDTH));
Count: 10049
Threshold: 1

Signal assignment statement on line 228:

228: sjw_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_sjw_fd), G_SJW_DBT_WIDTH));
Count: 5738
Threshold: 1

Signal assignment statement on line 233:

233: brp_nbt <= std_logic_vector(resize(unsigned(mr_btr_brp), G_BRP_NBT_WIDTH));
Count: 9788
Threshold: 1

Signal assignment statement on line 234:

234: brp_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_brp_fd), G_BRP_DBT_WIDTH));
Count: 9787
Threshold: 1

Signal assignment statement on lines 239 to 242:

239:    tseg1_nbt_d   <= std_logic_vector( 
240:                        resize(unsigned(mr_btr_prop),       G_TSEG1_NBT_WIDTH) + 
241:                        resize(unsigned(mr_btr_ph1),        G_TSEG1_NBT_WIDTH) + 
242:                        resize(sync_length,                 G_TSEG1_NBT_WIDTH));

Count: 10820
Threshold: 1

Signal assignment statement on lines 244 to 247:

244:    tseg1_dbt_d   <= std_logic_vector( 
245:                        resize(unsigned(mr_btr_fd_prop_fd), G_TSEG1_DBT_WIDTH) + 
246:                        resize(unsigned(mr_btr_fd_ph1_fd),  G_TSEG1_DBT_WIDTH) + 
247:                        resize(sync_length,                 G_TSEG1_DBT_WIDTH));

Count: 10125
Threshold: 1

If statement on lines 254 to 265:

254:        if (res_n = '0') then 
255:            -- Matching reset values to what is in Memory registers. 
...
264:            end if; 
265:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 258:

258: tseg1_nbt <= std_logic_vector(to_unsigned(9, G_TSEG1_NBT_WIDTH));
Count: 2424883
Threshold: 1

Signal assignment statement on line 259:

259: tseg1_dbt <= std_logic_vector(to_unsigned(7, G_TSEG1_DBT_WIDTH));
Count: 2424883
Threshold: 1

If statement on lines 261 to 264:

261:            if (capture = '1') then 
262:                tseg1_nbt <= tseg1_nbt_d; 
263:                tseg1_dbt <= tseg1_dbt_d; 
264:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 262:

262: tseg1_nbt <= tseg1_nbt_d;
Count: 6483
Threshold: 1

Signal assignment statement on line 263:

263: tseg1_dbt <= tseg1_dbt_d;
Count: 6483
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 200:

200: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 203:

203: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 210:

210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else

	Evaluated to	Count	Threshold
Bin	True	9714	1
Bin	False	20996	1

"if" / "when" / "else" condition on line 215:

215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else

	Evaluated to	Count	Threshold
Bin	True	6482	1
Bin	False	19395	1

"if" / "when" / "else" condition on line 254:

254: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 260:

260: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 261:

261: if (capture = '1') then

	Evaluated to	Count	Threshold
Bin	True	6483	1
Bin	False	543785195	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_BTR_PROP

	Element	From	To	Threshold	Excluded due to
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_PH1

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_PH2

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_SJW

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PROP_FD

	Element	From	To	Threshold	Excluded due to
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PH1_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_PH2_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_BRP_FD

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_BTR_FD_SJW_FD

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TSEG1_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	457	1
Bin	(7)	1	0	2056	1
Bin	(6)	0	1	1689	1
Bin	(6)	1	0	3290	1
Bin	(5)	0	1	807	1
Bin	(5)	1	0	2406	1
Bin	(4)	0	1	934	1
Bin	(4)	1	0	2533	1
Bin	(3)	0	1	5981	1
Bin	(3)	1	0	4381	1
Bin	(2)	0	1	4191	1
Bin	(2)	1	0	5782	1
Bin	(1)	0	1	1064	1
Bin	(1)	1	0	2662	1
Bin	(0)	0	1	3761	1
Bin	(0)	1	0	2160	1

Port:

TSEG2_NBT

	Element	From	To	Count	Threshold
Bin	(5)	0	1	204	1
Bin	(5)	1	0	1803	1
Bin	(4)	0	1	349	1
Bin	(4)	1	0	1947	1
Bin	(3)	0	1	313	1
Bin	(3)	1	0	1912	1
Bin	(2)	0	1	3874	1
Bin	(2)	1	0	2275	1
Bin	(1)	0	1	3412	1
Bin	(1)	1	0	5003	1
Bin	(0)	0	1	2160	1
Bin	(0)	1	0	559	1

Port:

BRP_NBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	13	1
Bin	(7)	1	0	1614	1
Bin	(6)	0	1	14	1
Bin	(6)	1	0	1615	1
Bin	(5)	0	1	12	1
Bin	(5)	1	0	1613	1
Bin	(4)	0	1	16	1
Bin	(4)	1	0	1617	1
Bin	(3)	0	1	4831	1
Bin	(3)	1	0	3242	1
Bin	(2)	0	1	930	1
Bin	(2)	1	0	2524	1
Bin	(1)	0	1	4762	1
Bin	(1)	1	0	3170	1
Bin	(0)	0	1	2317	1
Bin	(0)	1	0	3915	1

Port:

SJW_NBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	204	1
Bin	(4)	1	0	1802	1
Bin	(3)	0	1	271	1
Bin	(3)	1	0	1869	1
Bin	(2)	0	1	971	1
Bin	(2)	1	0	2568	1
Bin	(1)	0	1	2624	1
Bin	(1)	1	0	1032	1
Bin	(0)	0	1	3116	1
Bin	(0)	1	0	4713	1

Port:

TSEG1_DBT

	Element	From	To	Count	Threshold
Bin	(6)	0	1	2330	1
Bin	(6)	1	0	3929	1
Bin	(5)	0	1	267	1
Bin	(5)	1	0	1868	1
Bin	(4)	0	1	2412	1
Bin	(4)	1	0	4011	1
Bin	(3)	0	1	3645	1
Bin	(3)	1	0	5235	1
Bin	(2)	0	1	4399	1
Bin	(2)	1	0	2798	1
Bin	(1)	0	1	3281	1
Bin	(1)	1	0	1689	1
Bin	(0)	0	1	2073	1
Bin	(0)	1	0	472	1

Port:

TSEG2_DBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	288	1
Bin	(4)	1	0	1887	1
Bin	(3)	0	1	315	1
Bin	(3)	1	0	1914	1
Bin	(2)	0	1	1212	1
Bin	(2)	1	0	2802	1
Bin	(1)	0	1	1734	1
Bin	(1)	1	0	134	1
Bin	(0)	0	1	3870	1
Bin	(0)	1	0	2269	1

Port:

BRP_DBT

	Element	From	To	Count	Threshold
Bin	(7)	0	1	18	1
Bin	(7)	1	0	1619	1
Bin	(6)	0	1	29	1
Bin	(6)	1	0	1630	1
Bin	(5)	0	1	17	1
Bin	(5)	1	0	1618	1
Bin	(4)	0	1	30	1
Bin	(4)	1	0	1631	1
Bin	(3)	0	1	27	1
Bin	(3)	1	0	1628	1
Bin	(2)	0	1	4843	1
Bin	(2)	1	0	3254	1
Bin	(1)	0	1	757	1
Bin	(1)	1	0	2355	1
Bin	(0)	0	1	2600	1
Bin	(0)	1	0	4192	1

Port:

SJW_DBT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	247	1
Bin	(4)	1	0	1845	1
Bin	(3)	0	1	289	1
Bin	(3)	1	0	1887	1
Bin	(2)	0	1	916	1
Bin	(2)	1	0	2513	1
Bin	(1)	0	1	2568	1
Bin	(1)	1	0	976	1
Bin	(0)	0	1	953	1
Bin	(0)	1	0	2550	1

Port:

START_EDGE

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8083	1

Signal:

TSEG1_NBT_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	200	1
Bin	(7)	1	0	1799	1
Bin	(6)	0	1	128	1
Bin	(6)	1	0	1728	1
Bin	(5)	0	1	223	1
Bin	(5)	1	0	1822	1
Bin	(4)	0	1	300	1
Bin	(4)	1	0	1899	1
Bin	(3)	0	1	3871	1
Bin	(3)	1	0	2272	1
Bin	(2)	0	1	3312	1
Bin	(2)	1	0	4903	1
Bin	(1)	0	1	522	1
Bin	(1)	1	0	2120	1
Bin	(0)	0	1	2203	1
Bin	(0)	1	0	603	1

Signal:

TSEG1_DBT_D

	Element	From	To	Count	Threshold
Bin	(6)	0	1	218	1
Bin	(6)	1	0	1816	1
Bin	(5)	0	1	94	1
Bin	(5)	1	0	1695	1
Bin	(4)	0	1	276	1
Bin	(4)	1	0	1875	1
Bin	(3)	0	1	1132	1
Bin	(3)	1	0	2722	1
Bin	(2)	0	1	3848	1
Bin	(2)	1	0	2248	1
Bin	(1)	0	1	2611	1
Bin	(1)	1	0	1020	1
Bin	(0)	0	1	1815	1
Bin	(0)	1	0	215	1

Signal:

MR_SETTINGS_ENA_REG

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Signal:

MR_SETTINGS_ENA_REG_2

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Signal:

CAPTURE

	From	To	Count	Threshold
Bin	0	1	9714	1
Bin	1	0	11314	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_CFG_CAPTURE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 200 to 206:

Signal assignment statement on line 201:

Signal assignment statement on line 202:

Signal assignment statement on line 204:

Signal assignment statement on line 205:

If statement on lines 210 to 211:

Signal assignment statement on line 210:

Signal assignment statement on line 211:

If statement on lines 215 to 216:

Signal assignment statement on line 215:

Signal assignment statement on line 216:

Signal assignment statement on line 221:

Signal assignment statement on line 222:

Signal assignment statement on line 227:

Signal assignment statement on line 228:

Signal assignment statement on line 233:

Signal assignment statement on line 234:

Signal assignment statement on lines 239 to 242:

Signal assignment statement on lines 244 to 247:

If statement on lines 254 to 265:

Signal assignment statement on line 258:

Signal assignment statement on line 259:

If statement on lines 261 to 264:

Signal assignment statement on line 262:

Signal assignment statement on line 263:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 200:

"if" / "when" / "else" condition on line 203:

"if" / "when" / "else" condition on line 210:

"if" / "when" / "else" condition on line 215:

"if" / "when" / "else" condition on line 254:

"if" / "when" / "else" condition on line 260:

"if" / "when" / "else" condition on line 261:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 200:

"and" expression on line 210:

"=" expression on line 210:

"=" expression on line 210: