Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_CFG_CAPTURE_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
200: if (res_n = '0') then
201: mr_settings_ena_reg <= '0';
...
205: mr_settings_ena_reg_2 <= mr_settings_ena_reg;
206: end if; Count: 1055177083
Threshold: 1
Signal assignment statement:
201: mr_settings_ena_reg <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
202: mr_settings_ena_reg_2 <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
204: mr_settings_ena_reg <= mr_settings_ena; Count: 526374300
Threshold: 1
Signal assignment statement:
205: mr_settings_ena_reg_2 <= mr_settings_ena_reg; Count: 526374300
Threshold: 1
If statement:
210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else
211: '0'; Count: 30707
Threshold: 1
Signal assignment statement:
210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else Count: 9714
Threshold: 1
Signal assignment statement:
211: '0'; Count: 20993
Threshold: 1
If statement:
215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else
216: '0'; Count: 25874
Threshold: 1
Signal assignment statement:
215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else Count: 6481
Threshold: 1
Signal assignment statement:
216: '0'; Count: 19393
Threshold: 1
Signal assignment statement:
221: tseg2_nbt <= std_logic_vector(resize(unsigned(mr_btr_ph2), G_TSEG2_NBT_WIDTH)); Count: 10697
Threshold: 1
Signal assignment statement:
222: tseg2_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_ph2_fd),G_TSEG2_DBT_WIDTH)); Count: 10091
Threshold: 1
Signal assignment statement:
227: sjw_nbt <= std_logic_vector(resize(unsigned(mr_btr_sjw), G_SJW_NBT_WIDTH)); Count: 10045
Threshold: 1
Signal assignment statement:
228: sjw_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_sjw_fd), G_SJW_DBT_WIDTH)); Count: 5736
Threshold: 1
Signal assignment statement:
233: brp_nbt <= std_logic_vector(resize(unsigned(mr_btr_brp), G_BRP_NBT_WIDTH)); Count: 9787
Threshold: 1
Signal assignment statement:
234: brp_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_brp_fd), G_BRP_DBT_WIDTH)); Count: 9786
Threshold: 1
Signal assignment statement:
239: tseg1_nbt_d <= std_logic_vector(
240: resize(unsigned(mr_btr_prop), G_TSEG1_NBT_WIDTH) +
241: resize(unsigned(mr_btr_ph1), G_TSEG1_NBT_WIDTH) +
242: resize(sync_length, G_TSEG1_NBT_WIDTH)); Count: 10818
Threshold: 1
Signal assignment statement:
244: tseg1_dbt_d <= std_logic_vector(
245: resize(unsigned(mr_btr_fd_prop_fd), G_TSEG1_DBT_WIDTH) +
246: resize(unsigned(mr_btr_fd_ph1_fd), G_TSEG1_DBT_WIDTH) +
247: resize(sync_length, G_TSEG1_DBT_WIDTH)); Count: 10123
Threshold: 1
If statement:
254: if (res_n = '0') then
255: -- Matching reset values to what is in Memory registers.
...
264: end if;
265: end if; Count: 1055177083
Threshold: 1
Signal assignment statement:
258: tseg1_nbt <= std_logic_vector(to_unsigned(9, G_TSEG1_NBT_WIDTH)); Count: 2418499
Threshold: 1
Signal assignment statement:
259: tseg1_dbt <= std_logic_vector(to_unsigned(7, G_TSEG1_DBT_WIDTH)); Count: 2418499
Threshold: 1
If statement:
261: if (capture = '1') then
262: tseg1_nbt <= tseg1_nbt_d;
263: tseg1_dbt <= tseg1_dbt_d;
264: end if; Count: 526374300
Threshold: 1
Signal assignment statement:
262: tseg1_nbt <= tseg1_nbt_d; Count: 6482
Threshold: 1
Signal assignment statement:
263: tseg1_dbt <= tseg1_dbt_d; Count: 6482
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
200: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2418499 | 1 |
| Bin | False | 1052758584 | 1 |
"if" / "when" / "else" condition:
203: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526374300 | 1 |
| Bin | False | 526384284 | 1 |
"if" / "when" / "else" condition:
210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 9714 | 1 |
| Bin | False | 20993 | 1 |
"if" / "when" / "else" condition:
215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 6481 | 1 |
| Bin | False | 19393 | 1 |
"if" / "when" / "else" condition:
254: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2418499 | 1 |
| Bin | False | 1052758584 | 1 |
"if" / "when" / "else" condition:
260: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526374300 | 1 |
| Bin | False | 526384284 | 1 |
"if" / "when" / "else" condition:
261: if (capture = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 6482 | 1 |
| Bin | False | 526367818 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
MR_SETTINGS_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
MR_BTR_PROP(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
Port:
MR_BTR_PROP(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 312 | 1 |
| Bin | 1 | 0 | 1909 | 1 |
Port:
MR_BTR_PROP(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 223 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
Port:
MR_BTR_PROP(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 273 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
Port:
MR_BTR_PROP(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3820 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
Port:
MR_BTR_PROP(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 261 | 1 |
| Bin | 1 | 0 | 1858 | 1 |
Port:
MR_BTR_PROP(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1793 | 1 |
| Bin | 1 | 0 | 194 | 1 |
Port:
MR_BTR_PH1(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 316 | 1 |
| Bin | 1 | 0 | 1914 | 1 |
Port:
MR_BTR_PH1(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 250 | 1 |
| Bin | 1 | 0 | 1848 | 1 |
Port:
MR_BTR_PH1(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 259 | 1 |
| Bin | 1 | 0 | 1857 | 1 |
Port:
MR_BTR_PH1(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1304 | 1 |
| Bin | 1 | 0 | 2896 | 1 |
Port:
MR_BTR_PH1(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1927 | 1 |
| Bin | 1 | 0 | 328 | 1 |
Port:
MR_BTR_PH1(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2088 | 1 |
| Bin | 1 | 0 | 490 | 1 |
Port:
MR_BTR_PH2(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 204 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Port:
MR_BTR_PH2(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 347 | 1 |
| Bin | 1 | 0 | 1944 | 1 |
Port:
MR_BTR_PH2(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 314 | 1 |
| Bin | 1 | 0 | 1912 | 1 |
Port:
MR_BTR_PH2(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3872 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
Port:
MR_BTR_PH2(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3411 | 1 |
| Bin | 1 | 0 | 5003 | 1 |
Port:
MR_BTR_PH2(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2161 | 1 |
| Bin | 1 | 0 | 561 | 1 |
Port:
MR_BTR_BRP(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
Port:
MR_BTR_BRP(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12 | 1 |
| Bin | 1 | 0 | 1612 | 1 |
Port:
MR_BTR_BRP(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
Port:
MR_BTR_BRP(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 1617 | 1 |
Port:
MR_BTR_BRP(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4831 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Port:
MR_BTR_BRP(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 928 | 1 |
| Bin | 1 | 0 | 2523 | 1 |
Port:
MR_BTR_BRP(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4762 | 1 |
| Bin | 1 | 0 | 3169 | 1 |
Port:
MR_BTR_BRP(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2315 | 1 |
| Bin | 1 | 0 | 3912 | 1 |
Port:
MR_BTR_SJW(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Port:
MR_BTR_SJW(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 269 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
Port:
MR_BTR_SJW(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 966 | 1 |
| Bin | 1 | 0 | 2563 | 1 |
Port:
MR_BTR_SJW(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2625 | 1 |
| Bin | 1 | 0 | 1032 | 1 |
Port:
MR_BTR_SJW(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3116 | 1 |
| Bin | 1 | 0 | 4713 | 1 |
Port:
MR_BTR_FD_PROP_FD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 1840 | 1 |
Port:
MR_BTR_FD_PROP_FD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 286 | 1 |
| Bin | 1 | 0 | 1883 | 1 |
Port:
MR_BTR_FD_PROP_FD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
Port:
MR_BTR_FD_PROP_FD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1185 | 1 |
| Bin | 1 | 0 | 2775 | 1 |
Port:
MR_BTR_FD_PROP_FD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4706 | 1 |
| Bin | 1 | 0 | 3113 | 1 |
Port:
MR_BTR_FD_PROP_FD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3890 | 1 |
| Bin | 1 | 0 | 2290 | 1 |
Port:
MR_BTR_FD_PH1_FD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 253 | 1 |
| Bin | 1 | 0 | 1851 | 1 |
Port:
MR_BTR_FD_PH1_FD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 284 | 1 |
| Bin | 1 | 0 | 1882 | 1 |
Port:
MR_BTR_FD_PH1_FD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1179 | 1 |
| Bin | 1 | 0 | 2770 | 1 |
Port:
MR_BTR_FD_PH1_FD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1697 | 1 |
| Bin | 1 | 0 | 98 | 1 |
Port:
MR_BTR_FD_PH1_FD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3840 | 1 |
| Bin | 1 | 0 | 2241 | 1 |
Port:
MR_BTR_FD_PH2_FD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 281 | 1 |
| Bin | 1 | 0 | 1879 | 1 |
Port:
MR_BTR_FD_PH2_FD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 321 | 1 |
| Bin | 1 | 0 | 1919 | 1 |
Port:
MR_BTR_FD_PH2_FD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1212 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
Port:
MR_BTR_FD_PH2_FD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1732 | 1 |
| Bin | 1 | 0 | 133 | 1 |
Port:
MR_BTR_FD_PH2_FD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3871 | 1 |
| Bin | 1 | 0 | 2271 | 1 |
Port:
MR_BTR_FD_BRP_FD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
Port:
MR_BTR_FD_BRP_FD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
Port:
MR_BTR_FD_BRP_FD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
Port:
MR_BTR_FD_BRP_FD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
Port:
MR_BTR_FD_BRP_FD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
Port:
MR_BTR_FD_BRP_FD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4843 | 1 |
| Bin | 1 | 0 | 3253 | 1 |
Port:
MR_BTR_FD_BRP_FD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 758 | 1 |
| Bin | 1 | 0 | 2356 | 1 |
Port:
MR_BTR_FD_BRP_FD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2600 | 1 |
| Bin | 1 | 0 | 4192 | 1 |
Port:
MR_BTR_FD_SJW_FD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236 | 1 |
| Bin | 1 | 0 | 1833 | 1 |
Port:
MR_BTR_FD_SJW_FD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
Port:
MR_BTR_FD_SJW_FD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 929 | 1 |
| Bin | 1 | 0 | 2526 | 1 |
Port:
MR_BTR_FD_SJW_FD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2558 | 1 |
| Bin | 1 | 0 | 965 | 1 |
Port:
MR_BTR_FD_SJW_FD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 949 | 1 |
| Bin | 1 | 0 | 2546 | 1 |
Port:
TSEG1_NBT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 456 | 1 |
| Bin | 1 | 0 | 2054 | 1 |
Port:
TSEG1_NBT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1689 | 1 |
| Bin | 1 | 0 | 3289 | 1 |
Port:
TSEG1_NBT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 806 | 1 |
| Bin | 1 | 0 | 2404 | 1 |
Port:
TSEG1_NBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 935 | 1 |
| Bin | 1 | 0 | 2533 | 1 |
Port:
TSEG1_NBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5981 | 1 |
| Bin | 1 | 0 | 4382 | 1 |
Port:
TSEG1_NBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4192 | 1 |
| Bin | 1 | 0 | 5784 | 1 |
Port:
TSEG1_NBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1067 | 1 |
| Bin | 1 | 0 | 2664 | 1 |
Port:
TSEG1_NBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3759 | 1 |
| Bin | 1 | 0 | 2159 | 1 |
Port:
TSEG2_NBT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 204 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Port:
TSEG2_NBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 347 | 1 |
| Bin | 1 | 0 | 1944 | 1 |
Port:
TSEG2_NBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 314 | 1 |
| Bin | 1 | 0 | 1912 | 1 |
Port:
TSEG2_NBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3872 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
Port:
TSEG2_NBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3411 | 1 |
| Bin | 1 | 0 | 5003 | 1 |
Port:
TSEG2_NBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2161 | 1 |
| Bin | 1 | 0 | 561 | 1 |
Port:
BRP_NBT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
Port:
BRP_NBT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12 | 1 |
| Bin | 1 | 0 | 1612 | 1 |
Port:
BRP_NBT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
Port:
BRP_NBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 1617 | 1 |
Port:
BRP_NBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4831 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Port:
BRP_NBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 928 | 1 |
| Bin | 1 | 0 | 2523 | 1 |
Port:
BRP_NBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4762 | 1 |
| Bin | 1 | 0 | 3169 | 1 |
Port:
BRP_NBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2315 | 1 |
| Bin | 1 | 0 | 3912 | 1 |
Port:
SJW_NBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
Port:
SJW_NBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 269 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
Port:
SJW_NBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 966 | 1 |
| Bin | 1 | 0 | 2563 | 1 |
Port:
SJW_NBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2625 | 1 |
| Bin | 1 | 0 | 1032 | 1 |
Port:
SJW_NBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3116 | 1 |
| Bin | 1 | 0 | 4713 | 1 |
Port:
TSEG1_DBT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2332 | 1 |
| Bin | 1 | 0 | 3930 | 1 |
Port:
TSEG1_DBT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 269 | 1 |
| Bin | 1 | 0 | 1869 | 1 |
Port:
TSEG1_DBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2406 | 1 |
| Bin | 1 | 0 | 4004 | 1 |
Port:
TSEG1_DBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3646 | 1 |
| Bin | 1 | 0 | 5237 | 1 |
Port:
TSEG1_DBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4395 | 1 |
| Bin | 1 | 0 | 2795 | 1 |
Port:
TSEG1_DBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3285 | 1 |
| Bin | 1 | 0 | 1692 | 1 |
Port:
TSEG1_DBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2074 | 1 |
| Bin | 1 | 0 | 474 | 1 |
Port:
TSEG2_DBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 281 | 1 |
| Bin | 1 | 0 | 1879 | 1 |
Port:
TSEG2_DBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 321 | 1 |
| Bin | 1 | 0 | 1919 | 1 |
Port:
TSEG2_DBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1212 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
Port:
TSEG2_DBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1732 | 1 |
| Bin | 1 | 0 | 133 | 1 |
Port:
TSEG2_DBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3871 | 1 |
| Bin | 1 | 0 | 2271 | 1 |
Port:
BRP_DBT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
Port:
BRP_DBT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
Port:
BRP_DBT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
Port:
BRP_DBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
Port:
BRP_DBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
Port:
BRP_DBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4843 | 1 |
| Bin | 1 | 0 | 3253 | 1 |
Port:
BRP_DBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 758 | 1 |
| Bin | 1 | 0 | 2356 | 1 |
Port:
BRP_DBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2600 | 1 |
| Bin | 1 | 0 | 4192 | 1 |
Port:
SJW_DBT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236 | 1 |
| Bin | 1 | 0 | 1833 | 1 |
Port:
SJW_DBT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
Port:
SJW_DBT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 929 | 1 |
| Bin | 1 | 0 | 2526 | 1 |
Port:
SJW_DBT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2558 | 1 |
| Bin | 1 | 0 | 965 | 1 |
Port:
SJW_DBT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 949 | 1 |
| Bin | 1 | 0 | 2546 | 1 |
Port:
START_EDGE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 8081 | 1 |
Signal:
TSEG1_NBT_D(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 200 | 1 |
| Bin | 1 | 0 | 1798 | 1 |
Signal:
TSEG1_NBT_D(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126 | 1 |
| Bin | 1 | 0 | 1725 | 1 |
Signal:
TSEG1_NBT_D(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 226 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
Signal:
TSEG1_NBT_D(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 302 | 1 |
| Bin | 1 | 0 | 1900 | 1 |
Signal:
TSEG1_NBT_D(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3870 | 1 |
| Bin | 1 | 0 | 2272 | 1 |
Signal:
TSEG1_NBT_D(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3311 | 1 |
| Bin | 1 | 0 | 4903 | 1 |
Signal:
TSEG1_NBT_D(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 525 | 1 |
| Bin | 1 | 0 | 2122 | 1 |
Signal:
TSEG1_NBT_D(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2202 | 1 |
| Bin | 1 | 0 | 603 | 1 |
Signal:
TSEG1_DBT_D(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 220 | 1 |
| Bin | 1 | 0 | 1817 | 1 |
Signal:
TSEG1_DBT_D(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
Signal:
TSEG1_DBT_D(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 268 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
Signal:
TSEG1_DBT_D(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1138 | 1 |
| Bin | 1 | 0 | 2729 | 1 |
Signal:
TSEG1_DBT_D(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3845 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
Signal:
TSEG1_DBT_D(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2610 | 1 |
| Bin | 1 | 0 | 1018 | 1 |
Signal:
TSEG1_DBT_D(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1817 | 1 |
| Bin | 1 | 0 | 218 | 1 |
Signal:
MR_SETTINGS_ENA_REG | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Signal:
MR_SETTINGS_ENA_REG_2 | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6481 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Signal:
CAPTURE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9714 | 1 |
| Bin | 1 | 0 | 11313 | 1 |
Covered expressions:
"=" expression
200: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052758584 | 1 |
| Bin | True | 2418499 | 1 |
"=" expression
210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 14512 | 1 |
| Bin | True | 16195 | 1 |
"=" expression
210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 11321 | 1 |
| Bin | True | 19386 | 1 |
"and" expression
210: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else
<--------LHS--------> <----------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 9672 | 1 |
| Bin | True | False | 6481 | 1 |
| Bin | True | True | 9714 | 1 |
"=" expression
215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 11321 | 1 |
| Bin | True | 14553 | 1 |
"=" expression
215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 12912 | 1 |
| Bin | True | 12962 | 1 |
"and" expression
215: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else
<-----------LHS-----------> <----------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 6481 | 1 |
| Bin | True | False | 8072 | 1 |
| Bin | True | True | 6481 | 1 |
"=" expression
254: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052758584 | 1 |
| Bin | True | 2418499 | 1 |
"=" expression
261: if (capture = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 526367818 | 1 |
| Bin | True | 6482 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: